CN107170816B - A kind of landscape insulation bar double-pole-type transistor - Google Patents

Abstract

The invention belongs to semiconductor power device technology fields, particularly relate to a kind of landscape insulation bar double-pole-type transistor.The present invention is by forming three-dimensional structure along orientation etching groove in device surface, forming the landscape insulation bar double-pole-type transistor with three-dimensional structure on the basis of traditional landscape insulation bar double-pole-type transistor；Polycrystalline diode is formed on device three-dimensional drift region surface simultaneously and three-dimensional PMOS and Zener diode are integrated near collector.Structure of the invention has forward conduction voltage drop more lower than traditional LIGBT and negative resistance phenomenon is not present in turn on process, while having higher device electric breakdown strength, faster turn-off speed and lower turn-off power loss.

Description

A Lateral Insulated Gate Bipolar Transistor

technical field

The invention belongs to the technical field of semiconductor power devices, and in particular relates to a lateral insulated gate bipolar transistor.

Background technique

Insulated gate bipolar transistor (IGBT) is a new type of power electronic device combined with MOS field effect and bipolar transistor. The advantages of large current and low loss have become the mainstream power switching devices in the field of medium and high power power electronics, and are widely used in various fields of the national economy such as communications, energy, transportation, industry, medicine, household appliances, and aerospace. Internationally well-known semiconductor companies, such as ABB, Infineon (IR), ST, Renesas, Mitsubishi, FuJi, etc. have successively invested in the R&D and manufacturing of IGBTs. In recent years, as a hot field of power electronics, IGBT has received great attention from developed countries and regions such as the United States, Japan and Europe.

During the conduction process of the IGBT, electrons enter the N-type drift region through the MOS channel, which causes the P-type collector region to inject a large number of holes into the drift region. Therefore, a large number of excess electron-hole pairs are stored in the drift region of the IGBT in the on state, and these electron-hole pairs form a conductance modulation effect, which greatly reduces the resistance of the drift region, thereby reducing the forward voltage drop VCE. In practical applications, in order to reduce the on-state loss, it is always hoped that the lower the VCE, the better. However, the lower the VCE, the stronger the conductance modulation effect, and the more excess electron-hole pairs in the drift region. These large numbers of electron-hole pairs need to be fully extracted and recombined during the turn-off process of the IGBT, resulting in turn-off The loss EOFF increases. VCE and EOFF are a set of important compromise relations of IGBT, which are directly related to the size of on-state loss and turn-off loss. The change of each generation of IGBT products includes the optimization of this compromise relationship.

At present, silicon-on-insulator (SOI) technology is widely used in lateral power devices to reduce parasitic capacitance, suppress substrate current, and eliminate latch-up effects caused by the substrate. Its typical preparation process includes oxygen injection isolation SIMOX technology, bonding technology and Smart-Cut technology, etc. Lateral IGBT (LIGBT) is widely used in power integrated ICs (PICs) and smart power ICs due to its advantages of low gate drive power, strong current handling capability, and easy integration. Its basic structure is shown in Figure 1. Due to the need to extract excess carriers in the drift region during the turn-off process, the turn-off time is longer and the turn-off loss is larger, which limits the application of LIGBT in the high-frequency field. In order to improve the VCE-EOFF trade-off relationship of LIGBT, the most effective method is to increase the electron extraction path during the turn-off process to reduce the falling time of the current. The typical structure is the anode short circuit (SA-LIGBT) structure, as shown in Figure 2 Show. However, when the structure is in forward conduction, electrons reach the collector through the N+ emitter region 5, the surface channel of the P-type body region 4, the low-doped N-type drift region 3, and the collector N+ region 8, forming a parasitic MOS structure. The generation of an electronic current path will cause the conduction curve to show a negative resistance phenomenon, weaken the conductance modulation effect in the drift region, and increase the forward conduction voltage drop, which is not conducive to the practical application of the device.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a high-speed and low-loss lateral insulated gate bipolar transistor. The structure of the present invention forms a three-dimensional structure by etching grooves on the surface of the device along the channel length direction on the basis of the traditional lateral insulated gate bipolar transistor, and forms a lateral insulated gate bipolar transistor with a three-dimensional structure; A polycrystalline diode is formed on the surface of the region and a three-dimensional PMOS and Zener diode are integrated near the collector. In the blocking state, the charge and the three-dimensional field plate provided by the depletion of the drift region in the reverse-biased state of the three-dimensional polycrystalline diode on the surface of the device can increase the doping concentration of the drift region of the LIGBT device and obtain a higher density than the traditional LIGBT structure. Withstand voltage; in the process of turning off the device, as the collector voltage increases, the PMOS near the collector is automatically turned on and turned on by using the change of the collector voltage and the self-bias effect formed by the surface polycrystalline diode and the Zener diode , forming an electron current path at the collector terminal, speeding up the carrier extraction inside the LIGBT, and at the same time, the charge provided by the depletion of the drift region of the three-dimensional polycrystalline diode and the effect of the three-dimensional field plate accelerate the depletion layer in the drift region of the device in the direction perpendicular to the channel length The expansion of LIGBT further accelerates the carrier extraction inside the LIGBT device, thereby increasing the turn-off speed of the device and further reducing the turn-off loss of the device; in the on-state, the collector voltage is low, and the surface polycrystalline diode and Zener diode The self-bias effect formed by the collector (or diode string) makes the PMOS near the collector in the off state, and the electronic current path is cut off. The existence of the additional structure will not affect the forward conduction characteristics of the device, and there is no negative conduction during the conduction process. At the same time, the three-dimensional tri-gate structure increases the equivalent width of the gate structure, further reducing the forward conduction voltage drop of the device. Therefore, the structure of the present invention has lower forward conduction voltage drop than traditional LIGBT and does not have negative resistance phenomenon in the conduction process, and has higher device breakdown voltage, faster turn-off speed and lower turn-off break loss. The structure of the present invention is applicable not only to N-type LIGBT devices, but also to P-type LIGBT devices, and it is only necessary to exchange the doping types of materials in the structure between N and P. For the convenience of description, only an N-type LIGBT device is used as an example for illustration below.

The technical solution of the present invention is: as shown in FIG. 3 , a lateral insulated gate bipolar transistor, its half-cell structure includes a substrate 1, an insulating layer 2 and a first N-type low-doped transistor stacked sequentially from bottom to top. The impurity region 3; it is characterized in that, along the longitudinal direction of the device, the first N-type low-doped region 3 is in the shape of two steps, and the vertical height of the second step is defined to be greater than that of the first step, and the first N-type There are P-type body regions 4 and N-type buffer regions 7 on both sides of the upper layer of the low-doped region 3, and along the longitudinal direction of the device, the P-type body regions 4 and N-type buffer regions 7 are in the shape of two steps; There is a second N-type low-doped region 150 between the second step of the N-type low-doped region 3 and the second step of the P-type body region 4 and the N-type buffer zone 7; the upper layer of the P-type body region 4 has mutual The P+ contact area 6 and the N+ emission area 5 arranged side by side, wherein the N+ emission area 5 is located on the side close to the N-type buffer zone 7, and the P+ contact area 6 and the N+ emission area 5 are both in the shape of two steps; the P+ The upper surface of the contact region 6 and part of the N+ emitter region 5 has an emitter metal electrode 130, and the emitter metal electrode 130 is in the shape of two steps; the upper surface of the P-type body region 4 has a first gate structure, and the first A gate structure is composed of a first gate dielectric layer 110 and a first polysilicon gate electrode 120 located on the upper surface of the first gate dielectric layer 110. Along the longitudinal direction of the device, the lower surface of the first gate dielectric layer 110 is sequentially connected to the The upper surface of the first step of the first N-type low-doped region 3 is in contact with the upper surface and side surfaces of the second N-type low-doped region 150, and the lower surface of the first gate dielectric layer 110 is also in contact with the upper surface of part of the N+ emitter region 5. Surface contact, the upper surface of the first polysilicon gate electrode 120 is a horizontal plane or two-level ladder shape; the N-type buffer zone 7 has a P-type collector region 8, a highly doped N+ region 9 and a highly doped P+ region 10. The highly doped N+ region 9 and the highly doped P+ region 10 are in contact with each other, and the highly doped N+ region 9 is located on the side close to the P-type body region 4; the P-type collector region 8, the highly doped N+ region 9 and the highly doped P+ region 10 are both in the shape of two steps; the upper surface of the P-type collector region 8 has a collector metal electrode 131 on the side away from the P-type body region 4, and the collector metal electrode 131 is a two-step step shape; the upper surface of the highly doped N+ region 9 and the highly doped P+ region 10 has a metal electrode 132, and the metal electrode 132 is in a two-level ladder shape; the upper surface of the N-type buffer zone 7 has a second gate Pole structure, the second gate structure is composed of a second gate dielectric layer 111 and a second polysilicon electrode 124 located on the upper surface of the second gate dielectric layer 111, along the longitudinal direction of the device, the second gate dielectric layer 111 The lower surface of the second gate dielectric layer 111 is in contact with the upper surface of the first step of the first N-type low-doped region 3 and the upper surface and side surfaces of the second N-type low-doped region 150 in turn, and the lower surface of the second gate dielectric layer 111 is also in contact with the portion P type collector region 8 is in contact with the upper surface of the highly doped P+ region 10, and the upper surface of the second polysilicon electrode 124 is a horizontal plane or a two-level ladder shape; between the P type body region 4 and the N type buffer region 7 The upper surface of the device between has a dielectric layer 112, along the longitudinal direction of the device, the dielectric layer 1 The lower surface of 12 is sequentially in contact with the upper surface of the first step of the first N-type low-doped region 3 and the upper surface of the second N-type low-doped region 150, and the lower surface of the dielectric layer 112 is also in contact with part of the N-type buffer The upper surface of the region 7 is in contact; the upper surface of the dielectric layer 112 has a polysilicon P+ region 121, a P-type region 122 and an N+ region 123, wherein the P-type region 122 is located between the polysilicon P+ region 121 and the N+ region 123 and is connected to each other to form a polysilicon In the diode, the P+ region 121 is located on the side close to the P-type body region 4, and the N+ region 123 is located on the side close to the N-type buffer zone 7. Along the longitudinal direction of the device, the upper surfaces of the polysilicon P+ region 121, the P-type region 122 and the N+ region 123 It is a horizontal plane or a two-level ladder shape; the emitter metal electrode 130 is electrically connected to the polysilicon P+ region 121, the polysilicon N+ region 123 is electrically connected to the second polysilicon electrode 124, and the polysilicon N+ region 123 It is electrically connected with the second polysilicon electrode 124 through the Zener diode 140 and the collector metal 131, wherein the cathode of the Zener diode 140 is connected to the collector metal 131, and the anode of the Zener diode 140 is connected to the polysilicon N+ region 123 and the second polysilicon electrode 124 .

The above scheme is the general technical scheme of the present invention. The longitudinal direction of the device described in the above scheme corresponds to the Y-axis direction in the three-dimensional rectangular coordinate system shown in the figure, and the transverse direction of the device corresponds to the X-axis direction. In the top view of the device, the X-axis It is on the same horizontal plane as the Y axis and perpendicular to each other, and the vertical direction of the device corresponds to the direction of the Z axis.

Further, the doping concentration of the second N-type low-doped region 150 is equal to or greater than the doping concentration of the first N-type low-doped region 3 .

Further, the Zener diode is integrated on the side of the dielectric layer 112 close to the collector metal electrode 131 , and the corresponding collector metal electrode 131 extends to contact with the side of the dielectric layer 112 and cover part of the upper surface of the Zener diode.

Further, the Zener diode is replaced by a plurality of diodes connected in series, the anode of the diode string is connected to the collector metal 131, the cathode is connected to the polysilicon highly doped N+ region 123 and the polysilicon electrode 124, and the turn-on voltage value of the diode string is greater than that of the PMOS The absolute value of the threshold voltage.

Further, in the above solution, as shown in FIG. 11 , there is a capacitor 151 between the polysilicon P+ region 121 and the polysilicon N+ region 123 . The capacitance can be formed by the parasitic capacitance formed between the polysilicon electrode 124 and the emitter metal electrode 130 during surface wiring, or can be formed in the N-type low-doped drift region 3 or in the polysilicon layer and or metal layer of the surface wiring. Formed by integrating capacitors.

In the solution of the present invention, polysilicon P-type region 122 can also adopt N-type material; Gate dielectric layer 110, the thickness and material of dielectric layer 111 and dielectric layer 112 can be identical or can be different, and used material can be silicon dioxide ( SiO ₂ ), can also be high-K materials such as aluminum oxide (Al ₂ O ₃ ), hafnium dioxide ( _Hf O ₂ ) or silicon nitride (Si ₃ N ₄ ); the semiconductor material used in the device can be silicon ( Si), silicon carbide (SiC), gallium arsenide (GaAs) or gallium nitride (GaN).

The beneficial effects of the present invention are: in the conduction state, the structure of the present invention has a lower turn-on voltage drop than the traditional LIGBT and there is no negative resistance phenomenon in the conduction process; in the block state, it has higher breakdown voltage; at the same time, in the turn-off process, it has faster turn-off speed and lower turn-off loss.

Description of drawings

FIG. 1 is a schematic diagram of a traditional lateral insulated gate bipolar transistor;

FIG. 2 is a schematic diagram of a conventional anode short-circuited lateral insulated gate bipolar transistor;

3 is a schematic diagram of the three-dimensional structure of the transistor half-cell of Embodiment 1;

Fig. 4 is the schematic sectional view of Fig. 3 structure along AA ' line;

Fig. 5 is the schematic sectional view of Fig. 3 structure along BB ' line;

Fig. 6 is the schematic sectional view of Fig. 3 structure along CC ' line;

Fig. 7 is a schematic cross-sectional view of the structure of Fig. 3 along the DD' line;

Fig. 8 is the schematic sectional view of Fig. 3 structure along EE ' line;

9 is a schematic diagram of a three-dimensional structure of a transistor half-cell in Embodiment 2;

FIG. 10 is a schematic diagram of a three-dimensional structure of a transistor half cell in Embodiment 3;

Fig. 11 is a schematic diagram of a three-dimensional structure of a transistor half cell in embodiment 4;

Fig. 12 is a basic process flow chart of the transistor manufacturing method in Embodiment 5;

Fig. 13 is a schematic diagram of the structure of a lateral insulated gate bipolar transistor manufacturing method provided by the present invention after epitaxial growth and formation of 150 layers of N-type low-doped regions;

Fig. 14 is a structural schematic diagram of a lateral IGBT manufacturing method provided by the present invention after forming a trench along the X direction on the surface of the device through an etching process;

FIG. 15 is a structural schematic diagram after forming an N-type buffer layer 7 with a folded structure in a method for fabricating a lateral insulated gate bipolar transistor provided by the present invention;

Fig. 16 is a schematic diagram of the structure of a lateral insulated gate bipolar transistor manufacturing method provided by the present invention after forming a dielectric layer and a polysilicon layer;

Fig. 17 is a structural schematic diagram after ion implantation and annealing in each region of a lateral insulated gate bipolar transistor manufacturing method provided by the present invention;

Fig. 18 is a structural schematic diagram of a method for manufacturing a lateral insulated gate bipolar transistor provided by the present invention after metal interconnection is completed;

In Figure 1-Figure 17: 1 is the P-type substrate, 2 is the buried oxide layer, 3 is the low-doped N-type region, 4 is the P-type body region, 5 is the N+ emitter region, 6 is the highly doped P+ region, 7 is an N-type buffer layer, 8 is a P-type collector region, 9 is a highly doped N+ region, 10 is a P-type region, 110 is a gate dielectric layer, 111 is a first dielectric layer, 112 is a second dielectric layer, 120 121 is the polysilicon P+ area, 122 is the polysilicon P-type area, 123 is the polysilicon N+ area, 124 is the polysilicon electrode, 125 is the polysilicon P+ area, 126 is the polysilicon N+ area, 130 is the emitter metal electrode, 131 is the collector A metal electrode, 132 is a first metal electrode, 140 is a Zener diode, 150 is a low-doped N-type region, and 151 is a capacitor.

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

Example 1

As shown in Figure 3, it is a schematic structural diagram of this example, and its semi-cellular structure includes a substrate 1, an insulating layer 2, and a first N-type low-doped region 3 that are stacked in sequence from bottom to top; it is characterized in that, along the device In the longitudinal direction, the first N-type low-doped region 3 is in the shape of a second step, defining the vertical height of the second step to be greater than the first step, and the two sides of the upper layer of the first N-type low-doped region 3 respectively have P-type body region 4 and N-type buffer region 7, along the longitudinal direction of the device, the P-type body region 4 and N-type buffer region 7 are two-level ladder; in the second level of the first N-type low-doped region 3 There is a second N-type low-doped region 150 between the ladder and the P-type body region 4 and the second-level step of the N-type buffer region 7; the upper layer of the P-type body region 4 has a P+ contact region 6 and an N+ emitter arranged side by side. region 5, wherein the N+ emitter region 5 is located on the side close to the N-type buffer zone 7, and the P+ contact region 6 and the N+ emitter region 5 are both in the shape of two steps; the P+ contact region 6 and part of the N+ emitter region 5 are There is an emitter metal electrode 130 on the surface, and the emitter metal electrode 130 is in the shape of two steps; the upper surface of the P-type body region 4 has a first gate structure, and the first gate structure is composed of a first gate dielectric layer 110 and the first polysilicon gate electrode 120 located on the upper surface of the first gate dielectric layer 110, along the longitudinal direction of the device, the lower surface of the first gate dielectric layer 110 is sequentially connected with the first N-type low-doped region 3 The upper surface of a step is in contact with the upper surface of the second N-type low-doped region 150, the lower surface of the first gate dielectric layer 110 is also in contact with the upper surface of part of the N+ emitter region 5, and the first polysilicon gate electrode 120 The upper surface is a horizontal plane; the N-type buffer zone 7 has a P-type collector region 8, a highly doped N+ region 9 and a highly doped P+ region 10, and the highly doped N+ region 9 and the highly doped P+ region 10 are in contact with each other And the highly doped N+ region 9 is located on the side close to the P-type body region 4; the P-type collector region 8, the highly doped N+ region 9 and the highly doped P+ region 10 are all in the shape of a two-level ladder; the P There is a collector metal electrode 131 on the upper surface of the P-type collector region 8 away from the P-type body region 4, and the collector metal electrode 131 is in the shape of a two-level ladder; the highly doped N+ region 9 and the highly doped P+ region 10 The upper surface of the N-type buffer zone 7 has a metal electrode 132, and the metal electrode 132 is in the shape of a second step; the upper surface of the N-type buffer zone 7 has a second gate structure, and the second gate structure is composed of a second gate dielectric layer 111 and the second polysilicon electrode 124 located on the upper surface of the second gate dielectric layer 111, along the longitudinal direction of the device, the lower surface of the second gate dielectric layer 111 is sequentially connected with the first N-type low-doped region 3 first step The upper surface of the second gate dielectric layer 111 is in contact with the upper surface of the second N-type low-doped region 150, and the lower surface of the second gate dielectric layer 111 is also in contact with part of the P-type collector region 8 and the upper surface of the highly doped P+ region 10. The second The upper surface of the polysilicon electrode 124 is a horizontal plane; the upper surface of the device between the P-type body region 4 and the N-type buffer zone 7 has a dielectric layer 112, and along the device longitudinal direction, the lower surface of the dielectric layer 112 is sequentially and the upper surface of the first step of the first N-type low-doped region 3 and the second N-type low The upper surface of the doped region 150 is in contact, and the lower surface of the dielectric layer 112 is also in contact with the upper surface of a part of the N-type buffer zone 7; the upper surface of the dielectric layer 112 has a polysilicon P+ region 121, a P-type region 122 and an N+ region 123, wherein the P-type region 122 is located between the polysilicon P+ region 121 and the N+ region 123 and is connected to each other to form a polysilicon diode, the P+ region 121 is located on the side close to the P-type body region 4, and the N+ region 123 is located near the N-type buffer region 7- Side, along the longitudinal direction of the device, the upper surfaces of the polysilicon P+ region 121, the P-type region 122 and the N+ region 123 are horizontal planes; the emitter metal electrode 130 is electrically connected to the polysilicon P+ region 121, and the polysilicon N+ region 123 is connected to the polysilicon N+ region 123. The second polysilicon electrodes 124 are electrically connected and the polysilicon N+ region 123 and the second polysilicon electrode 124 are electrically connected to the collector metal 131 through the Zener diode 140, wherein the cathode of the Zener diode 140 is connected The electrode metal 131 and the anode of the Zener diode 140 are connected to the polysilicon N+ region 123 and the second polysilicon electrode 124 .

In this example, the doping concentration of the N-type low-doped region 150 is equal to or greater than the doping concentration of the N-type low-doped region 3; the depth of the formed trench is greater than the width of the trench; the formed The depth of the trenches is greater than the device surface width between the trenches; the N-type low-doped drift region 3/150 and the polysilicon P-type region 122 are fully depleted before device breakdown; the polysilicon gate electrode The distance between 120 and the polysilicon P+ region 121 is less than 1 micron, the width of the polysilicon P+ region 121 and the N+ region 123 is less than 1 micron, and the distance between the polysilicon N+ region 123 and the metal electrode 132 is less than 1 micron; by adjusting the dielectric layer 111 Thickness and material, and the concentration of N-type buffer layer 7 surfaces under dielectric layer 111, make by N+ district 9, P+ district 10, dielectric layer 111, polysilicon electrode 124, P-type collector region 8 and N-type buffer layer 7 form The threshold voltage of the PMOS device is -2V-0V; the Zener diode 140 is integrated with other parts of the structure of the present invention on the same chip, and the Zener diode 140 is adjusted to have a voltage stabilizing value of 2V-5V .

This example works as follows:

In the blocking state, in this example, the emitter metal electrode 130 and the gate electrode 120 are grounded, and the collector metal electrode 131 is connected to the high voltage Vc. At this time, on the three-dimensional folded surface of the device, the Zener diode 140 and the polycrystalline diode formed by the P+ region 121, the P-type region 122 and the N+ region 123 form the collector to the emitter branch, and the breakdown of the Zener diode is at a stable voltage. state, the voltage on the anode side of the Zener diode remains unchanged at Vc-Vz (Vz is the voltage regulation value of the Zener diode). Because the regulated voltage value Vz of the zener diode is low, the collector voltage is mainly borne by the polycrystalline diode, and the low-doped P region 122 of the polycrystalline diode is negatively charged after depletion; meanwhile, in the polycrystalline diode with folded structure In the lower N-type low-doped region 3/150, due to the reverse bias of the PN junction formed by the low-doped N region 3/150 and the P-type body region 4, and because the concentration of the P-type body region 4 and the N-type buffer layer 7 is much higher In the low-doped N region 3/150, the withstand voltage is mainly borne by the low-doped N region 3/150, and after the low-doped N region 3/150 is depleted, it becomes a positive charge; at this time, the low-doped P region 122 consumes The depleted negative charges form charge compensation for the depleted positive charges of the low-doped N region 3/150, so the low-doped P region 122 with a folded structure provides additional charges for the low-doped N region 3/150, three-dimensional multiple field plate and reduce the surface electric field. By making the polysilicon P-type region 122, the low-doped N region 3 and the low-doped N region 150 fully depleted before the device breaks down, the breakdown voltage of the LIGBT of the present invention can be greatly improved and the low-doped N region 3 and the low-doped N region 3 and low The doping concentration of the doped N region 150 . In addition, since the polysilicon electrode 124 is connected to the Zener diode 140, the gate-source voltage of the PMOS formed by the N+ region 9, the P-type region 10, the dielectric layer 111, the polysilicon electrode 124, the P-type collector region 8, and the N-type buffer layer 7 Keep the Vz value, and adjust the threshold voltage of the PMOS to make the Zener diode’s stable voltage value greater than the absolute value of the threshold voltage of the PMOS. At this time, the PMOS is turned on, and the heavily doped N+ region 9 passes through the metal electrode 132 and the PMOS and the P-type collector region 8 Connected, through the conversion of electron current and hole current between the N+ region 9 and the P-type region 10 through the metal electrode 132, an anode short-circuit structure is formed, which reduces the P-type collector region 8/lowly doped N-type drift region 3 and 150 The gain of the triode formed by the /P-type body region 4, thereby further improving the breakdown voltage of the device;

In the conduction state, in this example, the emitter metal electrode 130 is grounded, and the gate electrode 120 and the collector metal electrode 131 are connected to a high level. At this time, the inversion MOS channel on the surface of the P-type body region 4 is turned on, and the N+ emitter region 5 Electrons are injected into the low-doped drift region 3 , and holes are injected into the low-doped drift region 3 by the P-type collector region 8 at the same time, and the IGBT is turned on. At this time, on the collector-to-emitter branch formed by the Zener diode 140 and the polycrystalline diode on the surface of the device, both the polycrystalline diode and the Zener diode form a reverse bias, and because the collector voltage is low, the Zener diode 140 cannot Breakdown, the PMOS gate-source voltage formed between the polysilicon electrode 124 and the collector metal electrode 131 is lower than the PMOS threshold voltage, the PMOS is in the off state, the N+ region 9 and the P-type collector region 8 are in the disconnected state, and the additional structure It does not affect the forward conduction characteristics of the device, that is, there is no negative resistance phenomenon like the traditional lateral insulated gate bipolar transistor. At the same time, the introduction of the three-dimensional tri-gate structure increases the equivalent width of the gate structure and further reduces the forward conduction voltage drop of the device. Therefore, the structure of the present invention has lower forward conduction voltage drop than traditional LIGBT and there is no negative resistance phenomenon in the conduction process.

During the turn-off process, in this example, the emitter metal electrode 130 is grounded, the voltage of the gate electrode 120 gradually decreases from high level, the MOS channel on the surface of the P-type body region 4 is cut off, and the voltage of the collector metal electrode 131 gradually increases. As the voltage of the collector metal electrode 131 increases, when the collector voltage is lower than the Zener diode breakdown voltage Vz, the collector-to-emitter branch formed by the Zener diode 140 and the polycrystalline diode on the device surface, the Zener The diode is not broken down. At this time, the PMOS gate-source voltage is lower than its threshold voltage, and the PMOS is in an off state. When the collector voltage is higher than the Zener diode breakdown voltage Vz, the Zener diode breaks down, and the polycrystalline diode begins to bear the voltage. At this time, the PMOS gate-source voltage is stable at Vz, and the Zener diode is adjusted by adjusting the threshold voltage of the PMOS. The stable voltage value of the diode is greater than the absolute value of the threshold voltage of the PMOS. At this time, the PMOS is turned on and turned on. The heavily doped N+ region 9 is connected to the P-type collector region 8 through the metal electrode 132 and the PMOS, and the N+ region 9 is connected to the metal electrode 132 through the metal electrode 132. The conversion of electron current and hole current between P-type region 10 forms an anode short-circuit structure. At this time, electrons in the drift region are extracted by highly doped N+ region 9 and converted into hole current through metal electrode 132 through PMOS drain. The pole P-type region 10 , the inversion layer under the gate dielectric layer 111 , the PMOS source P+ region 8 , and finally reaches the collector metal 131 . This process completes the extraction of electrons in the low-doped N-type drift region 3/150, thereby greatly improving the turn-off speed of the LIGBT and reducing the turn-off loss. At the same time, during the turn-off process, when the collector voltage is higher than the Zener diode breakdown voltage Vz, the Zener diode breaks down, the polycrystalline diode begins to bear the voltage, the polycrystalline diode drift region 122 begins to be exhausted, and the polycrystalline diode drifts The charge and field plate effect provided by the region depletion accelerates the longitudinal expansion of the device drift region depletion layer along the X axis in the YZ plane, and further accelerates the carrier extraction inside the LIGBT device, thereby increasing the turn-off speed of the device and further reducing the device the turn-off loss. In addition, the use of a high doping concentration of 3/150 in the low-doped drift region further reduces the concentration of excess carriers to be extracted, further improves the turn-off speed of the device, and reduces the turn-off loss of the device.

Example 2

As shown in Figure 9, the difference from Example 1 is that

A zener diode is directly formed in the polysilicon layer above the dielectric layer 112, the zener diode is formed on the device surface between the trenches, the P+ region 125 is the anode of the zener diode, and the N+ region 126 is the cathode of the zener diode . The type, location and shape of the Zener diodes can be adjusted as desired.

Example 3

As shown in FIG. 10, the difference from Embodiment 1 is that a Zener diode is directly formed in the polysilicon layer above the dielectric layer 111, and the Zener diode is formed on the device surface between the trenches, and the P+ region 125 is The anode of the Zener diode, N+ region 126 is the cathode of the Zener diode. The type, location and shape of the Zener diodes can be adjusted as desired.

Example 4

On the basis of the above-mentioned embodiments, the Zener diode is replaced by a plurality of diodes connected in series, the anode of the diode string is connected to the collector metal 131, the cathode is connected to the polysilicon highly doped N+ region 123 and the polysilicon electrode 124, and the turn-on voltage of the diode string The value is greater than the absolute value of the threshold voltage of the PMOS.

Example 5

As shown in Figure 11, different from Embodiment 3, in this example, there is also a capacitor 151 between the polysilicon P+ region 121 and the polysilicon N+ region 123; The gate capacitance value of the PMOS formed by the region 10, the dielectric layer 111, the polysilicon electrode 124, the P-type collector region 8 and the N-type buffer layer 7. The capacitance can be formed by the parasitic capacitance formed between the polysilicon electrode 124 and the emitter metal electrode 130 during surface wiring, or can be formed by the metal layer and or polycrystalline layer in the N-type low-doped drift region 3 or surface wiring Formed by integrating capacitors. Compared with Embodiment 3, the control of the voltage of the polysilicon electrode 124 is improved, and the performance of the device is further improved.

The present invention also provides a method for manufacturing a lateral insulated gate bipolar transistor. The basic process flow is shown in FIG. 12 , taking the structure of a 200V N-type lateral insulated gate bipolar transistor as an example to illustrate its specific process steps. It is characterized in that it mainly includes the following steps:

Step 1: Select a suitable SOI material, which includes a P-type semiconductor material substrate 1 with a thickness of 300-500 microns and a concentration of 10-100 Ω·cm, a buried oxide layer 2 with a thickness of 0.5-1 microns, and a thickness of 5 An N-type low-doped silicon layer 3 of ~10um and a resistivity of 5-10Ω·cm;

Step 2: Form 150 layers of N-type low-doped regions with a thickness of 5-10 microns and a resistivity of 3-10Ω·cm by epitaxial growth, as shown in Figure 13;

Step 3: Form grooves along the X direction on the surface of the device through an etching process. The depth of the grooves is 5-10 microns, the width is 1-2 microns, and the width between the grooves is 1-2 microns. The lower surface is in contact with the N-type low-doped region 3 on the XY plane, and the sides of the trench are in contact with the N-type low-doped drift region 3 and the N-type low-doped region 150 on the XZ plane, as shown in FIG. 14 ;

Step 4: Form an N-type buffer layer 7 with a folded structure on one side of the device surface through photolithography, ion implantation and annealing process, the thickness of the N-type buffer layer 7 is 1-3um, as shown in Figure 15;

The fifth step: grow the gate oxide layer, perform polysilicon deposition and photolithography, etch to form the gate oxide layer 110, gate electrode 120, dielectric layer 111, polysilicon electrode 124, dielectric layer 112 and the polycrystalline silicon on the dielectric layer 112 Layer, in-situ P-type doping (for obtaining the doping of the P-type region 122 of polysilicon) is used in the polysilicon deposition process, the thickness of the oxide layer is 50-100 nanometers, the thickness of the polycrystalline layer is 0.5-1um, and the polycrystalline The layer is P-type doped, and the doping concentration is 10 ¹⁵ ~ 10 ¹⁶ cm ^-3 , as shown in Figure 16;

Step 6: Perform photolithography of the P-type body region, P-type ion implantation, and annealing to form the P-type body region 4, and the thickness of the P-type body region 4 is 1-3um;

Step 7: Perform N+ photolithography and N-type ion implantation to form N+ emitter region 5, heavily doped N+ region 9, and polysilicon diode N+ region 123;

Step 8: Perform P+ photolithography and P-type ion implantation to form highly doped P+ regions 6, P-type regions 10, and polysilicon diode P+ regions 121;

Step 9: Perform photolithography and ion implantation of the P-type collector region to form a P-type collector region 8, as shown in Figure 17;

Step 10: perform BPSG deposition, hole photolithography, metal deposition, photolithography, and etching to form metal interconnections, that is, to prepare a lateral insulated gate bipolar transistor as shown in FIG. 18 .

Further, the gate dielectric layer 110, dielectric layer 111 and dielectric layer 112 of different thicknesses and materials can be formed in two steps or three steps in the preparation process of the dielectric layer;

Further, the doping of the P-type region 122 of the polysilicon diode may not be in-situ doping, but obtained by adjusting the pattern ratio of the photolithography plate during the photolithography and ion implantation steps of the P-type collector region.

Claims (5)

1. A lateral insulated gate bipolar transistor, whose half-cell structure includes a substrate (1), an insulating layer (2) and a first N-type low-doped region (3) stacked sequentially from bottom to top; It is characterized in that, along the longitudinal direction of the device, the first N-type low-doped region (3) is in the shape of two steps, defining the vertical height of the second step to be greater than that of the first step, and the first N-type low-doped region There are P-type body regions (4) and N-type buffer regions (7) on both sides of the upper layer of the region (3), and along the longitudinal direction of the device, the P-type body regions (4) and N-type buffer regions (7) are two Step-like; there is a second N-type low doping between the second step of the first N-type low-doped region (3) and the second step of the P-type body region (4) and the N-type buffer zone (7). Region (150); the upper layer of the P-type body region (4) has a P+ contact region (6) and an N+ emitter region (5) arranged side by side, wherein the N+ emitter region (5) is located near the N-type buffer zone (7) One side of the P+ contact region (6) and the N+ emitter region (5) are two-level stepped; the upper surface of the P+ contact region (6) and part of the N+ emitter region (5) has an emitter metal electrode ( 130), the emitter metal electrode (130) is in the shape of two steps; the upper surface of the P-type body region (4) has a first gate structure, and the first gate structure is composed of a first gate dielectric layer ( 110) and the first polysilicon gate electrode (120) located on the upper surface of the first gate dielectric layer (110), along the longitudinal direction of the device, the lower surface of the first gate dielectric layer (110) is sequentially connected with the first N The upper surface of the first step of the N-type low-doped region (3) is in contact with the upper surface of the second N-type low-doped region (150), and the lower surface of the first gate dielectric layer (110) is also in contact with part of the N+ emitter region (5 ), the upper surface of the first polysilicon gate electrode (120) is a horizontal plane; the N-type buffer zone (7) has a P-type collector region (8), a highly doped N+ region (9) and the highly doped P+ region (10), the highly doped N+ region (9) and the highly doped P+ region (10) are in contact with each other and the highly doped N+ region (9) is located on the side close to the P-type body region (4) ; The P-type collector region (8), the highly doped N+ region (9) and the highly doped P+ region (10) are all two-level ladders; the upper surface of the P-type collector region (8) is far away from the P One side of the body region (4) has a collector metal electrode (131), and the collector metal electrode (131) is in a two-level ladder shape; the highly doped N+ region (9) and the highly doped P+ region (10 ) has a metal electrode (132) on the upper surface, and the metal electrode (132) is in a two-level ladder shape; the upper surface of the N-type buffer zone (7) has a second gate structure, and the second gate structure Consists of a second gate dielectric layer (111) and a second polysilicon electrode (124) located on the upper surface of the second gate dielectric layer (111), along the longitudinal direction of the device, the bottom of the second gate dielectric layer (111) The surface is sequentially in contact with the upper surface of the first step of the first N-type low-doped region (3) and the upper surface of the second N-type low-doped region (150), and the lower surface of the second gate dielectric layer (111) is also In contact with the upper surface of part of the P-type collector region (8) and the highly doped P+ region (10), the upper surface of the second polysilicon electrode (124) is a horizontal plane; in the P-type body region (4) and The upper surface of the device between the N-type buffer areas (7) has a dielectric layer (112), and along the longitudinal direction of the device, the lower surface of the dielectric layer (112) is sequentially connected with the first N-type low-doped region (3). The upper surface of the step is in contact with the upper surface of the second N-type low-doped region (150), and the lower surface of the dielectric layer (112) is also in contact with the upper surface of a part of the N-type buffer zone (7); the dielectric layer (112) upper surface has polysilicon P+ area (121), P type area (122) and N+ area (123), and wherein P type area (122) is positioned at polysilicon P+ area (121) and N+ area (123) and mutual Connect to form a polysilicon diode, the P+ region (121) is positioned at the side close to the P-type body region (4), the N+ region (123) is positioned at the side near the N-type buffer zone (7), and along the device longitudinal direction, the polysilicon P+ region (121 ), the upper surface of the P-type region (122) and the N+ region (123) is a horizontal plane; the electrical connection between the emitter metal electrode (130) and the polysilicon P+ region (121), the N+ region (123) and the first The two polysilicon electrodes (124) are electrically connected and the N+ region (123) is electrically connected to the second polysilicon electrode (124) through a Zener diode (140) and the collector metal (131), wherein The cathode of the Zener diode (140) is connected to the collector metal (131), and the anode of the Zener diode (140) is connected to the N+ region (123) and the second polysilicon electrode (124). 2. A lateral insulated gate bipolar transistor according to claim 1, characterized in that the doping concentration of the second N-type low-doped region (150) is equal to or greater than that of the first N-type low-doped region Doping concentration of region (3). 3. A lateral insulated gate bipolar transistor according to claim 1 or 2, characterized in that the Zener diode is integrated on the side of the dielectric layer (112) close to the collector metal electrode (131), corresponding The collector metal electrode (131) extends to contact with the side of the dielectric layer (112) and covers part of the upper surface of the Zener diode. 4. A kind of lateral insulated gate bipolar transistor according to claim 1 or 2, is characterized in that, described zener diode is replaced by a plurality of diodes connected in series, and the anode of diode string connects collector metal (131) , the cathode is connected to the N+ region (123) and the polysilicon electrode (124), and the turn-on voltage value of the diode string is greater than the absolute value of the threshold voltage of the PMOS. 5. A lateral insulated gate bipolar transistor according to claim 1 or 2, characterized in that there is a capacitor (151) between the polysilicon P+ region (121) and the N+ region (123).