CN105742346B - Double division trench gate charge storage type RC-IGBT and its manufacturing method - Google Patents

Abstract

The invention belongs to power semiconductor device technology fields, and in particular to inverse conductivity type trench gate charge storage type insulated gate bipolar transistor.The present invention passes through the dielectric layer between the bottom of gate electrode in RC IGBT device grooves and the equipotential double Split Electrodes of lateral leadin and emitter and double Split Electrodes and gate electrode, the switching speed of device is improved in IGBT operating modes, the carrier concentration profile of entire N-type drift region is improved, reduces the switching loss of device；The saturation current density of device is reduced, the short-circuit safety operation area of device is improved, improves reliability；Make reversed fly-wheel diode that there is low diode conduction voltage drop in reversed fly-wheel diode operating mode, and improve the reverse recovery characteristic of fly-wheel diode；Double division trench gate charge storage type IGBT production methods proposed by the invention simultaneously need not increase additional processing step, compatible with traditional RC IGBT production methods.

Description

Double split trench gate charge storage type RC-IGBT and its manufacturing method

technical field

The invention belongs to the technical field of power semiconductor devices, and relates to an insulated gate bipolar transistor (IGBT), in particular to a reverse conduction trench gate charge storage type insulated gate bipolar transistor (RC-CSTBT).

Background technique

Insulated Gate Bipolar Transistor (IGBT) is a new type of power electronic device combining MOS field effect and bipolar transistor. It not only has the advantages of easy driving and simple control of MOSFET, but also has the advantages of low conduction voltage of power transistor, large on-state current and small loss. It has become one of the core electronic components in modern power electronic circuits and is widely used in Various fields of the national economy such as communications, energy, transportation, industry, medicine, household appliances and aerospace. The application of IGBT plays an extremely important role in improving the performance of power electronic systems. Since the invention of IGBT, people have been working on improving the performance of IGBT. After more than 20 years of development, six generations of IGBT device structures have been proposed successively, which has steadily improved device performance. The 6th generation trench gate charge storage insulated gate bipolar transistor (CSTBT) uses a higher doping concentration and a certain thickness of the N-type charge storage layer structure, so that the carrier concentration distribution of the IGBT device near the emitter terminal It has been greatly improved, improving the conductance modulation of the N-type drift region, improving the carrier concentration distribution of the entire N-type drift region, and enabling the IGBT to obtain a low forward conduction voltage drop and an improved forward conduction voltage drop tradeoff with turn-off losses.

In power electronic systems, IGBTs usually need to be used with Free Wheeling Diodes (FWD) to ensure the safety and stability of the system. Therefore, in traditional IGBT modules or single-tube devices, FWD is usually connected in reverse parallel with it. This solution not only increases the number of devices, the volume of the module and the production cost, but also increases the number of solder joints in the packaging process, which will affect the reliability of the device. The parasitic effects generated by the metal wiring also affect the overall performance of the device. In order to solve this problem and achieve product integration, combined with the CSTBT device structure, the industry proposed a reverse conduction trench gate charge storage type insulated gate bipolar transistor (RC-CSTBT), and successfully integrated the freewheeling diode inside the CSTBT. , whose structure is shown in Figure 1. Compared with the traditional CSTBT without freewheeling capability, this structure has an N-type collector region 12 connected to the metal collector 13 and the N-type electric field stop layer 10 on its back, which is the same as the P-type base region 7, The N-type charge storage layer 8 and the N-drift region 9 form a parasitic diode structure, and in the freewheeling mode, the parasitic diode conducts to provide a current path.

However, for the traditional RC-CSTBT device structure, in the forward IGBT mode, due to the presence of a higher doping concentration and a certain thickness of the N-type charge storage layer, the breakdown voltage of the device is significantly reduced. In order to effectively shield the N-type Adverse effects of the charge storage layer To obtain a certain device withstand voltage, it is necessary to adopt: 1) deep trench gate depth, so that the depth of the trench gate is greater than the junction depth of the N-type charge storage layer, but the deep trench gate depth not only increases The larger gate-emitter capacitance also increases the gate-collector capacitance, thus reducing the switching speed of the device, increasing the switching loss of the device, and affecting the compromise between the conduction voltage drop and switching loss of the device characteristics; 2) The small cell width minimizes the distance between the trench gates. However, the high-density trench MOS structure not only increases the gate capacitance of the device, but also reduces the switching speed of the device and increases the The switching loss of the device is increased, which affects the compromise characteristics of the conduction voltage drop and switching loss of the device, and increases the saturation current density of the device, making the short-circuit safe working area of the device worse. In the reverse diode freewheeling mode of operation, due to the existence of the built-in potential of the PN junction formed by the P-type base region 7 and the N-type charge storage layer 8/N-drift region 9, the forward conduction voltage drop is relatively large, and at the same time due to When the freewheeling diode is turned on, a large number of carriers are injected into the N-drift region 9. The existence of a large number of excess carriers makes the reverse recovery characteristics of the freewheeling diode poor, such as long reverse recovery time and large reverse recovery charge. Wait.

Contents of the invention

The purpose of the present invention is in order to optimize the forward IGBT characteristic of traditional RC-CSTBT, improve reverse diode characteristic simultaneously, improve the reliability of device, on the basis of traditional RC-CSTBT device structure (as shown in Figure 1), the present invention Provide a double-split trench gate charge storage type RC-IGBT (as shown in Figure 2) and its manufacturing method. In the case of MOS structure density, by introducing a double-split electrode with the same potential as the emitter at the bottom and side of the gate electrode in the device trench, through the shielding effect of the double-split electrode and the thick dielectric layer between the double-split electrode and the gate electrode, The gate capacitance of the device is reduced, especially the gate-collector capacitance, the switching speed of the device is improved, the switching loss is reduced, and the compromise between forward voltage drop and switching loss is further improved. At the same time, the side split The introduction of the electrode reduces the density of the MOS channel, improves the short-circuit safe operating area of the IGBT, and improves the performance and reliability of the device; in addition, the wide bottom split electrode at the bottom of the trench further enhances the carrier enhancement of the emitter terminal effect, further improving the carrier concentration distribution of the entire N-type drift region, further improving the compromise between the forward conduction voltage drop and switching loss, and improving the performance of the device; at the same time, through the thick dielectric layer around the bottom split electrode and The wide width further effectively shields the N-type charge storage layer and the influence of the thin dielectric layer at the gate electrode and the side split electrode on the device withstand voltage under the condition of a certain device trench depth and trench MOS structure density, and improves the device withstand voltage. The breakdown voltage of the device improves the concentration of the electric field at the bottom of the trench, and further improves the reliability of the device. In the reverse diode freewheeling mode, through the side split electrode connected to the emitter, the MOS channel at the side split electrode is turned on, so that the reverse freewheeling diode works in the multi-sub-device mode, with low backlash diode turn-on voltage drop and excellent reverse recovery characteristics. The manufacturing method provided by the invention does not need to add additional process steps, and is compatible with the traditional trench gate charge storage type RC-IGBT manufacturing method.

The technical solution of the present invention is: double-split trench gate charge storage type RC-IGBT, including collector metal 13, P-type collector region 11, N-type electric field stop layer 10, and N-type drift region stacked sequentially from bottom to top 9 and emitter metal 1; also includes an N-type collector region 12 arranged in parallel with the P-type collector region 11; the N-type drift region 9 has an N+ emitter region 5, a P+ emitter region 6, and a P-type base region 7 , an N-type charge storage layer 8 and a trench gate structure; the trench gate structure sequentially penetrates the N+ emitter region 5, the P-type base region 7 and the N-type charge storage layer 8 along the vertical direction, and then extends into the N-type drift region; The P-type base region 7 is located on the upper surface of the N-type charge storage layer 8, and the N+ emitter region 5 and the P+ emitter region 6 are located side by side on the upper surface of the P-type base region 7; pole metal 1 connection; it is characterized in that the trench gate structure includes a bottom split electrode 31, a gate electrode 32, a side split electrode 33, a gate dielectric layer 41, a second dielectric layer 42, a third dielectric layer 43, a fourth dielectric layer 44 and the fifth dielectric layer 45; the gate electrode 32 and the side split electrode 33 are connected through the third dielectric layer 43; the gate electrode 32 is connected to the N+ emitter region on one side of the trench gate structure through the gate dielectric layer 41 5 is connected to the P-type base region 7; the side split electrode 33 is connected to the N+ emitter region 5 and the P-type base region 7 on the other side of the trench gate structure through the second dielectric layer 42; the bottom split electrode 31 is located at the gate Below the electrode 32 and the side split electrode 33, and the upper surface depth of the bottom split electrode 31 is less than the junction depth of the N-type charge storage layer 8, and the lower surface depth of the bottom split electrode 31 is greater than the junction depth of the N-type charge storage layer 8; The upper surface of the bottom split electrode 31 is connected to the lower surface of the gate electrode 32 and the side split electrode 33 through a fourth dielectric layer 44; the lower surface and side surfaces of the bottom split electrode 31 are connected to the N-type drift region 9 and the N-type The charge storage layers 8 are connected through the fifth dielectric layer 45; the width of the bottom split electrode 31 is greater than the width of the second dielectric layer 42, the side split electrodes 33, the third dielectric layer 43, the gate electrode 32 and the gate dielectric layer 41 The sum makes the trench gate structure an inverted "T" shape; the upper surface of the second dielectric layer 42, the side split electrode 33 and part of the third dielectric layer 43 is connected to the emitter metal 1; the gate dielectric layer 41 The upper surface of the gate electrode 32 and part of the third dielectric layer 43 has the first dielectric layer 2 ; the bottom split electrode 31 and the side split electrode 33 have the same potential as the emitter metal 1 .

Further, the thicknesses of the third dielectric layer 43 , the fourth dielectric layer 44 and the fifth dielectric layer 45 are greater than the thicknesses of the gate dielectric layer 41 and the second dielectric layer 42 .

Further, the thickness of the gate dielectric layer 41 is greater than the thickness of the second dielectric layer 42 .

Further, the bottom of the side split electrode 33 extends to connect with the upper surface of the bottom split electrode 31 .

Further, there are N+ layers 14 on both sides of the trench gate structure, one side of the N+ layer 14 is connected to the N-type charge storage layer 8, and the other side and bottom of the N+ layer 14 are connected to the trench gate structure , the upper surface of the N+ layer 14 is connected to the lower surface of the P-type base region 7 .

Further, the drift region structure is an NPT structure or an FS structure; the IGBT device is made of semiconductor materials Si, SiC, GaAs or GaN.

The manufacturing method of double-split trench gate charge storage type RC-IGBT is characterized in that it comprises the following steps:

Step 1: Select an N-type lightly doped single crystal silicon wafer as the N-type drift region 9 of the device. The thickness of the selected silicon wafer is 300-600um, and the doping concentration is 10 ¹³ -10 ¹⁴ /cm ³ ; The N-type field stop layer 10 of the device is manufactured by ion-implanting N-type impurities on the back and annealing. The thickness of the formed N-type field stop layer is 15-30 microns, the ^ion implantation energy is 1500keV-2000keV, and the implantation dose is ^1013-1014 pieces/cm ² , the annealing temperature is 1200-1250°C, and the annealing time is 300-600 minutes;

The second step: Flip and thin the silicon wafer to the required thickness, and form grooves on the surface of the silicon wafer by photolithography and etching;

Step 3: Form an oxide layer around the trench at 1050°C to 1150°C in an O ₂ atmosphere; then deposit and fill polysilicon in the trench at 750°C to 950°C; oxidize again and etch away excess oxide layer; form the bottom split electrode 31 and the fifth dielectric layer 45, the bottom sort electrode 31 is located in the fifth dielectric layer 45;

Step 4: Form an N-type doped layer with a thickness of 2 to 6 microns on the surface of the silicon wafer by epitaxy;

Step 5: Deposit a thin layer of pad oxide layer and silicon nitride layer on the surface of the silicon wafer. After the window is photoetched, silicon trench etching is performed again, and a trench is etched above the bottom electrode 31. The third step The oxide layer formed by oxidizing the surface of polysilicon in the step can be used as the stop layer of silicon etching in this step; after the trench etching is completed, rinse the silicon nitride and pad oxide layer on the surface with a solution; the groove and pad oxide layer formed in this step The groove formed in the second step constitutes an inverted "T" shaped groove;

Step 6: grow an oxide layer on the inner wall of the trench by thermal oxidation, and the thickness of the formed oxide layer is less than 120nm;

Step 7: Etching the oxide layer formed on the left side wall of the trench in the sixth step by using a photolithography process; forming a gate dielectric layer 41 on the right side wall of the trench; forming a fourth dielectric layer 44 at the bottom of the trench;

Step 8: Re-grow an oxide layer on the inner wall of the trench by thermal oxidation, and the thickness of the formed oxide layer is less than 40nm; form a second gate dielectric layer 42 on the left side wall of the trench

Step 9: Deposit and fill polysilicon in the trench at 750°C to 950°C;

Step 10: Etching part of the polysilicon filled in the trench in step 9 by photolithography, forming gate electrodes 32 and side split electrodes 33 on both sides of the trench respectively; the gate electrodes 32 are connected to the gate dielectric layer 41 , the side split electrode 33 is connected to the second dielectric layer 42;

The eleventh step: deposition, the trench between the gate electrode 32 and the side split electrode 33 formed in the tenth step is filled with a dielectric to form a third dielectric layer 43;

The twelfth step: using a photolithography process, first fabricate the N-type charge storage layer 8 of the device by ion-implanting N-type impurities, and the N-type charge storage layer 8 is located on both sides of the trench; the energy of ion implantation is 200-500keV, The implantation dose is 10 ¹³ to 10 ¹⁴ pcs/cm ² ; then the P-type base region 7 is produced by ion implantation of P-type impurities and annealing, the energy of ion implantation is 60-120keV, and the implantation dose is 10 ^{13-10 14} pcs/cm ² , the annealing temperature is 1100-1150°C, and the annealing time is 10-30 minutes; the P-type base region 7 is located on the upper surface of the N-type charge storage layer 8; the junction depth of the formed N-type charge storage layer 8 is greater than that of the gate electrode 32 The depth is less than the depth of the bottom split electrode 31, and the junction depth of the formed P-type base region 7 is less than the depth of the gate electrode 32;

The thirteenth step: using a photolithography process, the N+ emission region 5 of the device is manufactured by ion implantation of N-type impurities, the ion implantation energy is 30-60keV, and the implantation dose is 10 ^{15-10 16} /cm ² ; the N+ emission Region 5 is located on the upper surface of P-type base region 7 and connected to the trench;

Step 14: Using the photolithography process, the P+ emission region 6 of the device is produced by ion-implanting P-type impurities and annealing. The energy of ion implantation is 60-80keV, the implantation dose is 10 ^{15-10 16} /cm ² , and the annealing temperature The temperature is 900°C, and the time is 20 to 30 minutes; the P+ emitter region 6 and the N+ emitter region 5 are located side by side on the upper surface of the P-type base region 7;

Step 15: Deposit a dielectric layer on the surface of the device, and form a first dielectric layer 2 by photolithography and etching; the first dielectric layer 2 is located between a part of the third dielectric layer 43, the gate electrode 32 and the gate dielectric layer 41 upper surface;

The sixteenth step: deposit metal, and photolithography, etch on the upper surface of the N + emission region 5 and P + emission region 6 and the upper surface of the second dielectric layer 42, the side split electrode 33 and part of the third dielectric layer 43 to form a set electrode metal 1;

The seventeenth step: turn over the silicon wafer, reduce the thickness of the silicon wafer, inject P-type impurities on the back of the silicon wafer to form a P-type collector region 11, and the P-type collector region 11 is located on the lower surface of the N-type electric field stop layer 10, and inject The energy is 40-60keV, and the implantation dose is 10 ^{12-10 13} pcs/cm ² ; the N-type collector region 12 of the device is fabricated by ion-implanting N-type impurities. The ion-implantation energy is 40-60keV, and the implantation dose is 10 ¹⁴ to 10 ¹⁵ pieces/cm ² ; followed by back annealing in an atmosphere of H ₂ and N ₂ mixed at a temperature of 400 to 450°C for 20 to 30 minutes; the N-type collector region 12 and the P Type collectors 11 are arranged side by side;

Step 18: Deposit metal on the back to form collector metal 13 .

Further, in the third step, the P-type base region 7 can be formed in two steps by increasing the photolithography step, so that the concentration and junction depth of the P-type base region 7 on the side near the gate electrode 32 are greater than those near the side split electrode. The concentration and junction depth of the P-type base region 7 on the 33 side.

The working principle of the present invention is:

For the traditional RC-CSTBT device shown in Figure 1, in the forward IGBT mode, in order to improve the performance and reliability of the IGBT device, it is necessary to reduce the switching loss of the device and reduce the switching loss of the device under a certain blocking voltage capability. Reduces the forward voltage drop while improving the short-circuit safe operating area of the device. The switching process of the IGBT is the process of charging and discharging the gate capacitance. The larger the gate capacitance is, the longer the discharge time is. Therefore, in the switching process of the IGBT, the gate capacitance, especially the gate-collector capacitance has an important influence on the switching loss of the device. In the traditional trench gate charge storage type RC-IGBT structure as shown in Figure 1, in order to effectively shield the adverse effect of higher doping concentration and certain thickness of the N-type charge storage layer on the breakdown voltage to obtain a certain device endurance Therefore, it is necessary to use: 1) Deep trench gate depth, so that the depth of the trench gate is greater than the junction depth of the N-type charge storage layer; 2) Small cell width, high-density trench MOS structure makes the trench gate The distance between them should be reduced as much as possible. However, both the deep trench gate depth and the high density trench MOS structure increase not only the gate-emitter capacitance but also the gate-collector capacitance. In addition, for the traditional trench gate charge storage type IGBT structure, the gate oxide layer is formed in the trench by one thermal oxidation. In order to ensure a certain threshold voltage, the thickness of the entire gate oxide layer is small. The thickness of the layer is inversely proportional to the thickness of the small gate oxide layer in the traditional trench gate charge storage IGBT structure, which greatly increases the gate capacitance of the device. At the same time, the high-density trench MOS structure increases the saturation current density of the device, which deteriorates the short-circuit safe operating area of the device; in addition, the small gate oxide layer thickness concentrates the electric field at the bottom of the trench, making the reliability of the device poor.

As shown in Figures 2, 3 and 4, the present invention introduces a double-split electrode at the same potential as the emitter and a thick dielectric layer between the double-split electrode and the gate electrode at the bottom and sides of the gate electrode in the device trench. In the case of affecting the threshold voltage and turn-on of the IGBT device: 1) the depth of the gate electrode in the trench is reduced, and the gate capacitance including gate-collector capacitance and gate-emitter capacitance is greatly reduced; 2 ) through the shielding effect of the double-split electrodes, the coupling between the gate and the collector is shielded, and the gate-collector capacitance is converted into a gate-emitter capacitance, which greatly reduces the gate-collector capacitance. At the same time, through the thick dielectric Layers 43 and 44 act to make the gate-emitter capacitance increase from the gate-collector capacitance conversion much smaller than the gate-emitter capacitance decrease due to the introduction of the side split electrode 33, thereby greatly reducing the included Gate capacitance including gate-collector capacitance, gate-emitter capacitance. Therefore, the structure of the present invention greatly reduces the gate capacitance of the device, especially the gate-collector capacitance, improves the switching speed of the device, and reduces the switching loss of the device. In addition, under a certain trench MOS structure density, the introduction of the side split electrode 33 reduces the density of the MOS channel, reduces the saturation current density of the device, improves the short-circuit safe working area of the device, and improves reliability; in addition , the wide bottom split electrode at the bottom of the trench further enhances the carrier concentration enhancement effect at the emitter end, further improves the carrier concentration distribution in the entire N-type drift region, and further improves the forward conduction voltage drop and switching loss. In addition, since the side split electrode 33 and the bottom split electrode 31 are equipotential to the emitter, during the dynamic process of turning on the IGBT device, the semiconductor layer in contact with the side split electrode 33 and the bottom split electrode 31 through the dielectric layer No inversion (floating p-type base region 72) and electron accumulation (N-type charge storage layer 8 and N-type drift region 9) will be formed on the surface, so the negative differential capacitance effect will not be formed, and the current flow during the dynamic process of turning on will not be formed. , voltage oscillation and EMI problems, improving reliability; at the same time, through the thick dielectric layer and wide width around the bottom split electrode, the N-type is further effectively shielded under the condition of a certain device trench depth and trench MOS structure density. The impact of the charge storage layer and the thin dielectric layer at the gate electrode and the side split electrode on the withstand voltage of the device, especially effectively shielding the pair of the dielectric layer at the extremely thin side split electrode for obtaining a small parasitic MOS structure threshold voltage The impact of the withstand voltage of the device increases the breakdown voltage of the device, improves the concentration of the electric field at the bottom of the trench, and further improves the reliability of the device. In the composite double-split trench structure provided by the present invention, the depth of the trench gate electrode 32 is greater than the depth of the p-type base region 7 and the depth of the trench gate electrode 32 is smaller than the depth of the N-type charge storage layer 8, which does not affect the When the IGBT device is turned on, the gate capacitance, especially the gate-collector capacitance, is reduced as much as possible. On the other hand, the existence of a high-concentration N-type charge storage layer 8 with a certain thickness compensates The introduction of the bottom split electrode reduces the carrier concentration near the bottom split electrode, avoiding the deterioration of the device characteristics caused by the sharp increase of the forward conduction voltage drop of the device due to the introduction of the bottom split electrode. In the reverse diode freewheeling mode, by adjusting the concentration and thickness of the p-type base region 7 and the thickness and material of the dielectric layer 42, the threshold voltage of the parasitic MOS structure at the side split electrode is less than 0.1V, and the The role of the connected side split electrodes makes the MOS channel at the side split electrodes open below 0.1V, so that the reverse freewheeling diode works in the multi-sub-device mode of the MOS control diode, shielding the P-type base region 7 and The impact of the built-in potential of the PN junction formed by the N-type charge storage layer 8/N-drift region 9 makes the reverse freewheeling diode have a low diode conduction voltage drop; at the same time, due to the multi-subconduction, it does not need to recover in the reverse direction During the process, the excess carriers in the N-drift region 9 are extracted, which improves the reverse recovery characteristics of the freewheeling diode, such as short reverse recovery time and small reverse recovery charge. In addition, the manufacturing method provided by the present invention does not need to add additional process steps, and is compatible with the traditional trench gate charge storage type RC-IGBT manufacturing method.

The beneficial effects of the present invention are that the gate capacitance including gate-collector capacitance and gate-emitter capacitance is greatly reduced; the carrier concentration distribution of the entire N-type drift region is improved; The switching speed of the device reduces the switching loss of the device, reduces the saturation current density of the device, improves the short-circuit safe working area of the device, improves the reliability, improves the concentration of the electric field at the bottom of the trench, and avoids the splitting of the electrode due to the bottom The introduction of a sharp increase in the forward conduction voltage drop of the device leads to the deterioration of the device characteristics, so that the reverse freewheeling diode has a low diode conduction voltage drop, which improves the reverse recovery characteristics of the freewheeling diode, such as reverse recovery The time is short, the reverse recovery charge is small, etc.; in addition, the manufacturing method provided by the present invention does not need to add additional process steps, and is compatible with the traditional trench gate charge storage type RC-IGBT manufacturing method.

Description of drawings

Figure 1 is a schematic diagram of the cell structure of a traditional RC-CSTBT device;

In Figure 1, 1 is the emitter metal, 2 is the dielectric layer, 3 is the gate electrode, 4 is the gate dielectric layer, 5 is the N+ emitter region, 6 is the P+ emitter region, 7 is the P-type base region, and 8 is the N-type charge The storage layer, 9 is an N-drift region, 10 is an N-type electric field stop layer, 11 is a P-type collector region, 12 is an N-type collector region, and 13 is a collector metal;

Fig. 2 is the schematic diagram of the cell structure of the double split trench gate charge storage type RC-IGBT device of embodiment 1;

3 is a schematic diagram of the cell structure of the double split trench gate charge storage type RC-IGBT device of embodiment 2;

Fig. 4 is the schematic diagram of the cell structure of the double-split trench gate charge storage type RC-IGBT device of embodiment 3;

In Figure 2 to Figure 3, 1 is the emitter metal, 2 is the dielectric layer, 31 is the bottom split electrode, 32 is the gate electrode, 33 is the side split electrode, 41 is the gate dielectric layer, 42 is the dielectric layer, 43 is the dielectric layer , 44 is the dielectric layer, 45 is the dielectric layer, 5 is the N+ emitter region, 6 is the P+ emitter region, 7 is the P-type base region, 8 is the N-type charge storage layer, 9 is the N-drift region, and 10 is the N-type electric field Blocking layer, 11 is a P-type collector area, 12 is an N-type collector area, 13 is a collector metal, and 14 is an N+ layer;

5 is a schematic diagram of the device structure after the first etching to form a trench in the manufacturing method of the present invention;

6 is a schematic diagram of the device structure after forming bottom split electrodes in the manufacturing method of the present invention;

7 is a schematic diagram of the device structure after the epitaxial N-layer in the manufacturing method of the present invention;

8 is a schematic diagram of the device structure after the trench is formed by the second etching in the manufacturing method of the present invention;

9 is a schematic diagram of the device structure after forming a gate dielectric layer in the manufacturing method of the present invention;

10 is a schematic diagram of the device structure after forming the gate electrode and the side split electrode in the manufacturing method of the present invention;

Fig. 11 is a schematic diagram of the device structure after all the steps in the manufacturing method of the present invention are completed.

Detailed ways

Below in conjunction with accompanying drawing and embodiment, describe technical solution of the present invention in detail:

Example 1

A double-split trench gate charge storage type RC-IGBT in this example has a cell structure as shown in Figure 2, including: a back collector metal 13, a P-type collector located on the back collector metal 13 and connected to it. The electrical region 11 and the N-type collector region 12, the N-type field stop layer 10 located on the P-type collector region 11 and the N-type collector region 12 and connected to it, the N-type field stop layer 10 located on and connected to it The N-drift region 9; the composite double-split trench structure located in the middle of the upper part of the N-drift region 9 and connected thereto; the N-type charge storage layer 8 located on both sides of the upper part of the N-drift region 9 and connected to it, the N-type The sidewall of the charge storage layer 8 is connected to the sidewall of the composite double-split trench structure, and the p-type base region 7 located on the upper part of the N-type charge storage layer 8 and connected thereto, the sidewall of the p-type base region 7 is connected to the composite double-split trench structure. The side walls of the double-split trench structure are connected; the N+ emitter region and the P+ emitter region independent of each other are located on the top of the p-type base region 7 and connected to it, and the side walls of the N+ emitter region are connected to the side walls of the composite double-split trench structure. Connected; the emitter metal 1 located on the upper surface of the N+ emitter region and the P+ emitter region; the dielectric layer 2 located on the upper part of the composite double-split trench structure; it is characterized in that: the composite double-split trench structure includes a lower structure and an upper layer structure; The lower structure includes a thick dielectric layer 45 and the bottom split electrode 31 disposed in the thick dielectric layer 45; the upper structure includes a trench gate electrode 32, a side split electrode 33, a dielectric layer 41, a dielectric layer 42, and a dielectric layer 43 And a dielectric layer 44, between the gate electrode 32 and the side split electrode 33 is a dielectric layer 43, between the gate electrode 32 and the side split electrode 33 and the bottom split electrode 31 is a dielectric layer 44, the trench gate electrode 32 is connected with the N+ emitter region 5 and the p-type base region 7 through the dielectric layer 41, and the side split electrode 33 is connected with the N+ emitter region 5 and the p-type base region 7 through the dielectric layer 42; the width of the lower structure is larger than the The width of the upper structure; the depth of the trench gate electrode 32 is greater than the junction depth of the p-type base region 7, the depth of the trench gate electrode 32 is less than the junction depth of the N-type charge storage layer 8, and the trench gate electrode 32 and the width of the side split electrode 33 are greater than the thickness of the dielectric layer 45 and the dielectric layer 44; the depth of the side split electrode 33 is greater than the junction depth of the p-type base region 7, and the depth of the side split electrode 33 is not less than the trench gate The depth of the electrode 32; the depth of the upper surface of the bottom split electrode 31 is less than the junction depth of the N-type charge storage layer 8, and the depth of the lower surface of the bottom split electrode 31 is greater than the junction depth of the N-type charge storage layer 8; the medium The thickness of the layers 45, 43 and 44 is greater than the thickness of the dielectric layer 41 and 42, and the thickness of the dielectric layer 42 is smaller than the thickness of the dielectric layer 41; the side split electrode 33 is connected with the emitter metal 1 on the surface, and the bottom split The electrode 31 is at the same potential as the emitter metal 1 . The formed trench gate electrode 32 has a depth greater than the junction depth of the p-type base region 7 by 0.1 to 0.2 microns, and the formed N-type charge storage layer 8 has a thickness of 1 to 2 microns; the formed bottom split electrode The depth of the upper surface of 31 is 0.5-1.5 microns less than the junction depth of the N-type charge storage layer 8, and the depth of the lower surface is 0.5-1 microns greater than the junction depth of the N-type charge storage layer 8; the thickness of the formed dielectric layer 41 is less than 120 nanometer, the thickness of the formed dielectric layer 42 is less than 40 nanometers, the formed width of the dielectric layer 43 is 0.5-1 micron, the formed thickness of the described dielectric layers 44 and 45 is 0.2-0.5 micron, and the formed The lower structure of the composite double-split trench structure is 0.2-1 micron wider than the upper structure on the left and right sides; by adjusting the concentration and thickness of the p-type base region 7 and the thickness and material of the dielectric layer 42, the parasitic The threshold voltage of the MOS structure is less than 0.1V.

Example 2

A double-split trench gate charge storage type RC-IGBT in this example has a cell structure as shown in Figure 3. The difference from Example 1 is that the lower part of the side split electrode 33 extends directly to the top of the bottom split electrode 31. On the surface, the side split electrode 33 is directly connected to the bottom split electrode 31 to further reduce the gate capacitance of the device.

Example 3

A double-split trench gate charge storage type RC-IGBT in this example has a cell structure as shown in Figure 3. The difference from Example 1 is that the underlying structure of the composite trench structure and the p-type base region Part of the region between 7 also has a layer of N+ layer 14, the concentration of the N+ layer 14 is greater than the concentration of the N-type charge storage layer 8 and its sidewall is connected to the composite trench structure, the formed N+ layer 14 further reduces The resistance of the area between the lower layer structure of the composite trench structure and the p-type base region 7 is reduced, the carrier injection enhancement effect of the emitter terminal is further improved, and better forward voltage drop and switching loss of the device can be obtained. compromise.

The specific implementation scheme of the process manufacturing method of the present invention is described by taking the double-split trench gate charge storage type RC-IGBT with a voltage level of 600V as an example, and the specific process manufacturing method is as follows:

Step 1: Select a lightly doped FZ silicon wafer with a doping concentration of 2×10 ¹⁴ /cm ³ and a thickness of 300-600 microns to form the N-drift region 9 of the device; Type impurity and annealing to make the N-type field stop layer 10 of the device, the thickness of the formed N-type field stop layer is 15-20 microns, the ion implantation energy is 1500keV-2000keV, the implantation dose is 5× ¹⁰¹³ / ^cm2 , annealing The temperature is 1200°C, and the annealing time is 400 minutes;

Step 2: Flip and thin the silicon wafer to a thickness of 90-95 microns, and form evenly distributed grooves on the surface of the silicon wafer by photolithography and etching. The groove depth is 0.5-2 microns and the width is 2-3 microns , the distance between the grooves is 0.5-1.5 microns;

The third step: form a thick oxide layer with a thickness of 0.2 to 0.5 microns around the trench at 1050 ° C to 1150 ° C in an _O2 atmosphere; then deposit and fill polysilicon in the trench at 850 ° C; oxidize and etch again Remove the excess oxide layer and form a thick oxide layer of 0.2 to 0.3 microns on the surface of polysilicon;

Step 4: Form an N-type doped layer with a thickness of 3-5 microns and a doping concentration of 2×10 ¹⁴ /cm ³ on the surface of the silicon wafer by epitaxy;

Step 5: Deposit a thin layer of pad oxide layer and silicon nitride layer on the surface of the silicon wafer. After the window is photolithographically etched, perform trench silicon etching again to etch the trench. The third step is polysilicon The oxide layer formed by surface oxidation can be used as the stop layer of silicon etching in this step; after the trench etching is completed, rinse the silicon nitride and pad oxide layer on the surface with a solution; the centerline of the trench formed in this step and the second step The center lines of the formed grooves coincide, and the width of the formed grooves is 0.6-1.5 microns;

Step 6: grow a high-quality thin oxide layer on the inner wall of the trench by thermal oxidation, and the thickness of the formed oxide layer is less than 60nm;

The seventh step: photolithography, etching the oxide layer formed on the left side wall of the trench in the sixth step;

Step 8: Re-grow a high-quality thin oxide layer on the inner wall of the trench by thermal oxidation, and the thickness of the formed oxide layer is less than 20nm;

Step 9: Deposit and fill polysilicon in the trench at 850°C;

The tenth step: photolithography, etching part of the polysilicon filled in the trench in the ninth step to form the gate electrode 32 and the side split electrode 33;

The eleventh step: depositing, filling the trench between the gate electrode 32 and the side split electrode 33 formed in the tenth step with a dielectric to form a dielectric layer 43;

The twelfth step: photolithography, first fabricate the N-type charge storage layer 8 of the device by ion implantation of N-type impurities, the energy of ion implantation is 500keV, and the implantation dose is 5×10 ¹³ /cm ² ; and then by ion implantation of P-type impurity and annealed to make the p-type base region 7 of the device, the ion implantation energy is 120keV, the implantation dose is 1×10 ¹⁴ /cm ² , the annealing temperature is 1100-1150°C, and the annealing time is 15-30 minutes; the formed p The junction depth of the N-type base region 7 is 0.1-0.2 microns shallower than the depth of the gate electrode 32, and the junction depth of the formed N-type charge storage layer 8 is greater than the depth of the gate electrode 32 and smaller than the depth of the bottom split electrode 31. The thickness of the type charge storage layer 8 is 1-2 micrometers;

The thirteenth step: photolithography, fabricate the N+ emission region of the device by ion implantation of N-type impurities, the ion implantation energy is 40keV, and the implantation dose is 1×10 ¹⁵ /cm ² ;

The fourteenth step: photolithography, the P+ emission region of the device is manufactured by ion implantation of P-type impurities and annealing. The ion implantation energy is 60keV, the implantation dose is 5×10 ¹⁵ /cm ² , the annealing temperature is 900°C, and the time is 30 minutes;

Step 15: Deposit a dielectric layer, and form a dielectric layer 2 by photolithography and etching;

Step 16: Deposit metal, and form metal collector 1 by photolithography and etching;

Step 17: Turn over the silicon wafer, reduce the thickness of the silicon wafer, photolithography and implant P-type impurities on the back of the silicon wafer to make the P-type collector region 11 of the device, the implantation energy is 60keV, and the implantation dose is 5×10 ¹² / cm ² ; photolithography again, by ion-implanting N-type impurities to fabricate the N-type collector region 12 of the device, the ion implantation energy is 60keV, and the implantation dose is 2×10 ¹⁴ /cm ² ; then mix H ₂ and N ₂ The back annealing is carried out under the atmosphere, the temperature is 450 ℃, and the time is 30 minutes;

Step 18: Deposit metal on the back to form the metal collector 13 .

That is, a double-split trench gate charge storage type RC-IGBT is prepared.

Further, the preparation of the N-type field stop layer 10 in the first step of the process steps can be carried out after the preparation of the front structure of the device is completed; or a double layer with the N-type field stop layer 10 and the N-drift region 9 can be directly selected. The epitaxial material is used as the silicon wafer material at the beginning of the process;

Further, the preparation of the N-type field stop layer 10 in the first step in the process steps can be omitted;

Further, before the ninth step of polysilicon deposition, an etching process can be added to remove the oxide layer under the side split electrode 33 by etching to form the device structure as shown in FIG. 3 ;

Further, before the sixth step of the oxidation process, the N+ layer 14 with high doping concentration is formed by implanting N-type impurities with angled ions or in the formation process of the N-type charge storage layer 8 in the twelfth step, by adding a step of photolithography and an ion implantation process to form a highly doped N+ layer 14, that is, to form a device structure as shown in FIG. 4;

Further, in the twelfth step of the process steps, the p-type base region 7 can be formed on both sides of the trench respectively by increasing the photolithography step twice, so that the concentration of the p-type base region 7 on the side close to the gate electrode 32 and the junction depth are greater than the concentration and junction depth of the P-type base region 7 near the side split electrode 33;

Further, the materials of the dielectric layers 41 , 42 , 43 , 44 and 45 can be the same or different.

Claims (5)

1. Double-split trench gate charge storage type RC-IGBT, including collector metal (13), P-type collector region (11), N-type electric field stop layer (10), N-type drift stacked sequentially from bottom to top region (9) and emitter metal (1); also includes an N-type collector region (12) juxtaposed with the P-type collector region (11); said N-type drift region (9) has an N+ emitter region ( 5), P+ emitter region (6), P-type base region (7), N-type charge storage layer (8) and trench gate structure; the trench gate structure runs through N+ emitter region (5), The P-type base region (7) and the N-type charge storage layer (8) extend into the N-type drift region; the P-type base region (7) is located on the upper surface of the N-type charge storage layer (8), and the N+ emitter region ( 5) and the P+ emitter (6) are juxtaposed on the upper surface of the P-type base region (7); the upper surfaces of the N+ emitter (5) and the P+ emitter (6) are connected to the emitter metal (1); it is characterized in that, The trench gate structure comprises a bottom split electrode (31), a gate electrode (32), a side split electrode (33), a gate dielectric layer (41), a second dielectric layer (42), a third dielectric layer (43), The fourth dielectric layer (44) and the fifth dielectric layer (45); the gate electrode (32) and the side split electrode (33) are connected through the third dielectric layer (43); the gate electrode (32) is connected by The gate dielectric layer (41) is connected to the N+ emitter region (5) and the P-type base region (7) on one side of the trench gate structure; the side split electrode (33) is connected to the trench gate through the second dielectric layer (42) The N+ emitter region (5) on the other side of the structure is connected to the P-type base region (7); the bottom split electrode (31) is located below the gate electrode (32) and the side split electrode (33), and the bottom split electrode ( 31) has an upper surface depth smaller than the junction depth of the N-type charge storage layer (8), and a lower surface depth of the bottom split electrode (31) is greater than the junction depth of the N-type charge storage layer (8); the bottom split electrode (31) The upper surface of the upper surface of the gate electrode (32) and the lower surface of the side split electrode (33) are connected by a fourth dielectric layer (44); the lower surface and side surfaces of the bottom split electrode (31) are connected to the N-type drift region ( 9) and the N-type charge storage layer (8) are connected through the fifth dielectric layer (45); the width of the bottom split electrode (31) is greater than that of the second dielectric layer (42), the side split electrode (33), the second dielectric layer The sum of the widths of the three dielectric layers (43), the gate electrode (32) and the gate dielectric layer (41) makes the trench gate structure an inverted "T" shape; the second dielectric layer (42), side split electrodes ( 33) and the upper surface of part of the third dielectric layer (43) is connected to the emitter metal (1); the upper surface of the gate dielectric layer (41), gate electrode (32) and part of the third dielectric layer (43) has The first dielectric layer (2); the bottom split electrode (31), the side split electrode (33) and the emitter metal (1) have the same potential. 2. The double split trench gate charge storage type RC-IGBT according to claim 1, characterized in that the third dielectric layer (43), the fourth dielectric layer (44) and the fifth dielectric layer (45) The thicknesses are all greater than the thickness of the gate dielectric layer (41); the thicknesses of the third dielectric layer (43), the fourth dielectric layer (44) and the fifth dielectric layer (45) are all greater than that of the second dielectric layer (42) Thickness; the thickness of the gate dielectric layer (41) is greater than the thickness of the second dielectric layer (42). 3. The double-split trench gate charge storage type RC-IGBT according to claim 1, characterized in that, both sides of the trench gate structure also have an N+ layer (14), the N+ layer (14) One side is connected to the N-type charge storage layer (8), the other side and the bottom of the N+ layer (14) are connected to the trench gate structure, and the upper surface of the N+ layer (14) is connected to the lower surface of the P-type base region (7). connect. 4. A method for manufacturing a double split trench gate charge storage type RC-IGBT, characterized in that it comprises the following steps: Step 1: Select an N-type lightly doped single crystal silicon wafer as the N-type drift region (9) of the device, the thickness of the selected silicon wafer is 300-600um, and the doping concentration is 10 ¹³ -10 ¹⁴ /cm ³ ; The N-type field stop layer (10) of the device is manufactured by ion-implanting N-type impurities on the back of the silicon wafer and annealed. The thickness of the formed N-type field stop layer is 15-30 microns, the ion implantation energy is 1500keV-2000keV, and the implantation dose is 10 ^{13-10 14} pieces/cm ² , the annealing temperature is 1200-1250°C, and the annealing time is 300-600 minutes; The second step: Flip and thin the silicon wafer to the required thickness, and form grooves on the surface of the silicon wafer by photolithography and etching; Step 3: Form an oxide layer around the trench at 1050°C to 1150°C in an O ₂ atmosphere; then deposit and fill polysilicon in the trench at 750°C to 950°C; oxidize again and etch away excess oxide layer; forming a bottom split electrode (31) and a fifth dielectric layer (45), the bottom split electrode (31) being located in the fifth dielectric layer (45); Step 4: Form an N-type doped layer with a thickness of 2 to 6 microns on the surface of the silicon wafer by epitaxy; Step 5: Deposit a thin layer of pad oxide layer and silicon nitride layer on the surface of the silicon wafer. After the window is photoetched, silicon trench etching is performed again, and a trench is etched above the bottom split electrode (31) In the third step, the oxide layer formed by oxidizing the surface of polysilicon can be used as the stop layer of silicon etching in this step; after the trench etching is completed, rinse the silicon nitride and pad oxide layer on the surface with a solution; the formed in this step The groove and the groove formed in the second step form an inverted "T" groove; Step 6: grow an oxide layer on the inner wall of the trench by thermal oxidation, and the thickness of the formed oxide layer is less than 120nm; Step 7: Using a photolithography process, etch the oxide layer formed on the left side wall of the trench in step 6; form a gate dielectric layer (41) on the right side wall of the trench; form a fourth dielectric layer at the bottom of the trench (44); Step 8: growing an oxide layer on the inner wall of the trench by thermal oxidation, and the thickness of the formed oxide layer is less than 40nm; forming a second dielectric layer (42) on the left side wall of the trench; Step 9: Deposit and fill polysilicon in the trench at 750°C to 950°C; Step 10: using a photolithography process to etch part of the polysilicon filled in the trench in the ninth step, and form gate electrodes (32) and side split electrodes (33) on both sides of the trench respectively; the gate electrodes (32) It is connected with the gate dielectric layer (41), and the side split electrode (33) is connected with the second dielectric layer (42); The eleventh step: depositing, filling the trench between the gate electrode (32) formed in the tenth step and the side split electrode (33) with a medium to form a third dielectric layer (43); The twelfth step: adopt photolithography process, first make the N-type charge storage layer (8) of device by ion-implanting N-type impurity, described N-type charge storage layer (8) is positioned at groove both sides; The energy of ion implantation is 200-500keV, the implantation dose is 10 ^{13-10 14} /cm ² ; then the P-type base region (7) is produced by ion-implanting P-type impurities and annealing, the energy of ion implantation is 60-120keV, and the implantation dose is 10 ^13- 10 ¹⁴ cells/cm ² , the annealing temperature is 1100-1150°C, and the annealing time is 10-30 minutes; the P-type base region (7) is located on the upper surface of the N-type charge storage layer (8); the formed N-type charge storage The junction depth of the layer (8) is greater than the depth of the gate electrode (32) and smaller than the depth of the bottom split electrode (31), and the junction depth of the formed P-type base region (7) is smaller than the depth of the gate electrode (32); The thirteenth step: using a photolithography process to fabricate the N+ emission region (5) of the device by ion-implanting N-type impurities, the energy of ion implantation is 30-60keV, and the implantation dose is 10 ^{15-10 16} pcs/cm ² ; The N+ emitter region (5) is located on the upper surface of the P-type base region (7) and connected to the trench; The fourteenth step: using photolithography technology, ion-implanting P-type impurities and annealing to fabricate the P+ emission region (6) of the device, the energy of ion implantation is 60-80keV, and the implantation dose is 10 ^{15-10 16} /cm ² , The annealing temperature is 900°C, and the time is 20 to 30 minutes; the P+ emission region (6) and the N+ emission region (5) are located side by side on the upper surface of the P-type base region (7); Step 15: deposit a dielectric layer on the surface of the device, and form a first dielectric layer (2) by photolithography and etching; the first dielectric layer (2) is located in part of the third dielectric layer (43), gate electrode ( 32) and the upper surface of the gate dielectric layer (41); The sixteenth step: deposit metal, and photolithography, etch on the upper surface of the N+ emitter region (5) and the P+ emitter region (6), as well as the second dielectric layer (42), side split electrodes (33) and part of the third The upper surface of the dielectric layer (43) forms the collector metal (1); The seventeenth step: turn over the silicon wafer, reduce the thickness of the silicon wafer, inject P-type impurities into the back of the silicon wafer to form a P-type collector region (11), and the P-type collector region (11) is located in the N-type electric field stop layer ( 10) On the lower surface, the implantation energy is 40-60keV, and the implantation dose is 10 ^{12-10 13} /cm ² ; photolithography is performed again, and the N-type collector region (12) of the device is fabricated by ion-implanting N-type impurities, and the ion-implanted The energy is 40-60keV, the implant dose is 10 ^{14-10 15} /cm ² ; then back annealing is carried out under the atmosphere mixed with H ₂ and N ₂ , the temperature is 400-450°C, and the time is 20-30 minutes; the said The N-type collector area (12) and the P-type collector area (11) are arranged side by side; Step 18: Deposit metal on the back to form collector metal (13). 5. The manufacturing method of double-split trench gate charge storage type RC-IGBT according to claim 4, characterized in that in the third step, the P-type base region can be formed in two steps by adding photolithography steps (7), make the concentration and junction depth of the P-type base region (7) near the gate electrode (32) side greater than the concentration and junction depth of the P-type base region (7) near the side split electrode (33) side.