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CN107146817A - 一种低压工艺中的高压nmos晶体管 - Google Patents

一种低压工艺中的高压nmos晶体管 Download PDF

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Publication number
CN107146817A
CN107146817A CN201710567225.9A CN201710567225A CN107146817A CN 107146817 A CN107146817 A CN 107146817A CN 201710567225 A CN201710567225 A CN 201710567225A CN 107146817 A CN107146817 A CN 107146817A
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voltage
substrate psub
low
type doped
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不公告发明人
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Changsha Party Xingteng Electronic Technology Co Ltd
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Changsha Party Xingteng Electronic Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供了一种低压工艺中的高压NMOS晶体管，属于半导体集成电路技术领域。该晶体管包括：P型衬底PSUB、N型阱NWELL、第一N型掺杂N+1、第二N型掺杂N+2和多晶硅POLY；本发明在传统的低压NMOS晶体管的基础上，在第二N型掺杂N+2的外围增加了N型阱NWELL，使得第二N型掺杂N+2不直接与P型衬底PSUB接触。由于二极管的掺杂特性，第二N型掺杂N+2与P型衬底PSUB形成的寄生PN结二极管的反向击穿电压远低于N型阱NWELL与P型衬底PSUB形成的寄生PN结二极管的反向击穿电压，这样就使得器件的漏极D比低压器件的漏极能够承受更高的电压，符合很多高压场合的应用要求。

Description

一种低压工艺中的高压NMOS晶体管
技术领域
本发明属于半导体集成电路技术领域，具体涉及一种低压工艺中的高压NMOS晶体管。
背景技术
目前在电源管理芯片等产品中，为了节约面积，数字电路部分常常需要用到低压器件，而为了更好的耐压，模拟电路部分则需要用到高压器件。所以，在很多芯片上，需要同时集成高压器件和低压器件。
为了应对这种趋势，目前传统的做法是在低压工艺的基础上，引入了高压工艺。高压工艺，需要在低压工艺的基础上，增加高压的P型注入层、N型注入层、高压的P阱、高压N阱等多层掩模板，这大大提高了芯片的成本，增加了芯片的制作流程，延长了芯片的产出时间。
发明内容
为解决现有高压工艺导致芯片成本过高、产出时间过长的技术问题，本发明提供了一种低压工艺中的高压NMOS晶体管。
一种低压工艺中的高压NMOS晶体管，包括：P型衬底PSUB、N型阱NWELL、第一N型掺杂N+1、第二N型掺杂N+2和多晶硅POLY；P型衬底PSUB位于最下方；N型阱NWELL、第一N型掺杂N+1和第二N型掺杂N+2都做在P型衬底PSUB上；第一N型掺杂N+1位于P型衬底PSUB的左上方；第二N型掺杂N+2位于P型衬底PSUB的右上方，与第一N型掺杂N+1左右对称；N型阱NWELL将第二N型掺杂N+2包围，使其不与P型衬底PSUB直接接触；在第一N型掺杂N+1和第二N型掺杂N+2的间隙的正上方，是层多晶硅POLY，它是器件的栅极G；第一N型掺杂N+1是器件的源极S；第二N型掺杂N+2是器件的漏极D。
本发明提供的低压工艺中的高压NMOS晶体管，在传统的低压NMOS晶体管的基础上，在第二N型掺杂N+2的外围增加了N型阱NWELL，使得第二N型掺杂N+2不直接与P型衬底PSUB接触。由于二极管的掺杂特性，第二N型掺杂N+2与P型衬底PSUB形成的寄生PN结二极管的反向击穿电压远低于N型阱NWELL与P型衬底PSUB形成的寄生PN结二极管的反向击穿电压，这样就使得器件的漏极D比低压器件的漏极能够承受更高的电压，符合很多高压场合的应用要求。
附图说明
图1是本发明实施方式提供的低压工艺中的高压NMOS晶体管的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明了，下面结合具体实施方式并参照附图，对本发明进一步详细说明。应该理解，这些描述只是示例性的，而并非要限制本发明的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本发明的概念。
为解决现有高压工艺导致芯片成本过高、产出时间过长的技术问题，本发明提供了一种低压工艺中的高压NMOS晶体管。如图1所示，低压工艺中的高压NMOS晶体管包括：P型衬底PSUB、N型阱NWELL、第一N型掺杂N+1、第二N型掺杂N+2和多晶硅POLY；P型衬底PSUB位于最下方；N型阱NWELL、第一N型掺杂N+1和第二N型掺杂N+2都做在P型衬底PSUB上；第一N型掺杂N+1位于P型衬底PSUB的左上方；第二N型掺杂N+2位于P型衬底PSUB的右上方，与第一N型掺杂N+1左右对称；N型阱NWELL将第二N型掺杂N+2包围，使其不与P型衬底PSUB直接接触；在第一N型掺杂N+1和第二N型掺杂N+2的间隙的正上方，是层多晶硅POLY，它是器件的栅极G；第一N型掺杂N+1是器件的源极S；第二N型掺杂N+2是器件的漏极D。
本发明提供的低压工艺中的高压NMOS晶体管，在传统的低压NMOS晶体管的基础上，在第二N型掺杂N+2的外围增加了N型阱NWELL，使得第二N型掺杂N+2不直接与P型衬底PSUB接触。由于二极管的掺杂特性，第二N型掺杂N+2与P型衬底PSUB形成的寄生PN结二极管的反向击穿电压远低于N型阱NWELL与P型衬底PSUB形成的寄生PN结二极管的反向击穿电压，这样就使得器件的漏极D比低压器件的漏极能够承受更高的电压，符合很多高压场合的应用要求。
应当理解的是，本发明的上述具体实施方式仅仅用于示例性说明或解释本发明的原理，而不构成对本发明的限制。因此，在不偏离本发明的精神和范围的情况下所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。此外，本发明所附权利要求旨在涵盖落入所附权利要求范围和边界、或者这种范围和边界的等同形式内的全部变化和修改例。

Claims (1)

1.一种低压工艺中的高压NMOS晶体管，其特征在于，包括：
P型衬底PSUB、N型阱NWELL、第一N型掺杂N+1、第二N型掺杂N+2和多晶硅POLY；P型衬底PSUB位于最下方；N型阱NWELL、第一N型掺杂N+1和第二N型掺杂N+2都做在P型衬底PSUB上；第一N型掺杂N+1位于P型衬底PSUB的左上方；第二N型掺杂N+2位于P型衬底PSUB的右上方，与第一N型掺杂N+1左右对称；N型阱NWELL将第二N型掺杂N+2包围，使其不与P型衬底PSUB直接接触；在第一N型掺杂N+1和第二N型掺杂N+2的间隙的正上方，是层多晶硅POLY，它是器件的栅极G；第一N型掺杂N+1是器件的源极S；第二N型掺杂N+2是器件的漏极D。
CN201710567225.9A 2017-07-12 2017-07-12 一种低压工艺中的高压nmos晶体管 Withdrawn CN107146817A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112992895A (zh) * 2021-01-27 2021-06-18 复旦大学 GaN基开关集成单元与GaN基开关管的晶圆结构的制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4907048A (en) * 1987-11-23 1990-03-06 Xerox Corporation Double implanted LDD transistor self-aligned with gate
CN1375879A (zh) * 2001-02-16 2002-10-23 佳能株式会社 半导体器件及其制造方法和喷液设备
US6624487B1 (en) * 2002-05-07 2003-09-23 Texas Instruments Incorporated Drain-extended MOS ESD protection structure
CN1866541A (zh) * 2005-05-12 2006-11-22 英飞凌科技股份公司 场效应晶体管和制造场效应晶体管的方法
CN102376574A (zh) * 2010-08-09 2012-03-14 上海宏力半导体制造有限公司 半导体器件及其制造方法
CN104505399A (zh) * 2014-12-18 2015-04-08 杭州捷茂微电子有限公司 一种用于栅极接地nmos结构esd保护器件

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4907048A (en) * 1987-11-23 1990-03-06 Xerox Corporation Double implanted LDD transistor self-aligned with gate
CN1375879A (zh) * 2001-02-16 2002-10-23 佳能株式会社 半导体器件及其制造方法和喷液设备
US6624487B1 (en) * 2002-05-07 2003-09-23 Texas Instruments Incorporated Drain-extended MOS ESD protection structure
CN1866541A (zh) * 2005-05-12 2006-11-22 英飞凌科技股份公司 场效应晶体管和制造场效应晶体管的方法
CN102376574A (zh) * 2010-08-09 2012-03-14 上海宏力半导体制造有限公司 半导体器件及其制造方法
CN104505399A (zh) * 2014-12-18 2015-04-08 杭州捷茂微电子有限公司 一种用于栅极接地nmos结构esd保护器件

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112992895A (zh) * 2021-01-27 2021-06-18 复旦大学 GaN基开关集成单元与GaN基开关管的晶圆结构的制备方法

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Application publication date: 20170908