CN106876256A - SiC double flute UMOSFET devices and preparation method thereof - Google Patents

Abstract

The invention relates to a method for preparing a SiC double-slot UMOSFET device, which is characterized in that it comprises: selecting a SiC substrate; growing a drift layer, an epitaxial layer and a source layer on the continuous surface of the SiC substrate; 1. Etching the epitaxial layer and the drift layer to form a gate groove; performing ion implantation on the gate groove to form a gate dielectric protection area; etching the source region layer, the epitaxial layer and the drift layer Forming a source trench; performing ion implantation on the source trench to form a source trench corner protection area; growing a gate dielectric layer and a gate layer in the gate trench to form a gate; passivation treatment and preparing electrodes to form the SiC double slot UMOSFET devices. The present invention forms a Schottky contact at the interface between the source electrode and the drift layer and the epitaxial layer, while ensuring that the problem of "power-on degradation" of the body diode is not caused, additional Schottky diodes are reduced, and the reliability of the device is improved. And reduce the complexity and cost of device design.

Description

SiC double-slot UMOSFET device and its preparation method

technical field

The invention relates to the technical field of integrated circuits, in particular to a SiC double-slot UMOSFET device and a preparation method thereof.

Background technique

The wide bandgap semiconductor material SiC has excellent physical and chemical properties such as large bandgap width, high critical breakdown electric field, high thermal conductivity and high electron saturation drift velocity, and is suitable for making high temperature, high pressure, high power, radiation resistant Semiconductor device. In the field of power electronics, power MOSFET has been widely used, it has the characteristics of simple gate drive and short switching time. Compared with the horizontal structure MOSFET, the vertical structure UMOSFET has the advantages of small on-resistance and small cell size, and has broad application prospects.

However, in UMOSFET, the electric field concentration at the corner of the trench gate can easily lead to premature breakdown of the oxide layer, and this phenomenon is more serious for SiC materials. By designing a layer of P+ doped region, namely P+ gate dielectric protection region, at the bottom of the gate groove, the peak electric field at the bottom of the groove is transferred from the gate oxide layer to the PN junction formed by the P+ gate dielectric protection region and the N-drift layer. , thereby alleviating the reliability problem caused by the gate oxide electric field. And for the UMOSFET with double-groove structure, by carving a groove on the source, the depth of this region into the N-drift layer is greater than the depth of the gate oxide in the N-drift layer. Using this, the electric field at the oxide layer is due to the existence of the source groove And transferred to the corner of the source trench, further improving the breakdown characteristics of the device. At the same time, the MOSFET is used as a power switch in the converter. When its body diode continues to flow forward current as a freewheeling path, the phenomenon of "power-on deterioration" will occur, which will increase the on-resistance and the forward conduction voltage drop of the diode. and cause reliability issues.

Therefore, in practical applications, a Schottky diode whose turn-on voltage is lower than that of the body diode is usually connected in parallel across the source and drain of the device to provide a freewheeling path. Obviously, this method greatly increases the complexity and cost of circuit design.

Contents of the invention

Therefore, in order to solve the technical defects and deficiencies existing in the prior art, the present invention proposes a method for preparing a SiC double-slot UMOSFET device.

Specifically, a method for preparing a SiC double-slot UMOSFET device proposed by an embodiment of the present invention includes:

Step 1. Select the SiC substrate;

Step 2, growing a drift layer, an epitaxial layer and a source region layer on the continuous surface of the SiC substrate;

Step 3, etching the source region layer, the epitaxial layer and the drift layer to form gate grooves;

Step 4, performing ion implantation on the gate groove to form a gate dielectric protection area;

Step 5. Etching the source region layer, the epitaxial layer and the drift layer to form source trenches;

Step 6, performing ion implantation on the source groove to form a corner protection area of the source groove;

Step 7, growing a gate dielectric layer and a gate layer in the gate groove to form a gate;

Step 8, passivating and preparing electrodes to form the SiC double-slot UMOSFET device.

In one embodiment of the invention, step 2 includes:

Step 21, using an epitaxial growth process to grow the drift layer on the surface of the SiC substrate;

Step 22, using an epitaxial growth process to grow the epitaxial layer on the surface of the drift layer;

Step 23 , epitaxially growing the source region layer on the surface of the epitaxial layer by using an epitaxial growth process.

In one embodiment of the present invention, step 3 includes:

The surface of the source region layer is etched by using the first mask plate by using an ICP etching process, and the gate groove is formed in the source region layer, the epitaxial layer and the drift layer.

In one embodiment of the present invention, step 4 includes:

Using a self-aligned implantation process and using a first mask plate, Al ion implantation is performed on the gate groove to form the gate dielectric protection region in the drift layer.

In one embodiment of the present invention, step 5 includes:

The surface of the source region layer is etched by using a second mask plate by using an ICP etching process, and the source groove is formed in the source region layer, the epitaxial layer and the drift layer.

In one embodiment of the present invention, step 6 includes:

Using a self-aligned implantation process and using a second mask plate, Al ion implantation is performed on the source trench to form a corner protection area of the source trench in the drift layer.

In one embodiment of the present invention, performing Al ion implantation on the source groove includes:

Using an implantation energy of 450keV and an implantation dose of 7.97×10 ¹³ cm ^-2 , perform the first Al ion implantation on the source groove;

Using an implant energy of 300keV and an implant dose of 4.69×10 ¹³ cm ^-2 , perform a second Al ion implantation on the source groove;

Using an implant energy of 200keV and an implant dose of 3.27×10 ¹³ cm ^-2 , perform a third Al ion implantation on the source groove;

The fourth Al ion implantation was performed on the source trench by using an implantation energy of 120keV and an implantation dose of 2.97×10 ¹³ cm ⁻² .

In one embodiment of the present invention, step 7 includes:

Using a dry oxygen process, growing _SiO2 material in the gate trench to form the gate dielectric layer;

growing a polycrystalline Si material in the gate groove by using a HWLPCVD process to form the gate layer;

In one embodiment of the present invention, step 8 includes:

growing a passivation layer on the surface of the substrate including the gate;

Etching the passivation layer on the surface of the gate by an etching process to form an electrode contact hole;

Using an electron beam evaporation process, growing a metal material in the source groove and the electrode contact hole to form a source electrode and a gate electrode;

Using an electron beam evaporation process, a metal material is grown on the lower surface of the substrate to form a drain electrode to finally form the SiC double-groove UMOSFET device.

A SiC double-slot UMOSFET device proposed in another embodiment of the present invention is prepared by the method provided in the above embodiment.

In the above embodiment, by forming a Schottky contact at the interface between the source electrode and the N-drift layer and the epitaxial layer, the external Schottky diode is replaced as a freewheeling path, while ensuring that the problem of "conduction degradation" of the body diode is not caused , reducing additional Schottky diodes, improving device reliability and reducing device design complexity and cost. In addition, the present invention uses the double-slot structure of the double-slot UMSFET to form a P+ gate dielectric protection area and a P+ source slot corner protection area through an ion self-alignment process without photolithography, which further improves the breakdown characteristics of the device. Better device performance is achieved with a smaller process cost.

Other aspects and features of the present invention will become apparent from the following detailed description with reference to the accompanying drawings. It should be understood, however, that the drawings are designed for purposes of illustration only and not as a limitation of the scope of the invention since reference should be made to the appended claims. It should also be understood that, unless otherwise indicated, the drawings are not necessarily drawn to scale and are merely intended to conceptually illustrate the structures and processes described herein.

Description of drawings

The specific implementation manners of the present invention will be described in detail below in conjunction with the accompanying drawings.

FIG. 1 is a schematic structural diagram of a SiC double-slot UMOSFET device provided by an embodiment of the present invention;

2 is a schematic diagram of a method for preparing a SiC double-slot UMOSFET device provided by an embodiment of the present invention;

3a-3k are process schematic diagrams of a SiC double-slot UMOSFET device provided by an embodiment of the present invention.

detailed description

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

Embodiment one

Please refer to FIG. 1 , which is a schematic structural diagram of a SiC double-slot UMOSFET device provided by an embodiment of the present invention. The SiC double-slot UMOSFET device of the present invention includes a drain 11, an N+ substrate 1, an N-drift layer 2, a P-epitaxy layer 3, an N+ source region layer 4, a source 10, a P+ source groove corner protection region 6, and a groove gate dielectric 7. Polysilicon 8, P+ gate dielectric protection area 5, gate electrode 9.

Preferably, the depth of the source groove is greater than the depth of the gate groove, and the width of the source groove is equal to the width of the P+ source groove corner protection area 6; the width of the gate groove is equal to the width of the P+ gate dielectric protection area 5, and the source 10 and N - The interface between the drift layer 2 and the P-epitaxial layer 3 is a Schottky contact, the rest are ohmic contacts.

Optionally, the depth of the source trench is 3 μm, and the depth of the gate trench is 2.5 μm, which are formed by inductively coupled plasma (ICP for short) etching. The widths of the source groove and the P+ source groove corner protection region 6 are 1 μm respectively, and the widths of the gate groove and the P+ gate dielectric protection region 5 are 1.5 μm respectively.

Optionally, the N+ substrate 1 is an N-type SiC substrate 1 with a thickness of 200 μm-500 μm and a nitrogen ion doping concentration of 5×10 ¹⁸ cm ⁻³ to 1×10 ²⁰ cm ⁻³ . The N-drift layer 2 is an N-type SiC epitaxial layer with a thickness of 10 μm to 20 μm and a nitrogen ion doping concentration of 1×10 ¹⁵ cm ⁻³ to 6×10 ¹⁵ cm ⁻³ .

Optionally, the P+ source groove corner protection region 6 has a thickness of 0.5 μm, and an Al ion doping concentration of 3×10 ¹⁸ cm ⁻³ . The P+ gate dielectric protection region 5 has a thickness of 0.5 μm and an Al ion doping concentration of 3×10 ¹⁸ cm ⁻³ .

Optionally, the P- epitaxial layer 3 is a P-type SiC epitaxial layer with a thickness of 1 μm˜1.5 μm and an Al ion doping concentration of 1×10 ¹⁷ cm ⁻³ . The N+ source region layer 4 is an N-type SiC epitaxial layer with a thickness of 0.5 μm and a nitrogen ion doping concentration of 5×10 ¹⁸ cm ⁻³ .

Optionally, the trench gate dielectric 7 is silicon dioxide with a thickness of 100 nm, formed by a dry oxygen process. The polysilicon 8 is poly Si with a depth of 2.4 μm and a width of 1.3 μm, and is deposited to fill the entire gate groove structure. A field oxide layer or Si ₃ N ₄ layer is deposited as a passivation layer, and the passivation layer is etched to open electrode holes. The gate electrode 9, drain 11 and source 10 and their Schottky contacts are formed by electron beam evaporation of metals.

In the embodiment of the present invention, the present invention replaces the externally connected Schottky diode as a freewheeling path by introducing a Schottky diode into the source tank, reducing the additional Schottky diode while ensuring that the problem of "power-on degradation" of the body diode is not caused. The base diode improves the reliability of the device and reduces the complexity and cost of device design.

It should be noted that the gate involved in the present invention refers to an integral structure including a gate dielectric layer and a gate material layer, for example, the gate is an integral structure formed of gate oxide material and polysilicon material. The gate electrode in the present invention refers to the metal material deposited on the surface of the gate in the present invention for the purpose of metallizing interconnection, and similar expressions such as source electrode and drain electrode are also used.

Embodiment two

Please refer to FIG. 2 . FIG. 2 is a schematic diagram of a method for fabricating a SiC double-slot UMOSFET device provided by an embodiment of the present invention. The preparation method may comprise the steps of:

Step 1. Select the SiC substrate;

Step 2, growing a drift layer, an epitaxial layer and a source region layer on the continuous surface of the SiC substrate;

Step 3, etching the source region layer, the epitaxial layer and the drift layer to form gate grooves;

Step 4, performing ion implantation on the gate groove to form a gate dielectric protection area;

Step 5. Etching the source region layer, the epitaxial layer and the drift layer to form source trenches;

Step 6, performing ion implantation on the source groove to form a corner protection area of the source groove;

Step 7, growing a gate dielectric layer and a gate layer in the gate groove to form a gate;

Step 8, passivating and preparing electrodes to form the SiC double-slot UMOSFET device.

Optionally, for step 2, may include:

Step 21, using an epitaxial growth process to grow the drift layer on the surface of the SiC substrate;

Step 22, using an epitaxial growth process to grow the epitaxial layer on the surface of the drift layer;

Step 23 , epitaxially growing the source region layer on the surface of the epitaxial layer by using an epitaxial growth process.

Specifically, for step 21, including:

A drift layer doped with nitrogen ions of 10 μm to 20 μm is grown on an N-type SiC substrate, the doping concentration is 1×10 ¹⁵ cm ^-3 to 6×10 ¹⁵ cm ^-3 , the epitaxy temperature is 1600°C, the pressure is 100mbar, and the reaction The gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is liquid nitrogen;

Specifically, for step 22, including:

A 1μm-1.5μm Al ion-doped epitaxial layer is grown on the nitrogen ion-doped drift layer, the doping concentration is 1×10 ¹⁷ cm ^-3 ～1×10 ¹⁸ cm ^-3 , the epitaxy temperature is 1600°C, and the pressure is 100mbar , the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is trimethylaluminum;

Specifically, for step 23, including:

A source region layer doped with 0.5 μm nitrogen ions is grown on the epitaxial layer, the doping concentration is 5×10 ¹⁸ cm ^-3 , the epitaxial temperature is 1600°C, the pressure is 100 mbar, the reaction gas is silane and propane, and the carrier gas is pure Hydrogen, the impurity source is liquid nitrogen;

Optionally, for step 3, may include:

The surface of the source region layer is etched by using the first mask plate by using an ICP etching process, and the gate groove is formed in the source region layer, the epitaxial layer and the drift layer.

Specifically, for step 3, include:

Using the ICP process, etch to form a gate groove with a width of 1.5 μm and a depth of 2.5 μm, of which, the ICP coil power is 850W, the source power is 100W, and the reaction gas SF ₆ and O ₂ are 48 sccm and 12 sccm respectively;

Optionally, for step 4, may include:

Using a self-aligned implantation process and using a first mask plate, Al ion implantation is performed on the gate groove to form the gate dielectric protection region in the drift layer.

Specifically, for step 4, include:

Al ion self-aligned implantation was performed multiple times in the drift layer by using the etching mask of the gate trench to form a gate dielectric protection area with a depth of 0.5 μm and a concentration of 3×10 ¹⁸ cm ^-3 , and the implantation temperature was 650°C.

Optionally, for step 5, may include:

The surface of the source region layer is etched by using a second mask plate by using an ICP etching process, and the source groove is formed in the source region layer, the epitaxial layer and the drift layer.

Specifically, for step 5, include:

The source groove is formed by etching by ICP process, the width is 1μm, the depth is 3μm, the ICP coil power is 850W, the source power is 100W, and the reaction gas _SF6 and _O2 are 48sccm and 12sccm respectively;

Optionally, for step 6, may include:

Using a self-aligned implantation process and using a second mask plate, Al ion implantation is performed on the source trench to form a corner protection area of the source trench in the drift layer.

Wherein, performing Al ion implantation on the source tank includes:

Using implant energy of 450keV and implant dose of 7.97×10 ¹³ cm ^-2 , perform the first Al ion implantation on the gate groove;

Using an implant energy of 300keV and an implant dose of 4.69×10 ¹³ cm ^-2 , perform a second Al ion implantation on the gate groove;

Using an implant energy of 200keV and an implant dose of 3.27×10 ¹³ cm ^-2 , perform Al ion implantation on the gate groove for the third time;

A fourth Al ion implantation is performed on the gate trench by using an implantation energy of 120keV and an implantation dose of 2.97×10 ¹³ cm ⁻² .

Specifically, for step 6, include:

Using the etch mask of the source trench to carry out self-aligned implantation of Al ions multiple times in the drift layer to form a protection area at the corner of the source trench with a depth of 0.5 μm and a concentration of 3×10 ¹⁸ cm ^-3 , and the implantation temperature is 650°C;

Optionally, for step 7, may include:

Using a dry oxygen process, growing _SiO2 material in the gate trench to form the gate dielectric layer;

Using a hot wall low pressure chemical vapor deposition (hot wall low pressure chemical vapor deposition, HWLPCVD for short) process, growing polycrystalline Si material in the gate trench to form the gate layer;

Specifically, step 7 includes:

Prepare the SiO ₂ gate dielectric layer at 1150°C by dry oxygen process with a thickness of 100nm, and then anneal at 1050°C in NO atmosphere to reduce the roughness of the SiO ₂ film surface;

The HWLPCVD process is used to grow poly Si to fill the gate groove, the deposition temperature is 600-650°C, the deposition pressure is 60-80Pa, the reaction gas is silane and phosphine, and the carrier gas is helium;

Optionally, for step 8, may include:

growing a passivation layer on the surface of the substrate including the gate;

Etching the passivation layer on the surface of the gate by an etching process to form an electrode contact hole;

Using an electron beam evaporation process, growing a metal material in the source groove and the electrode contact hole to form a source electrode and a gate electrode 9;

Using an electron beam evaporation process, a metal material is grown on the lower surface of the substrate to form a drain electrode to finally form the SiC double-groove UMOSFET device.

Specifically, step 8 includes:

Deposit a layer of field oxygen or Si ₃ N ₄ on the surface of the device, and then open electrode contact holes;

Ti/Ni/Au was evaporated by electron beam to prepare electrodes, and finally annealed rapidly in Ar atmosphere for 3min at a temperature of 1050°C. Because the doping concentration of the drift layer and the epitaxial layer is low, a Schottky contact is formed at the interface between the source electrode and the drift layer and the epitaxial layer, and ohmic contacts are formed at other interfaces.

In the embodiment of the present invention, the present invention replaces the externally connected Schottky diode as a freewheeling path by introducing a Schottky diode into the source tank, reducing the additional Schottky diode while ensuring that the problem of "power-on degradation" of the body diode is not caused. The base diode improves the reliability of the device and reduces the complexity and cost of device design. In addition, the embodiment of the present invention utilizes the double-groove structure of the dual-groove UMSFET to form the gate dielectric protection area and the source groove corner protection area through the ion self-alignment process without photolithography, which further improves the breakdown characteristics of the device. Better device performance is achieved with a smaller process cost.

Embodiment two

Please refer to FIG. 3. FIG. 3 provides another SiC double-slot UMOSFET device preparation method for this embodiment. The preparation method includes the following steps:

In step a, an N-drift layer 2 is epitaxially grown on an N-type SiC substrate 1, as shown in FIG. 3a.

RCA standard cleaning was performed on the N-type SiC substrate with a thickness of 200 μm and a nitrogen ion doping concentration of 5×10 ¹⁸ cm ^-3 , and then epitaxial growth was performed on the entire SiC substrate 1 with a thickness of 10 μm and a nitrogen ion doping concentration of 1×10 ¹⁵ cm ⁻³ of N-drift layer 2. The process conditions are as follows: temperature is 1600°C, pressure is 100mbar, reaction gas is silane and propane, carrier gas is pure hydrogen, and impurity source is liquid nitrogen.

Step b, epitaxially growing the P- epitaxial layer 3, as shown in FIG. 3b.

A P-epitaxial layer 3 with a thickness of 1 μm and an Al ion doping concentration of 1×10 ¹⁷ cm ⁻³ is grown on the N-drift layer 2 . The process conditions are as follows: the temperature is 1600°C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is trimethylaluminum.

Step c, epitaxially growing the N+ source region layer 4, as shown in FIG. 3c.

An N+ source region layer 4 with a thickness of 0.5 μm and a nitrogen ion doping concentration of 5×10 ¹⁸ cm ⁻³ is grown on the P − epitaxial layer 3 . The process conditions are as follows: temperature is 1600°C, pressure is 100mbar, reaction gas is silane and propane, carrier gas is pure hydrogen, and impurity source is liquid nitrogen.

In step d, gate grooves are formed by etching, as shown in FIG. 3d.

First magnetron sputtering a layer The Ti film is used as an ICP etching mask, and then coated with photolithography, and ICP etching is performed. The width of the etched groove is 1.5 μm, and the depth is 2.5 μm. Finally, the glue is removed, the etching mask is removed, and it is cleaned into a light sheet . The process conditions are: ICP coil power 850W, source power 100W, reaction gas _SF6 and _O2 are 48sccm and 12sccm respectively.

In step e, self-aligned implantation of Al ions is performed multiple times in the N-drift layer 2 by using the etching mask of the gate groove, as shown in FIG. 3e.

The implantation ^energies of ^450keV , ^300keV , ^200keV and ^120keV were ^{adopted successively} , and ^Al Ions are implanted into the implantation region of the N-drift layer 2 in four times to form a P+ gate dielectric protection region 5 with a depth of 0.5 μm and a concentration of 3×10 ¹⁸ cm ⁻³ , and the implantation temperature is 650° C.

In step f, source grooves are formed by etching, as shown in FIG. 3f.

First magnetron sputtering a layer The Ti film is used as an ICP etching mask, and then glued to photolithography, and ICP etching is performed, and the width of the etched groove is 1 μm, and the depth is 3 μm. Finally, the glue is removed, the etching mask is removed, and a light sheet is cleaned. The process conditions are: ICP coil power 850W, source power 100W, reaction gas _SF6 and _O2 are 48sccm and 12sccm respectively.

In step g, self-aligned implantation of Al ions is performed on the N-drift layer 2 for multiple times by using the etching mask of the source trench, as shown in FIG. 3g.

Firstly, the implantation energies of 450keV, 300keV, 200keV and 120keV were adopted successively, and the implant doses were 7.97×10 ¹³ cm ^-2 , 4.69×10 ¹³ cm ^-2 , 3.27×10 ¹³ cm ^-2 and 2.97×10 ¹³ cm ^-2 Al ions are implanted into the implantation region of the N-drift layer 2 in four times to form a P+ source groove corner protection region 6 with a depth of 0.5 μm and a concentration of 3×10 ¹⁸ cm ^-3 , and the implantation temperature is 650°C.

Then use the RCA cleaning standard to clean the SiC surface, make a C film protection after drying, and then perform ion activation annealing in an argon atmosphere at 1700-1750 ° C for 10 minutes.

In step h, trench gate dielectric 7 is prepared, and the material used is SiO ₂ , as shown in FIG. 3h.

The SiO ₂ gate dielectric layer was prepared at 1150°C by dry oxygen process with a thickness of 100nm, and then annealed at 1050°C in NO atmosphere to reduce the roughness of the SiO ₂ film surface.

Step i, preparing a poly Si gate, as shown in Figure 3i.

Poly Si is grown by low-pressure hot-wall chemical vapor deposition to fill the gate groove, the deposition temperature is 600-650°C, the deposition pressure is 60-80Pa, the reaction gas is silane and phosphine, and the carrier gas is helium. Then glue photolithography, etch the polySi layer to form a polysilicon gate, and finally remove the glue and clean.

Step j, preparing a passivation layer, as shown in Figure 3j.

Deposit a layer of field oxygen or Si ₃ N ₄ on the surface of the device, then apply glue for photolithography, etch the passivation layer to open electrode contact holes, and finally remove the glue and clean.

In step k, an electrode is prepared, as shown in FIG. 3k.

First, the front electron beam evaporates Ti/Ni/Au to make the gate and source electrode, then apply glue and photolithography, corrode the metal to form the gate, source electrode, remove the glue, and clean.

Then Ti/Ni/Au is evaporated by electron beam on the back side to make the drain electrode, and finally annealed rapidly in Ar atmosphere for 3min at a temperature of 1050°C. Because the doping concentration of the N-drift layer 2 and the P-epitaxial layer 3 is relatively low, a Schottky contact is formed at the interface between the source electrode 10 and the N-drift layer 2 and the P-epitaxial layer 3 , and ohmic contacts are formed at other interfaces.

Embodiment three

Please refer to FIG. 3. FIG. 3 provides another SiC double-slot UMOSFET device preparation method for this embodiment. The preparation method includes the following steps:

In step a, an N-drift layer 2 is epitaxially grown on an N-type SiC substrate 1, as shown in FIG. 3a.

RCA standard cleaning is performed on the N-type SiC substrate 1 with a thickness of 500 μm and a nitrogen ion doping concentration of 1×10 ²⁰ cm ^-3 , and then epitaxial growth on the entire SiC substrate 1 with a thickness of 20 μm and a nitrogen ion doping concentration of The N-drift layer 2 is 3×10 ¹⁵ cm ^-3 . The process conditions are as follows: temperature is 1600°C, pressure is 100mbar, reaction gas is silane and propane, carrier gas is pure hydrogen, and impurity source is liquid nitrogen.

Step b, epitaxially growing the P- epitaxial layer 3, as shown in FIG. 3b.

A P-epitaxial layer 3 with a thickness of 1.5 μm and an Al ion doping concentration of 1×10 ¹⁷ cm ⁻³ is grown on the N-drift layer 2 . The process conditions are as follows: the temperature is 1600°C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is trimethylaluminum.

Step c, epitaxially growing the N+ source region layer 4, as shown in FIG. 3c.

An N+ source region layer 4 with a thickness of 0.5 μm and a nitrogen ion doping concentration of 5×10 ¹⁸ cm ⁻³ is grown on the P − epitaxial layer 3 . The process conditions are as follows: temperature is 1600°C, pressure is 100mbar, reaction gas is silane and propane, carrier gas is pure hydrogen, and impurity source is liquid nitrogen.

In step d, gate grooves are formed by etching, as shown in FIG. 3d.

First magnetron sputtering a layer The Ti film is used as an ICP etching mask, and then coated with photolithography, and ICP etching is performed. The width of the etched groove is 1.5 μm, and the depth is 2.5 μm. Finally, the glue is removed, the etching mask is removed, and it is cleaned into a light sheet . The process conditions are: ICP coil power 850W, source power 100W, reaction gas _SF6 and _O2 are 48sccm and 12sccm respectively.

In step e, self-aligned implantation of Al ions is performed multiple times in the N-drift layer 2 by using the etching mask of the gate groove, as shown in FIG. 3e.

The implantation ^energies of ^450keV , ^300keV , ^200keV and ^120keV were ^{adopted successively} , and ^Al Ions are implanted into the implantation region of the N-drift layer 2 in four times to form a P+ gate dielectric protection region 5 with a depth of 0.5 μm and a concentration of 3×10 ¹⁸ cm ⁻³ , and the implantation temperature is 650° C.

In step f, source grooves are formed by etching, as shown in FIG. 3f.

First magnetron sputtering a layer The Ti film is used as an ICP etching mask, and then glued to photolithography, and ICP etching is performed, and the width of the etched groove is 1 μm, and the depth is 3 μm. Finally, the glue is removed, the etching mask is removed, and a light sheet is cleaned. The process conditions are: ICP coil power 850W, source power 100W, reaction gas _SF6 and _O2 are 48sccm and 12sccm respectively.

In step g, self-aligned implantation of Al ions is performed on the N-drift layer 2 for multiple times by using the etching mask of the source trench, as shown in FIG. 3g.

Firstly, the implantation energies of 450keV, 300keV, 200keV and 120keV were adopted successively, and the implant doses were 7.97×10 ¹³ cm ^-2 , 4.69×10 ¹³ cm ^-2 , 3.27×10 ¹³ cm ^-2 and 2.97×10 ¹³ cm ^-2 Al ions are implanted into the implantation region of the N-drift layer 2 in four times to form a P+ source groove corner protection region 6 with a depth of 0.5 μm and a concentration of 3×10 ¹⁸ cm ^-3 , and the implantation temperature is 650°C.

Then use the RCA cleaning standard to clean the SiC surface, make a C film protection after drying, and then perform ion activation annealing in an argon atmosphere at 1700-1750 ° C for 10 minutes.

In step h, trench gate dielectric 7 is prepared, and the material used is SiO ₂ , as shown in FIG. 3h.

The SiO ₂ gate dielectric layer was prepared at 1150°C by dry oxygen process with a thickness of 100nm, and then annealed at 1050°C in NO atmosphere to reduce the roughness of the SiO ₂ film surface.

Step i, preparing a poly Si gate, as shown in Figure 3i.

Poly Si is grown by low-pressure hot-wall chemical vapor deposition to fill the gate groove, the deposition temperature is 600-650°C, the deposition pressure is 60-80Pa, the reaction gas is silane and phosphine, and the carrier gas is helium. Then glue photolithography, etch the polySi layer to form a polysilicon gate, and finally remove the glue and clean.

Step j, preparing a passivation layer, as shown in Figure 3j.

Deposit a layer of field oxygen or Si ₃ N ₄ on the surface of the device, then apply glue for photolithography, etch the passivation layer to open electrode contact holes, and finally remove the glue and clean.

In step k, an electrode is prepared, as shown in FIG. 3k.

First, the front electron beam evaporates Ti/Ni/Au to make the gate and source electrode, then apply glue and photolithography, corrode the metal to form the gate, source electrode, remove the glue, and clean.

Then Ti/Ni/Au is evaporated by electron beam on the back side to make the drain electrode, and finally annealed rapidly in Ar atmosphere for 3min at a temperature of 1050°C. Because the doping concentration of the N-drift layer 2 and the P-epitaxial layer 3 is relatively low, a Schottky contact is formed at the interface between the source electrode 10 and the N-drift layer 2 and the P-epitaxial layer 3 , and ohmic contacts are formed at other interfaces.

Embodiment four

Please refer to FIG. 3. FIG. 3 provides another SiC double-slot UMOSFET device preparation method for this embodiment. The preparation method includes the following steps:

In step a, an N-drift layer 2 is epitaxially grown on an N-type Si substrate 1, as shown in FIG. 3a.

RCA standard cleaning was performed on the N-type SiC substrate with a thickness of 300 μm and a nitrogen ion doping concentration of 1×10 ¹⁹ cm ^-3 , and then epitaxial growth was performed on the entire SiC substrate 1 with a thickness of 15 μm and a nitrogen ion doping concentration of N-drift layer 2 of 6×10 ¹⁵ cm ⁻³ . The process conditions are as follows: temperature is 1600°C, pressure is 100mbar, reaction gas is silane and propane, carrier gas is pure hydrogen, and impurity source is liquid nitrogen.

Step b, epitaxially growing the P- epitaxial layer 3, as shown in FIG. 3b.

A P-epitaxial layer 3 with a thickness of 1.3 μm and an Al ion doping concentration of 1×10 ¹⁷ cm ⁻³ is grown on the N-drift layer 2 . The process conditions are as follows: the temperature is 1600°C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is trimethylaluminum.

Step c, epitaxially growing the N+ source region layer 4, as shown in FIG. 3c.

An N+ source region layer 4 with a thickness of 0.5 μm and a nitrogen ion doping concentration of 5×10 ¹⁸ cm ⁻³ is grown on the P − epitaxial layer 3 .

The process conditions are as follows: temperature is 1600°C, pressure is 100mbar, reaction gas is silane and propane, carrier gas is pure hydrogen, and impurity source is liquid nitrogen.

In step d, gate grooves are formed by etching, as shown in FIG. 3d.

First magnetron sputtering a layer The Ti film is used as an ICP etching mask, and then coated with photolithography, and ICP etching is performed. The width of the etched groove is 1.5 μm, and the depth is 2.5 μm. Finally, the glue is removed, the etching mask is removed, and it is cleaned into a light sheet . The process conditions are: ICP coil power 850W, source power 100W, reaction gas _SF6 and _O2 are 48sccm and 12sccm respectively.

In step e, self-aligned implantation of Al ions is performed multiple times in the N-drift layer 2 by using the etching mask of the gate groove, as shown in FIG. 3e.

The implantation ^energies of ^450keV , ^300keV , ^200keV and ^120keV were ^{adopted successively} , and ^Al Ions are implanted into the implantation region of the N-drift layer 2 in four times to form a P+ gate dielectric protection region 5 with a depth of 0.5 μm and a concentration of 3×10 ¹⁸ cm ⁻³ , and the implantation temperature is 650° C.

In step f, source grooves are formed by etching, as shown in FIG. 3f.

First magnetron sputtering a layer The Ti film is used as an ICP etching mask, and then glued to photolithography, and ICP etching is performed, and the width of the etched groove is 1 μm, and the depth is 3 μm. Finally, the glue is removed, the etching mask is removed, and a light sheet is cleaned. The process conditions are: ICP coil power 850W, source power 100W, reaction gas _SF6 and _O2 are 48sccm and 12sccm respectively.

In step g, self-aligned implantation of Al ions is performed on the N-drift layer 2 for multiple times by using the etching mask of the source trench, as shown in FIG. 3g.

Firstly, the implantation energies of 450keV, 300keV, 200keV and 120keV were adopted successively, and the implant doses were 7.97×10 ¹³ cm ^-2 , 4.69×10 ¹³ cm ^-2 , 3.27×10 ¹³ cm ^-2 and 2.97×10 ¹³ cm ^-2 Al ions are implanted into the implantation region of the N-drift layer 2 in four times to form a P+ source groove corner protection region 6 with a depth of 0.5 μm and a concentration of 3×10 ¹⁸ cm ^-3 , and the implantation temperature is 650°C.

Then use the RCA cleaning standard to clean the SiC surface, make a C film protection after drying, and then perform ion activation annealing in an argon atmosphere at 1700-1750 ° C for 10 minutes.

In step h, trench gate dielectric 7 is prepared, and the material used is SiO ₂ , as shown in FIG. 3h.

The SiO ₂ gate dielectric layer was prepared at 1150°C by dry oxygen process with a thickness of 100nm, and then annealed at 1050°C in NO atmosphere to reduce the roughness of the SiO ₂ film surface.

Step i, preparing a poly Si gate, as shown in Figure 3i.

Poly Si is grown by low-pressure hot-wall chemical vapor deposition to fill the gate groove, the deposition temperature is 600-650°C, the deposition pressure is 60-80Pa, the reaction gas is silane and phosphine, and the carrier gas is helium. Then apply glue for photolithography, etch the polySi layer to form a polysilicon gate, and finally remove the glue and clean.

Step j, preparing a passivation layer, as shown in Figure 3j.

Deposit a layer of field oxygen or Si ₃ N ₄ on the surface of the device, then apply glue for photolithography, etch the passivation layer to open electrode contact holes, and finally remove the glue and clean.

In step k, an electrode is prepared, as shown in FIG. 3k.

First, the front electron beam evaporates Ti/Ni/Au to make the gate and source electrode, then apply glue and photolithography, corrode the metal to form the gate, source electrode, remove the glue, and clean.

Then Ti/Ni/Au is evaporated by electron beam on the back side to make the drain electrode, and finally annealed rapidly in Ar atmosphere for 3min at a temperature of 1050°C. Because the doping concentration of the N-drift layer 2 and the P-epitaxial layer 3 is relatively low, a Schottky contact is formed at the interface between the source electrode 10 and the N-drift layer 2 and the P-epitaxial layer 3 , and ohmic contacts are formed at other interfaces.

In summary, this paper uses specific examples to illustrate the implementation of a SiC double-slot UMOSFET device and its manufacturing method provided by the embodiment of the present invention. The description of the above embodiment is only used to help understand the present invention method and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation and scope of application. In summary, the content of this specification should not be understood as For the limitation of the present invention, the scope of protection of the present invention should be based on the appended claims.

Claims (10)

1. a kind of preparation method of SiC double flutes UMOSFET devices, it is characterised in that including：

Step 1, selection SiC substrate；

Step 2, grow drift layer, epitaxial layer and source region layer in the SiC substrate continuous surface；

Step 3, the source region layer, the epitaxial layer and the drift layer are performed etching to form grid groove；

Step 4, ion implanting is carried out to the grid groove form gate medium protection zone；

Step 5, the source region layer, the epitaxial layer and the drift layer are performed etching and to form source slot；

Step 6, the source slot is carried out ion implanting formed source slot turning protection zone；

Step 7, in the grid groove gate dielectric layer and grid layer are grown to form grid；

Step 8, Passivation Treatment simultaneously prepare electrode to form the SiC double flutes UMOSFET devices.

2. method according to claim 1, it is characterised in that step 2 includes：

Step 21, using epitaxial growth technology, in drift layer described in the SiC substrate superficial growth；

Step 22, using epitaxial growth technology, in epitaxial layer described in the drift layer superficial growth；

Step 23, using epitaxial growth technology, in source region layer described in the epi-layer surface epitaxial growth.

3. method according to claim 1, it is characterised in that step 3 includes：

Using ICP etching technics, using the first mask plate, the source region layer surface is performed etching, in the source region layer, described The grid groove is formed in epitaxial layer and the drift layer.

4. method according to claim 1, it is characterised in that step 4 includes：

Using autoregistration injection technology, using the first mask plate, Al ion implantings are carried out to the grid groove in the drift layer Form the gate medium protection zone.

5. method according to claim 1, it is characterised in that step 5 includes：

Using ICP etching technics, using the second mask plate, the source region layer surface is performed etching, in the source region layer, described The source slot is formed in epitaxial layer and the drift layer.

6. method according to claim 1, it is characterised in that step 6 includes：

Using autoregistration injection technology, using the second mask plate, Al ion implantings are carried out to the source slot in the drift layer Form source slot turning protection zone.

7. method according to claim 6, it is characterised in that Al ion implantings are carried out to the source slot, including：

Using the Implantation Energy of 450keV, 7.97 × 10¹³cm^-2Implantation dosage, the source slot is carried out first time Al ion note Enter；

Using the Implantation Energy of 300keV, 4.69 × 10¹³cm^-2Implantation dosage, second Al ion note is carried out to the source slot Enter；

Using the Implantation Energy of 200keV, 3.27 × 10¹³cm^-2Implantation dosage, the source slot is carried out third time Al ions note Enter；

Using the Implantation Energy of 120keV, 2.97 × 10¹³cm^-2Implantation dosage, the 4th Al ion note is carried out to the source slot Enter.

8. method according to claim 1, it is characterised in that step 7 includes：

Using dry oxygen technique, SiO is grown in the grid groove₂Material is forming the gate dielectric layer；

Using HWLPCVD techniques, polycrystalline Si material is grown in the grid groove to form the grid layer.

9. method according to claim 1, it is characterised in that step 8 includes：

In the substrate top surface growth of passivation layer including the grid；

Using etching technics, the passivation layer to the gate surface performs etching to form electrode contact hole；

Using electron beam evaporation process, metal material formation source electrode and grid are grown in the source slot and the electrode contact hole Electrode；

Using electron beam evaporation process, drain electrode is formed in substrate lower surface growth metal material double to ultimately form the SiC Groove UMOSFET devices.

10. a kind of SiC double flutes UMOSFET devices, it is characterised in that the SiC double flutes UMOSFET devices are by claim 1~9 Method described in any one prepares to be formed.