CN106816176B

CN106816176B - Power supply device and boosting device

Info

Publication number: CN106816176B
Application number: CN201510870091.9A
Authority: CN
Inventors: 陈宗仁
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2015-12-02
Filing date: 2015-12-02
Publication date: 2020-03-03
Anticipated expiration: 2035-12-02
Also published as: CN106816176A

Abstract

The invention provides a power supply device and a booster device. The power supply device for outputting a write voltage to a nor flash ram array comprises: a booster device and a voltage stabilizer. The boosting device is used for generating a boosted voltage and comprises a charge pump, a first voltage division circuit, a first comparator and an oscillator. The charge pump boosts the gradually-rising voltage to a boosted voltage according to the mode signal and the clock signal. The first voltage divider circuit generates a first feedback voltage according to the boosted voltage. The first comparator compares the first feedback voltage with a first reference voltage to generate a first driving signal. The oscillator receives a ramp-up voltage according to the mode signal and outputs a clock signal according to the first driving signal, wherein the ramp-up voltage ramps up from a ground level to a supply voltage. The voltage stabilizing device receives the boosted voltage to generate a write voltage. By implementing the invention, the NOR flash RAM unit for writing program can be protected.

Description

Power supply device and boosting device

Technical Field

The present invention relates to a power supply device and a voltage boosting device, and more particularly, to a power supply device and a voltage boosting device for eliminating overshoot voltage.

Background

In flash RAM, such as NOR flash RAM, a high voltage source is usually required to perform the write operation and the erase operation. Generally, the high voltage source usually utilizes a charge pump to generate high voltage for the flash ram to operate normally. However, when the high voltage output by the charge pump has an overshoot voltage, the overshoot voltage may damage the flash random access memory cell. Therefore, it is necessary to provide a solution for reducing the overshoot voltage of the charge pump.

Disclosure of Invention

The present invention provides a power supply device for outputting a write voltage to a nor flash ram array. The power supply device comprises a boosting device and a voltage stabilizing device. The boosting device is used for generating a boosted voltage and comprises a charge pump, a first voltage division circuit, a first comparator and an oscillator. The charge pump boosts a gradually-rising voltage to the boosted voltage according to a mode signal and a clock signal. The first voltage divider circuit generates a first feedback voltage according to the boosted voltage. The first comparator compares the first feedback voltage with a first reference voltage to generate a first driving signal. The oscillator receives the ramp-up voltage according to the mode signal and outputs the clock signal according to the first driving signal, wherein the ramp-up voltage ramps up from a ground level to a supply voltage. The voltage stabilizer receives the boosted voltage to generate the write voltage.

According to an embodiment of the present invention, the clock signal includes a clock amplitude, and the clock amplitude increases as the ramp voltage rises from the ground level to the supply voltage, so that the boost voltage also increases as the ramp voltage increases, for eliminating an overshoot voltage of the boost voltage.

According to an embodiment of the present invention, the power supply device further includes a selector, a unity gain buffer, a first P-type transistor, a resistive element, a capacitive element, and an N-type transistor. The selector selects one of the ramp-up voltage and the supply voltage to be supplied to the oscillator according to the mode signal. The unity gain buffer comprises an input end and an output end, wherein the output end outputs the gradually-rising voltage. The first P-type transistor has a gate terminal receiving the mode signal, a source terminal receiving the supply voltage, and a drain terminal coupled to a first node. The resistive element is coupled between the first node and the input terminal of the unity gain buffer. The capacitive element is coupled between the input terminal of the unity gain buffer and a ground terminal. The gate terminal of the N-type transistor receives the mode signal, the source terminal is coupled to the ground terminal, and the drain terminal is coupled to the input terminal.

According to an embodiment of the present invention, when the mode signal is at a first logic level, the oscillator receives the ramp-up voltage, the first P-type transistor is turned on, and the N-type transistor is turned off, so that the ramp-up voltage and the voltage at the input terminal are charged from the ground level to the supply voltage.

According to another embodiment of the present invention, when the mode signal is at a second logic level, the oscillator receives the supply voltage, the first P-type transistor is turned off, the N-type transistor is turned on, and the input terminal is coupled to the ground terminal.

According to an embodiment of the present invention, the voltage stabilizer further includes: a P-type pass transistor, a second voltage divider circuit and a second comparator. The gate terminal of the P-type conducting transistor receives a second driving signal, the source terminal receives the boosting voltage, and the drain terminal outputs the writing voltage. The second voltage division circuit generates a second feedback voltage according to the write voltage. The second comparator compares the second feedback voltage with a second reference voltage to generate the second driving signal.

The present invention further provides a boosting apparatus for generating a boosted voltage, the boosting apparatus including a charge pump, a first voltage divider, a first comparator and an oscillator. The charge pump boosts a gradually-rising voltage to the boosted voltage according to a mode signal and a clock signal. The first voltage divider circuit generates a first feedback voltage according to the boosted voltage. The first comparator compares the first feedback voltage with a first reference voltage to generate a driving signal. The oscillator receives the ramp-up voltage according to the mode signal and outputs the clock signal according to the driving signal, wherein the ramp-up voltage ramps up from a ground level to a supply voltage.

According to an embodiment of the present invention, the boost device further includes a selector, a unity gain buffer, a first P-type transistor, a resistive element, a capacitive element, and an N-type transistor. The selector selects one of the ramp-up voltage and the supply voltage to be supplied to the oscillator according to the mode signal. The unity gain buffer comprises an input end and an output end, wherein the output end outputs the gradually-rising voltage. The first P-type transistor has a gate terminal receiving the mode signal, a source terminal receiving the supply voltage, and a drain terminal coupled to a first node. The resistive element is coupled between the first node and the input terminal of the unity gain buffer. The capacitive element is coupled between the input terminal of the unity gain buffer and a ground terminal. The gate terminal of the N-type transistor receives the mode signal, the source terminal is coupled to the ground terminal, and the drain terminal is coupled to the input terminal.

According to an embodiment of the present invention, when the mode signal is at a second logic level, the oscillator receives the supply voltage, the first P-type transistor is turned off, the N-type transistor is turned on, and the input terminal is coupled to the ground terminal.

By implementing the invention, the write voltage can not generate overshoot voltage, thereby protecting the NOR gate flash RAM unit for writing programs.

Drawings

Fig. 1 is a circuit diagram of a power supply device according to an embodiment of the invention;

FIG. 2 is a waveform diagram illustrating a write operation of a NOR gate flash RAM array according to an embodiment of the invention;

fig. 3 is a circuit diagram showing a power supply device according to another embodiment of the invention; and

fig. 4 is a waveform diagram showing a write operation of a nor gate flash ram array according to another embodiment of the invention.

Reference numerals

100. 300 power supply device

110. 310 step-up device

111. 311 first voltage division circuit

1111. 3111A first resistive element

1112. 3112 second resistive element

112. 312 first comparator

113. 313 oscillator

114. 314 charge pump

130. 330 voltage stabilizer

131. 331P type conducting transistor

132. 332 second voltage division circuit

1321. 3321 third resistive element

1322. 3322 fourth resistive element

133. 333 second comparator

201. 401 write operation

202. 402 dropping voltage

203 overshoot voltage

315 selector

316 unity gain buffer

317 a first P type transistor

318 fifth resistive element

319 capacitive element

320N type transistor

NI input terminal

NO output

N1 first node

SM mode signal

VB boost voltage

VCC supply voltage

VD1 first drive signal

VD2 second drive signal

VFB1 first feedback Voltage

VFB2 second feedback Voltage

VPGM write voltage

VREF1 first reference voltage

VREF2 second reference voltage

VSL step-up voltage

SCLK clock signal

Detailed Description

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below:

preferred embodiments according to the present invention will be described below. It should be appreciated that the present invention provides many applicable inventive concepts and that the particular embodiments disclosed herein are illustrative only of the particular forms of the invention which may be made and used in a generic and descriptive sense only and not for purposes of limitation.

Fig. 1 is a circuit diagram of a power supply device according to an embodiment of the invention. As shown in fig. 1, the power supply apparatus 100 includes a voltage boosting apparatus 110 and a voltage stabilizing apparatus 130. The voltage boosting apparatus 110 includes a first voltage dividing circuit 111, a first comparator 112, an oscillator 113, and a charge pump 114, wherein the voltage boosting apparatus 110 is configured to boost a supply voltage VCC to generate a boosted voltage VB, and stabilize a voltage value of the boosted voltage VB using negative feedback theory.

The first voltage divider circuit 111 includes a first resistive element 1111 and a second resistive element 1112, and the first voltage divider circuit 111 divides the boost voltage VB by a first voltage dividing coefficient generated by the first resistive element 1111 and the second resistive element 1112 to generate the first feedback voltage VFB1, wherein the first voltage dividing coefficient is a ratio of an impedance of the second resistive element 1112 to a sum of impedances of the first resistive element 1111 and the second resistive element 1112.

The first comparator 112 compares the first feedback voltage VFB1 with the first reference voltage VREF1 to generate a first driving signal VD1, and the oscillator 113 outputs a clock signal SCLK to drive the charge pump 114 according to the first driving signal VD1, wherein the clock amplitude of the clock signal SCLK is the supply voltage VCC. The charge pump 114 boosts the supply voltage VCC to the boosted voltage VB according to the clock signal SCLK.

The voltage stabilizer 130 includes a P-type pass transistor 131, a second voltage dividing circuit 132 and a second comparator 133, and is configured to step down the boosted voltage VB to the write voltage VPGM and stably output the write voltage VPGM by using a negative feedback theory. The P-type pass transistor 131 provides the boosted voltage VB to the write voltage VPGM according to the second driving signal VD2, and the second voltage divider circuit 132 includes a third resistive element 1321 and a fourth resistive element 1322.

The second voltage divider circuit 132 divides the write voltage VPGM by a second voltage division factor using the second voltage division factor generated by the third resistive element 1321 and the fourth resistive element 1322 to generate the second feedback voltage VFB 2. The second comparator 133 compares the second feedback voltage VFB2 and the second reference voltage VREF2 to generate the second driving signal VD 2. That is, the write voltage VPGM is equal to the product of the second reference voltage VREF2 and the second voltage division factor.

According to an embodiment of the present invention, the write voltage VPGM is provided to the bit lines of a nor gate flash ram array, and thus the write voltage VPGM can be considered as the bit line voltage of the nor gate flash ram array. Fig. 2 is a waveform diagram showing a write operation of a nor gate flash ram array according to an embodiment of the invention. As shown in fig. 2, when a write operation 201 is performed, representing that a nor flash ram array performs a write procedure, a bit line of the nor flash ram array draws current to a write voltage VPGM.

When the bit line of the nor flash ram array draws current to the write voltage VPGM, the voltage value of the write voltage VPGM is caused to generate the droop voltage 202. Since the write voltage VPGM receives the boosted voltage VB via the P-type pass transistor 131, when the write voltage VPGM drops by the voltage 202, the voltage value of the boosted voltage VB is liable to drop.

When the voltage value of the boosted voltage VB decreases, the first feedback voltage VFB1 also decreases, the first comparator 112 senses and sends the first driving signal VD1 to cause the oscillator to send the clock signal SCLK, and the charge pump 114 boosts the supply voltage VCC to the boosted voltage VB according to the clock signal SCLK. However, since the clock signal SCLK generated by the oscillator 113 is not controlled, the charge pump 114 outputs the boosted voltage VB to the original voltage value, and an overshoot voltage must be generated at the boosted voltage VB.

Furthermore, since the response time of the voltage regulator 130 is limited, although the voltage regulator 130 has the function of stabilizing the write voltage VPGM, when the charge pump 114 outputs the boosted voltage VB at full power and an overshoot voltage is generated, the voltage regulator 130 cannot immediately turn off the P-type pass transistor 131, so that the write voltage VPGM will generate the overshoot voltage 203. However, the overshoot 203 of the write voltage VPGM will cause the nor flash ram cell performing the write operation to be damaged, and therefore the overshoot 203 of the write voltage VPGM must be eliminated.

Fig. 3 is a circuit diagram illustrating a power supply device according to another embodiment of the invention. As shown in fig. 3, the power supply apparatus 300 also has a voltage boosting apparatus 310 and a voltage stabilizing apparatus 330. Compared to fig. 1, the boost device 310 further includes a selector 315, a unity gain buffer 316, a first P-type transistor 317, a fifth resistive element 318, a capacitive element 319, and an N-type transistor 320 in addition to the first voltage dividing circuit 311, the first comparator 312, the oscillator 313, and the charge pump 314, and the voltage regulator 330 also includes a P-type pass transistor 331, a second voltage dividing circuit 332, and a second comparator 333, wherein the voltage dividing circuit 332 includes a third resistive element 3321 and a fourth resistive element 3322.

The first voltage divider circuit 311 is the same as the first voltage divider circuit 111 of fig. 1, and includes a first resistive element 3111 and a second resistive element 3112, which is not described again. The boost device 310 also receives a supply of the supply voltage VCC, and the selector 315 selects one of the supply voltage VCC and the ramp-up voltage VSL to be provided to the oscillator 313 according to the mode signal SM. The unity gain buffer 316 includes an input NI and an output NO, wherein the output NO outputs the ramp-up voltage VSL.

The source terminal of the first P-type transistor 317 receives the supply voltage VCC, the drain terminal thereof is coupled to the first node N1, and the gate terminal thereof receives the mode signal SM. The fifth resistive element 318 is coupled between the first node N1 and the input terminal NI, and the capacitive element 319 is coupled between the input terminal NI and the ground terminal. The N-type transistor 320 has a gate terminal receiving the mode signal SM, a source terminal coupled to the ground terminal, and a drain terminal coupled to the input terminal NI.

According to an embodiment of the present invention, when the mode signal SM received by the boosting device 310 is at the low logic level, the bit line voltage is the write voltage VPGM to be supplied to the bit line of the nor flash ram array. Accordingly, the selector 315 selects the ramp-up voltage VSL to be supplied to the oscillator 313 according to the mode signal SM at the low logic level.

Since the mode signal SM is at a low logic level, the first P-type transistor 317 is turned on and the N-type transistor 320 is turned off, and the input NI charges the capacitive element 319 with the supply voltage VCC via the fifth resistive element 318. Since the gain of the unity gain buffer 316 is 1, the ramp-up voltage VSL is equal to the voltage across the capacitive element 319. That is, the ramp-up voltage VSL is gradually increased from the ground level of the ground terminal to the supply voltage VCC.

Fig. 4 is a waveform diagram showing a write operation of a nor gate flash ram array according to another embodiment of the invention. According to an embodiment of the present invention, when the write operation 401 is performed, the mode signal SM changes from the high logic level to the low logic level, so the selector 315 selects the ramp-up voltage VSL to be provided to the oscillator 313 according to the mode signal SM, the first P-type transistor 317 is turned on, the N-type transistor 320 is turned off, and the ramp-up voltage VSL is a voltage waveform generated by the supply voltage VCC to the capacitive element 319 through the fifth resistive element 318.

According to another embodiment of the present invention, the mode signal SM is transitioned from the low logic level to the high logic level when the write operation 401 is performed, and the mode signal SM returns to the low logic level when the write operation 401 is finished, and the selector 315, the first P-type transistor 317 and the N-type transistor 320 must be correspondingly modified accordingly. The write operation 401 is only performed when the mode signal SM is at a low logic level, but is not limited thereto in any way.

Since the ramp-up voltage VSL is used as the supply voltage of the oscillator 313, the clock amplitude of the clock signal SCLK generated by the oscillator 313 is also the ramp-up voltage VSL, i.e. the clock amplitude is also gradually increased to the supply voltage VCC, so that the boosted voltage VB generated by the charge pump 314 is also gradually increased along with the ramp-up voltage VSL. According to another embodiment of the present invention, the clock frequency of the clock signal SCLK generated by the user-controllable oscillator 313 is increased with the ramp-up voltage VSL.

As the ramp-up voltage VSL gradually increases, the boosted voltage VB generated by the charge pump 314 also gradually increases with the ramp-up voltage VSL. Although the bit line of the nor flash ram array starts to draw current to the write voltage VPGM after entering the write operation 401, so that the write voltage VPGM generates the pull-down voltage 402, the clock amplitude of the clock signal SCLK generated by the oscillator 313 gradually increases with the ramp-up voltage VSL, and the boost voltage VB also gradually increases with the ramp-up voltage VSL, so that no overshoot voltage occurs at the write voltage VPGM, thereby protecting the nor flash ram cells performing the write process.

According to an embodiment of the present invention, when the nor flash ram finishes the write operation 401, the mode signal SM returns to the high logic level, the selector 315 selects the supply voltage VCC to be provided to the oscillator 313 according to the mode signal SM, the first P-type transistor 317 is turned off, the N-type semiconductor 320 is turned on, and the input terminal NI is coupled to the ground terminal.

According to an embodiment of the present invention, the boost device 310 can also be used as a charge pump regulator with soft start (soft start). Since the ramp-up voltage VSL is gradually increased from the ground voltage to the supply voltage VCC, the charge pump 314 does not output the boosted voltage VB at all, and the write voltage VPGM is subjected to an overshoot voltage due to the insufficient response speed of the voltage stabilizer 330, thereby protecting the back electrode circuit from being damaged by the excessively high supply voltage.

The foregoing describes features of various embodiments so that others skilled in the art may readily understand the forms of the present description. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced above. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A power supply apparatus for outputting a write voltage to a nor flash ram array, the power supply apparatus comprising:

a boost device for generating a boost voltage, comprising:

a charge pump for boosting a gradually rising voltage to the boosted voltage according to a mode signal and a clock signal;

a first voltage divider circuit for generating a first feedback voltage according to the boosted voltage;

a first comparator for comparing the first feedback voltage with a first reference voltage to generate a first driving signal; and

an oscillator that receives the ramp-up voltage according to the mode signal and outputs the clock signal according to the first driving signal, wherein the ramp-up voltage ramps up from a ground level to a supply voltage; and

and the voltage stabilizing device receives the boosting voltage to generate the writing voltage.

2. The power supply of claim 1 wherein the clock signal comprises a clock amplitude that increases as the ramp voltage ramps from the ground level to the supply voltage such that the boost voltage also increases as the ramp voltage increases to eliminate an overshoot voltage of the boost voltage.

3. The power supply apparatus of claim 1, further comprising:

a selector for selecting one of the ramp-up voltage and the supply voltage to be provided to the oscillator according to the mode signal;

a unity gain buffer comprising an input terminal and an output terminal, wherein the output terminal outputs the ramp-up voltage;

a first P-type transistor having a gate terminal receiving the mode signal, a source terminal receiving the supply voltage, and a drain terminal coupled to a first node;

a resistive element coupled between the first node and the input of the unity gain buffer;

a capacitive element coupled between the input terminal of the unity gain buffer and a ground terminal; and

and the grid end of the N-type transistor is used for receiving the mode signal, the source end of the N-type transistor is coupled to the grounding end, and the drain end of the N-type transistor is coupled to the input end.

4. The power supply of claim 3 wherein the oscillator receives the ramp-up voltage when the mode signal is at a first logic level, the first P-type transistor is turned on, and the N-type transistor is turned off, such that the ramp-up voltage and the voltage at the input terminal are charged from the ground level to the supply voltage.

5. The power supply of claim 3 wherein the oscillator receives the supply voltage when the mode signal is at a second logic level, the first P-type transistor is non-conductive, the N-type transistor is conductive and couples the input terminal to the ground terminal.

6. The power supply apparatus according to claim 1, wherein the voltage regulator means further comprises:

the grid end of the P-type conducting transistor receives a second driving signal, the source end of the P-type conducting transistor receives the boosting voltage, and the drain end of the P-type conducting transistor outputs the writing voltage;

a second voltage divider circuit for generating a second feedback voltage according to the write voltage; and

the second comparator compares the second feedback voltage with a second reference voltage to generate the second driving signal.

7. A voltage boost device for generating a boosted voltage, said voltage boost device comprising:

a first comparator for comparing the first feedback voltage with a first reference voltage to generate a driving signal; and

an oscillator that receives the ramp-up voltage according to the mode signal and outputs the clock signal according to the driving signal, wherein the ramp-up voltage ramps up from a ground level to a supply voltage.

8. The apparatus of claim 7, wherein the clock signal comprises a clock amplitude that increases as the ramp voltage ramps from the ground level to the supply voltage such that the boost voltage also increases as the ramp voltage increases to eliminate an overshoot voltage of the boost voltage.

9. A booster apparatus as set forth in claim 7, further comprising:

10. The apparatus of claim 9, wherein the oscillator receives the ramp-up voltage when the mode signal is at a first logic level, the first P-type transistor is turned on, and the N-type transistor is turned off, such that the ramp-up voltage and the voltage at the input terminal are charged from the ground level to the supply voltage.

11. A boost apparatus according to claim 9, wherein said oscillator receives said supply voltage when said mode signal is at a second logic level, said first P-type transistor is non-conductive, said N-type transistor is conductive and couples said input terminal to said ground terminal.