CN106816176A - Power supply device and increasing apparatus - Google Patents
Power supply device and increasing apparatus Download PDFInfo
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Abstract
The present invention provides a kind of power supply device and increasing apparatus.Above-mentioned power supply device, is used to export write-in voltage to nor gate flash type random access memory array, including：Increasing apparatus and stable-pressure device.Increasing apparatus are used to produce booster voltage, including charge pump, the first bleeder circuit, first comparator and oscillator.Charge pump according to mode signal and clock signal, by the boost in voltage to booster voltage that edges up.First bleeder circuit produces the first feedback voltage according to booster voltage.First comparator compares the first feedback voltage and the first reference voltage, and produces the first drive signal.Oscillator edges up voltage according to mode signal reception, and exports clock signal according to the first drive signal, wherein the voltage that edges up rises to supply voltage from level is grounded.Stable-pressure device receives booster voltage and produces write-in voltage.By implementing the present invention, the nor gate flash type random access memory unit for carrying out write-in program can be protected.
Description
Technical field
The invention relates to a kind of power supply device and increasing apparatus, overshoot is eliminated in particular to one kind
(overshoot) power supply device and increasing apparatus of voltage.
Background technology
In flash type random access memory, such as nor gate flash type random access memory (NOR flash
RAM), it usually needs high voltage source can normally perform write operation and operation of erasing.In general, it is high
Voltage source generally produces high voltage using charge pump, flash type random access memory can just acted normal.However,
When the high voltage that charge pump is exported has overshoot (overshoot) voltage, overshoot voltage may damage flash type
Random access memory unit.Therefore, we are necessary to propose solution for the overshoot voltage for reducing charge pump.
The content of the invention
In view of this, the present invention proposes a kind of power supply device, is used to export a write-in voltage to a nor gate quick flashing
Formula random access memory array.Power supply device includes an increasing apparatus and a stable-pressure device.Above-mentioned liter press-fits
Put to produce a booster voltage, including a charge pump, one first bleeder circuit, a first comparator and a vibration
Device.Above-mentioned charge pump edges up one boost in voltage to above-mentioned booster voltage according to a mode signal and a clock signal.
Above-mentioned first bleeder circuit produces one first feedback voltage according to above-mentioned booster voltage.Above-mentioned first comparator is more above-mentioned
First feedback voltage and one first reference voltage and produce one first drive signal.Above-mentioned oscillator is according to above-mentioned pattern
Signal receives the above-mentioned voltage that edges up, and exports above-mentioned clock signal according to above-mentioned first drive signal, wherein it is above-mentioned gradually
Up voltage rises to a supply voltage from a ground connection level.Above-mentioned stable-pressure device receives above-mentioned booster voltage and produces above-mentioned
Write-in voltage.
An embodiment of the invention, above-mentioned clock signal includes a period of time pulsating width, and above-mentioned clock pulse amplitude is with above-mentioned
The voltage that edges up rises to above-mentioned supply voltage and increases from above-mentioned ground connection level so that above-mentioned booster voltage is also with above-mentioned
The voltage that edges up increases, and is used to eliminate an overshoot voltage of above-mentioned booster voltage.
An embodiment of the invention, power supply device further includes a selector, a unity gain buffer, one
First P-type transistor, a resistance element, a capacitive element and a N-type transistor.Above-mentioned selector root
According to above-mentioned mode signal, above-mentioned one of the voltage and above-mentioned supply voltage of edging up is selected to provide to above-mentioned oscillator.It is above-mentioned
Unity gain buffer includes an input and an output end, wherein above-mentioned output end exports the above-mentioned voltage that edges up.On
State the first P-type transistor gate terminal and receive above-mentioned mode signal, source terminal receives above-mentioned supply voltage, drain electrode end coupling
To a first node.Above-mentioned resistance element is coupled to the above-mentioned of above-mentioned first node and above-mentioned unity gain buffer
Between input.Above-mentioned capacitive element is coupled to the above-mentioned input and an earth terminal of above-mentioned unity gain buffer
Between.Above-mentioned N-type transistor, gate terminal receives above-mentioned mode signal, and source terminal is coupled to above-mentioned earth terminal, leaks
Extremely it is coupled to above-mentioned input.
An embodiment of the invention, when above-mentioned mode signal is first logic level, above-mentioned oscillator is received
The above-mentioned voltage that edges up, above-mentioned first P-type transistor is conducting, and above-mentioned N-type transistor is to be not turned on so that above-mentioned
The voltage of voltage and above-mentioned input of edging up is to charge to above-mentioned supply voltage by above-mentioned ground connection level.
According to another embodiment of the present invention, when above-mentioned mode signal is second logic level, above-mentioned oscillator connects
Receive above-mentioned supply voltage, to be not turned on, above-mentioned N-type transistor is conducting and will be above-mentioned to above-mentioned first P-type transistor
Input is coupled to above-mentioned earth terminal.
An embodiment of the invention, above-mentioned stable-pressure device is further included：One p-type conducting transistor, one second partial pressure
Circuit and one second comparator.The gate terminal of aforementioned p-type conducting transistor receives one second drive signal, source terminal
Above-mentioned booster voltage is received, drain electrode end exports above-mentioned write-in voltage.Above-mentioned second bleeder circuit is according to above-mentioned write-in voltage
Produce one second feedback voltage.Above-mentioned more above-mentioned second feedback voltage of second comparator and one second reference voltage and
Produce above-mentioned second drive signal.
The present invention more proposes that a kind of increasing apparatus are used to produce a booster voltage, and increasing apparatus include a charge pump, one the
One bleeder circuit, a first comparator and an oscillator.Above-mentioned charge pump is believed according to a mode signal and a clock pulse
Number, one is edged up boost in voltage to above-mentioned booster voltage.Above-mentioned first bleeder circuit produces one according to above-mentioned booster voltage
First feedback voltage.Above-mentioned more above-mentioned first feedback voltage of first comparator and one first reference voltage and produce one
Drive signal.Above-mentioned oscillator according to the above-mentioned voltage that edges up of above-mentioned mode signal reception, and according to above-mentioned drive signal
Above-mentioned clock signal is exported, wherein the above-mentioned voltage that edges up rises to a supply voltage from a ground connection level.
An embodiment of the invention, above-mentioned clock signal includes a period of time pulsating width, and above-mentioned clock pulse amplitude is with above-mentioned
The voltage that edges up rises to above-mentioned supply voltage and increases from above-mentioned ground connection level so that above-mentioned booster voltage is also with above-mentioned
The voltage that edges up increases, and is used to eliminate an overshoot voltage of above-mentioned booster voltage.
An embodiment of the invention, increasing apparatus further include a selector, a unity gain buffer, one first
P-type transistor, a resistance element, a capacitive element and a N-type transistor.Above-mentioned selector is according to above-mentioned
Mode signal, selects above-mentioned one of the voltage and above-mentioned supply voltage of edging up to provide to above-mentioned oscillator.Above-mentioned unit increases
Beneficial buffer includes an input and an output end, wherein above-mentioned output end exports the above-mentioned voltage that edges up.Above-mentioned first
P-type transistor gate terminal receives above-mentioned mode signal, and source terminal receives above-mentioned supply voltage, and drain electrode end is coupled to one the
One node.Above-mentioned resistance element is coupled to the above-mentioned input of above-mentioned first node and above-mentioned unity gain buffer
Between.Above-mentioned capacitive element is coupled between the above-mentioned input of above-mentioned unity gain buffer and an earth terminal.
The gate terminal of above-mentioned N-type transistor receives above-mentioned mode signal, and source terminal is coupled to above-mentioned earth terminal, drain electrode end coupling
It is connected to above-mentioned input.
An embodiment of the invention, when above-mentioned mode signal is first logic level, above-mentioned oscillator is received
The above-mentioned voltage that edges up, above-mentioned first P-type transistor is conducting, and above-mentioned N-type transistor is to be not turned on so that above-mentioned
The voltage of voltage and above-mentioned input of edging up is to charge to above-mentioned supply voltage by above-mentioned ground connection level.
An embodiment of the invention, when above-mentioned mode signal is second logic level, above-mentioned oscillator is received
Above-mentioned supply voltage, to be not turned on, above-mentioned N-type transistor is conducting and will be above-mentioned defeated to above-mentioned first P-type transistor
Enter end and be coupled to above-mentioned earth terminal.
By implement the present invention, write-in voltage can be made to be not in overshoot voltage, so protect carry out write-in program or
Not gate flash type random access memory unit.
Brief description of the drawings
Fig. 1 is the circuit diagram for showing the power supply device described in an embodiment of the invention；
Fig. 2 is to show the nor gate flash type random access memory array described in an embodiment of the invention
The oscillogram of write operation；
Fig. 3 is the circuit diagram of the power supply device for showing described according to another embodiment of the present invention；And
Fig. 4 is to show nor gate flash type random access memory array described according to another embodiment of the present invention
Write operation oscillogram.
Drawing reference numeral
100th, 300 power supply device
110th, 310 increasing apparatus
111st, 311 first bleeder circuit
1111st, 3111 first resistor element
1112nd, 3112 second resistance element
112nd, 312 first comparator
113rd, 313 oscillator
114th, 314 charge pump
130th, 330 stable-pressure device
131st, 331 p-types conducting transistor
132nd, 332 second bleeder circuit
1321st, 3321 3rd resistor element
1322nd, 3322 the 4th resistance element
133rd, 333 second comparator
201st, 401 write operation
202nd, 402 drop-out voltage
203 overshoot voltages
315 selectors
316 unity gain buffers
317 first P-type transistors
318 the 5th resistance elements
319 capacitive elements
320 N-type transistors
NI inputs
NO output ends
N1 first nodes
SM mode signals
VB booster voltages
VCC supplies voltage
The drive signals of VD1 first
The drive signals of VD2 second
The feedback voltages of VFB1 first
The feedback voltages of VFB2 second
VPGM writes voltage
The reference voltages of VREF1 first
The reference voltages of VREF2 second
VSL edges up voltage
SCLK clock signals
Specific embodiment
To enable the above objects, features and advantages of the present invention to become apparent, hereafter especially exemplified by a preferred embodiment,
And coordinate institute's accompanying drawings to be described in detail below：
Described below is according to preferred embodiment of the present invention.Must be noted that the invention provides perhaps
More applicable inventive concept, disclosed specific embodiment, is only for explanation and reaches and use of the invention herein
Ad hoc fashion, without may be used to limit to the scope of the present invention.
Fig. 1 is the circuit diagram for showing the power supply device described in an embodiment of the invention.As shown in figure 1,
Power supply device 100 includes increasing apparatus 110 and stable-pressure device 130.Increasing apparatus 110 include the first partial pressure
Circuit 111, first comparator 112, oscillator 113 and charge pump 114, wherein increasing apparatus 110 be used to by
Supply voltage VCC boosts and produces booster voltage VB, and using the voltage of the theoretical stabilization booster voltage VB of negative feedback
Value.
First bleeder circuit 111 includes first resistor element 1111 and second resistance element 1112, first point
Volt circuit 111 is using the first partial pressure system produced by first resistor element 1111 and second resistance element 1112
Number, produces the first feedback voltage VFB1, wherein the first partial pressure system by booster voltage VB except upper first partial pressure coefficient
Impedance and first resistor element 1111 and second resistance element 1112 of the number for second resistance element 1112
Impedance summation ratio.
First comparator 112 compares the first feedback voltage VFB1 and the first reference voltage VREF1 and produces first
Drive signal VD1, oscillator 113 exports clock signal SCLK and drives charge pump according to the first drive signal VD1
114, the wherein clock pulse amplitude of clock signal SCLK is supply voltage VCC.Charge pump 114 is according to clock signal
SCLK, and supply voltage VCC is boosted into booster voltage VB.
Stable-pressure device 130 includes p-type conducting transistor 131, the second bleeder circuit 132 and the second comparator 133,
It is used to for booster voltage VB to be depressurized to write-in voltage VPGM, and using the theoretical stabilization output write-in voltage of negative feedback
VPGM.P-type turns on transistor 131 and is provided to write-in electricity booster voltage VB according to the second drive signal VD2
Pressure VPGM, the second bleeder circuit 132 includes the resistance element 1322 of 3rd resistor element 1321 and the 4th.
Second bleeder circuit 132 is using produced by 3rd resistor element 1321 and the 4th resistance element 1322
Second partial pressure coefficient, the second feedback voltage VFB2 is produced by write-in voltage VPGM except upper second partial pressure coefficient.The
Two comparators 133 compare the second feedback voltage VFB2 and the second reference voltage VREF2 and produce the second driving to believe
Number VD2.It is, write-in voltage VPGM is equal to the second reference voltage VREF2 and the second partial pressure coefficient
Product.
An embodiment of the invention, write-in voltage VPGM is to provide to a nor gate flash type arbitrary access and deposits
The bit line of memory array, therefore write-in voltage VPGM can be considered non-or grid flash type random access memory array
Bit-line voltage.Fig. 2 is to show the non-or grid flash type random access memory battle array described in an embodiment of the invention
The oscillogram of the write operation of row.As shown in Fig. 2 when perform write operation 201 when, represent nor gate flash type with
Machine access memory array performs write-in program, and the bit line of nor gate flash type random access memory array is to write-in electricity
Pressure VPGM extracts electric current.
When the bit line of nor gate flash type random access memory array extracts electric current to write-in voltage VPGM, make
Magnitude of voltage into write-in voltage VPGM produces drop-out voltage 202.Because write-in voltage VPGM is led via p-type
Logical transistor 131 receives booster voltage VB, therefore when voltage VPGM generation drop-out voltages 202 are write, boosting
The magnitude of voltage of voltage VB certainly will also there occurs decline.
When the magnitude of voltage of booster voltage VB declines, the first feedback voltage VFB1 also declines therewith, compares through first
Device 112 senses and sends the first drive signal VD1 and cause oscillator to send clock signal SCLK, charge pump 114
Supply voltage VCC is boosted to by booster voltage VB according to clock signal SCLK.However, due to oscillator 113
The clock signal SCLK that is sent and without control so that charge pump 114 is exported with all strength, by booster voltage
VB returns back to original magnitude of voltage, now certainly will generate overshoot (overshoot) electricity in booster voltage VB
Pressure.
Furthermore, because the reaction time of stable-pressure device 130 has it to limit, although there is stable-pressure device 130 stabilization to write
The function of voltage VPGM, but when charge pump 114 exports booster voltage VB and generates overshoot voltage with all strength,
Stable-pressure device 130 cannot immediately close p-type conducting transistor 131, thus result in write-in voltage VPGM and occurred
Rush the phenomenon of voltage 203.However, the overshoot voltage 203 of write-in voltage VPGM can allow to carry out write operation
Nor gate flash type random access memory unit is damaged, therefore certainly will eliminate the overshoot electricity of write-in voltage VPGM
Pressure 203.
Fig. 3 is the circuit diagram of the power supply device for showing described according to another embodiment of the present invention.As shown in figure 3,
Power supply device 300 equally has increasing apparatus 310 and stable-pressure device 330.Compared to Figure 1, increasing apparatus
310 in addition to including the first bleeder circuit 311, first comparator 312, oscillator 313 and charge pump 314,
Further include selector 315, unity gain buffer 316, the first P-type transistor 317, the 5th resistance element 318,
Capacitive element 319 and N-type transistor 320, stable-pressure device 330 equally include p-type conducting transistor 331,
Second bleeder circuit 332 and the second comparator 333, wherein bleeder circuit 332 include 3rd resistor element 3321
And the 4th resistance element 3322.
First bleeder circuit 311 is identical with first bleeder circuit 111 of Fig. 1, including first resistor element 3111
And second resistance element 3112, will not be repeated here.Increasing apparatus 310 equally receive supply voltage VCC's
Supply, selector 315 will supply voltage VCC and one of the voltage VSL that edges up according to mode signal SM, selection
There is provided to oscillator 313.Unity gain buffer 316 includes input NI and output end NO, wherein output end
NO exports the voltage VSL that edges up.
The source terminal of the first P-type transistor 317 receives supply voltage VCC, and drain electrode end is coupled to first node N1,
Gate terminal reception pattern signal SM.5th resistance element 318 is coupled to first node N1 and input NI
Between, capacitive element 319 is coupled between input NI and earth terminal.The gate terminal of N-type transistor 320
Reception pattern signal SM, source terminal is coupled to earth terminal, and drain electrode end is coupled to input NI.
An embodiment of the invention, when increasing apparatus 310 receive mode signal SM for low logic level,
Represent write-in voltage VPGM need to be provided to the bit line of nor gate flash type random access memory array and be bit line
Voltage.Therefore, selector 315 is according to the mode signal SM for low logic level, and selection will edge up voltage VSL
There is provided to oscillator 313.
Because mode signal SM is low logic level so that the first P-type transistor 317 is turned on and N-type transistor
320 are not turned on, input NI then for supply voltage VCC through the 5th resistance element 318 to capacitive element 319
Charge.Because the gain of unity gain buffer 316 is 1, therefore the voltage VSL that edges up is equal to capacitive element 319
Cross-pressure.It is, the voltage VSL that edges up is to be gradually increased to supply voltage VCC by the ground connection level of earth terminal.
Fig. 4 is to show nor gate flash type random access memory array described according to another embodiment of the present invention
Write operation oscillogram.An embodiment of the invention, when write operation 401 is performed, mode signal
SM is changed into low logic level by logic level high, therefore selector 315 selects the electricity that edges up according to mode signal SM
Pressure VSL is provided to oscillator 313, and the first P-type transistor 317 is conducting, and N-type transistor 320 is to be not turned on,
The voltage VSL that edges up is to supply voltage VCC through the 5th resistance element 318 to the electricity produced by capacitive element 319
Corrugating.
According to another embodiment of the present invention, when write operation 401 is performed, mode signal SM is by low logic position
The paramount logic level of quasi- transformation, when write operation 401 is terminated, mode signal SM returns to low logic level, and selects
Selecting device 315, the first P-type transistor 317 and N-type transistor 320 must relative modification therewith.Herein only with mould
Write operation 401 is performed when formula signal SM is low logic level to illustrate, and this is not defined in any form.
Due to supply voltages of the voltage VSL as oscillator 313, the clock signal produced by oscillator 313 of edging up
The clock pulse amplitude of SCLK is also to edge up voltage VSL, that is, clock pulse amplitude is also gradually increased to supply voltage VCC,
So that booster voltage VB produced by charge pump 314 also gradually increases with voltage VSL is edged up.According to this hair
Bright another embodiment, the clock frequency of the clock signal SCLK produced by the controllable oscillator 313 of user with
Edge up voltage VSL and increase.
With edging up, voltage VSL gradually increases, and the booster voltage VB produced by charge pump 314 is also with the electricity that edges up
Pressure VSL gradually increases.Although the bit line of nor gate flash type random access memory array is entering write operation 401
After when starting to extract electric current to write-in voltage VPGM so that write-in voltage VPGM produces drop-out voltage 402, so
And the clock pulse amplitude of the clock signal SCLK produced by oscillator 313 gradually increases with voltage VSL is edged up,
Booster voltage VB is also as the voltage VSL that edges up gradually increases so that be not in write-in voltage VPGM
Voltage is rushed, and then protects the nor gate flash type random access memory unit for carrying out write-in program.
An embodiment of the invention, when nor gate flash type random access memory terminates write operation 401,
Mode signal SM returns to logic level high, and selector 315 is carried according to mode signal SM selection supplies voltage VCC
Be supplied to oscillator 313, the first P-type transistor 317 to be not turned on, N-type semiconductor 320 turn on and by input
NI is coupled to earth terminal.
An embodiment of the invention, increasing apparatus 310 can act also as the electric charge with soft start (soft start)
Pump voltage-stablizer.Due to edging up, voltage VSL is gradually increased to supply voltage VCC by ground voltage so that charge pump 314
Booster voltage VB will not be with all strength exported, and causes write-in voltage VPGM because the reaction speed of stable-pressure device 330 is inadequate
It is fast and overshoot voltage occurs, so after protecting polar circuit from being damaged because of too high supply voltage.
The feature of many embodiments described above, makes those of ordinary skill in the art clearly understood that this
The form of specification.Those of ordinary skill in the art is it will be appreciated that it is using disclosure of the present invention
Basis completes to be same as the purpose of above-described embodiment and/or reach to be same as to design or change other processing procedures and structure
The advantage of above-described embodiment.Those of ordinary skill in the art is not also it will be appreciated that depart from spirit of the invention
Can without departing from the spirit and scope of the present invention make arbitrary change with the equivalent constructions of scope, substitute and retouching.
Claims (11)
1. a kind of power supply device, is used to export a write-in voltage to a nor gate flash type random access memory
Array, it is characterised in that above-mentioned power supply device includes：
One increasing apparatus, are used to produce a booster voltage, including：
One charge pump, according to a mode signal and a clock signal, one is edged up boost in voltage to above-mentioned booster voltage；
One first bleeder circuit, one first feedback voltage is produced according to above-mentioned booster voltage；
One first comparator, compares above-mentioned first feedback voltage and one first reference voltage and produces one first driving letter
Number；And
One oscillator, it is according to the above-mentioned voltage that edges up of above-mentioned mode signal reception and defeated according to above-mentioned first drive signal
Go out above-mentioned clock signal, wherein the above-mentioned voltage that edges up rises to a supply voltage from a ground connection level；And
One stable-pressure device, receives above-mentioned booster voltage and produces above-mentioned write-in voltage.
2. power supply device as claimed in claim 1, it is characterised in that above-mentioned clock signal includes a clock pulse
Amplitude, above-mentioned clock pulse amplitude increases as the above-mentioned voltage that edges up rises to above-mentioned supply voltage from above-mentioned ground connection level,
So that above-mentioned booster voltage is used to eliminate an overshoot voltage of above-mentioned booster voltage also as the above-mentioned voltage that edges up increases.
3. power supply device as claimed in claim 1, it is characterised in that above-mentioned power supply device is further included：
One selector, according to above-mentioned mode signal, selects above-mentioned one of the voltage and above-mentioned supply voltage of edging up to provide extremely
Above-mentioned oscillator；
One unity gain buffer, including an input and an output end, wherein the output of above-mentioned output end is above-mentioned edging up
Voltage；
One first P-type transistor, gate terminal receives above-mentioned mode signal, and source terminal receives above-mentioned supply voltage, drain electrode
End is coupled to a first node；
One resistance element, be coupled to above-mentioned first node and above-mentioned unity gain buffer above-mentioned input it
Between；
One capacitive element, is coupled between the above-mentioned input of above-mentioned unity gain buffer and an earth terminal；With
And
One N-type transistor, gate terminal receives above-mentioned mode signal, and source terminal is coupled to above-mentioned earth terminal, drain electrode end
It is coupled to above-mentioned input.
4. power supply device as claimed in claim 3, it is characterised in that when above-mentioned mode signal is one first
During logic level, above-mentioned oscillator receives the above-mentioned voltage that edges up, and above-mentioned first P-type transistor is conducting, above-mentioned N
Transistor npn npn is to be not turned on so that the voltage of above-mentioned edge up voltage and above-mentioned input is charged by above-mentioned ground connection level
To above-mentioned supply voltage.
5. power supply device as claimed in claim 3, it is characterised in that when above-mentioned mode signal is one second
During logic level, above-mentioned oscillator receives above-mentioned supply voltage, and above-mentioned first P-type transistor is to be not turned on, above-mentioned N
Above-mentioned input for conducting and is coupled to above-mentioned earth terminal by transistor npn npn.
6. power supply device as claimed in claim 1, it is characterised in that above-mentioned stable-pressure device is further included：
One p-type turns on transistor, and gate terminal receives one second drive signal, and source terminal receives above-mentioned booster voltage, leakage
Extremely export above-mentioned write-in voltage；
One second bleeder circuit, one second feedback voltage is produced according to above-mentioned write-in voltage；And
One second comparator, compares above-mentioned second feedback voltage and one second reference voltage and produces above-mentioned second to drive
Signal.
7. a kind of increasing apparatus, are used to produce a booster voltage, it is characterised in that above-mentioned increasing apparatus include：
One charge pump, according to a mode signal and a clock signal, one is edged up boost in voltage to above-mentioned booster voltage；
One first bleeder circuit, one first feedback voltage is produced according to above-mentioned booster voltage；
One first comparator, compares above-mentioned first feedback voltage and one first reference voltage and produces a drive signal；
And
One oscillator, according to the above-mentioned voltage that edges up of above-mentioned mode signal reception, and exports according to above-mentioned drive signal
Clock signal is stated, wherein the above-mentioned voltage that edges up rises to a supply voltage from a ground connection level.
8. increasing apparatus as claimed in claim 7, it is characterised in that above-mentioned clock signal includes a period of time pulsating width,
Above-mentioned clock pulse amplitude increases as the above-mentioned voltage that edges up rises to above-mentioned supply voltage from above-mentioned ground connection level so that on
Booster voltage is stated also as the above-mentioned voltage that edges up increases, and is used to eliminate an overshoot voltage of above-mentioned booster voltage.
9. increasing apparatus as claimed in claim 7, it is characterised in that above-mentioned increasing apparatus are further included：
One selector, according to above-mentioned mode signal, selects above-mentioned one of the voltage and above-mentioned supply voltage of edging up to provide extremely
Above-mentioned oscillator；
One unity gain buffer, including an input and an output end, wherein the output of above-mentioned output end is above-mentioned edging up
Voltage；
One first P-type transistor, gate terminal receives above-mentioned mode signal, and source terminal receives above-mentioned supply voltage, drain electrode
End is coupled to a first node；
One resistance element, be coupled to above-mentioned first node and above-mentioned unity gain buffer above-mentioned input it
Between；
One capacitive element, is coupled between the above-mentioned input of above-mentioned unity gain buffer and an earth terminal；With
And
One N-type transistor, gate terminal receives above-mentioned mode signal, and source terminal is coupled to above-mentioned earth terminal, drain electrode end
It is coupled to above-mentioned input.
10. increasing apparatus as claimed in claim 9, it is characterised in that when above-mentioned mode signal is one first logic
During level, above-mentioned oscillator receives the above-mentioned voltage that edges up, and above-mentioned first P-type transistor is conducting, and above-mentioned N-type is brilliant
Body pipe is to be not turned on so that the voltage of above-mentioned edge up voltage and above-mentioned input is charged to by above-mentioned ground connection level
State supply voltage.
11. increasing apparatus as claimed in claim 9, it is characterised in that when above-mentioned mode signal is one second logic
During level, above-mentioned oscillator receives above-mentioned supply voltage, and above-mentioned first P-type transistor is to be not turned on, above-mentioned N-type
Above-mentioned input for conducting and is coupled to above-mentioned earth terminal by transistor.
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|---|---|---|---|
| CN201510870091.9A CN106816176B (en) | 2015-12-02 | 2015-12-02 | Power supply device and boosting device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510870091.9A CN106816176B (en) | 2015-12-02 | 2015-12-02 | Power supply device and boosting device |
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| CN106816176A true CN106816176A (en) | 2017-06-09 |
| CN106816176B CN106816176B (en) | 2020-03-03 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111211548A (en) * | 2018-11-21 | 2020-05-29 | 长鑫存储技术有限公司 | Circuit device of charge pump, semiconductor memory and output voltage overshoot protection method |
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| US20020021611A1 (en) * | 1997-02-27 | 2002-02-21 | Kabushiki Kaisha Toshiba | Power supply circuit and semiconductor memory device having the same |
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| CN111211548A (en) * | 2018-11-21 | 2020-05-29 | 长鑫存储技术有限公司 | Circuit device of charge pump, semiconductor memory and output voltage overshoot protection method |
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| CN106816176B (en) | 2020-03-03 |
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