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CN106502011A - 画素结构及工作方法、阵列基板 - Google Patents

画素结构及工作方法、阵列基板 Download PDF

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CN106502011A
CN106502011A CN201611265069.2A CN201611265069A CN106502011A CN 106502011 A CN106502011 A CN 106502011A CN 201611265069 A CN201611265069 A CN 201611265069A CN 106502011 A CN106502011 A CN 106502011A
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potential
common electrode
electrode line
gate
pixel structure
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陈帅
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to CN201611265069.2A priority Critical patent/CN106502011A/zh
Priority to PCT/CN2017/071005 priority patent/WO2018120298A1/zh
Priority to EP17889423.4A priority patent/EP3564740A4/en
Priority to JP2019531635A priority patent/JP2020501197A/ja
Priority to US15/328,620 priority patent/US10186224B2/en
Priority to KR1020197021457A priority patent/KR20190095450A/ko
Publication of CN106502011A publication Critical patent/CN106502011A/zh
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    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract

本发明提供了一种画素结构，所述画素结构包括数据线、栅极、像素电极以及驱动所述栅极的公共电极线；所述公共电极线与像素电极之间的电容为存储电容；所述公共电极线与栅极短接。本发明还提供了一种用于上述画素结构的工作方法及阵列基板。与现有技术相比提高了公共电极线的驱动能力；减少公共电极线ACOM的WOA走线；节省液晶面板的设计空间。

Description

画素结构及工作方法、阵列基板
技术领域
本发明涉及TFT显示装置领域，特别涉及一种用于改善液晶面板共电极稳压性的画素结构及工作方法、阵列基板。
背景技术
串扰是TFT-LCD显示不良中比较常见的一种现象，是指某一区域的画面会影响到其他区域的画面。TFT-LCD根据串扰的位置不同可以分为垂直串扰及水平串扰。以VA显示模式为例，判断串扰的画面，若出现不良现象为水平向则为水平串扰。导致不同类型串扰的原因有所不同，在这里，我们只探讨水平串扰的不良现象，通常情况下，驱动方式的不同将会导致不同宏观表现的水平串扰，例如帧反转可能会出现线状水平串扰，而列反转和点反转的水平串扰现象就会很轻微。但是，无论哪种驱动方式，产生这种画面不良的真因都是一致的，源于数据线路和共电极的电容耦合作用。当数据线路电位发生变化时，便会经由数据线路与公共电极线(ACOM)之间的寄生电容(CDC)在公共电极线形成一个瞬间的电位跳变。若公共电极线(ACOM)的信号延迟较为严重或电压驱动能力不足，则电位无法很快恢复到预设定电位，这个电位跳变会通过储存电容Cst的耦合作用拉低像素跨压，导致像素亮度降低从而形成水平串扰。以VA显示模式、Row Inversion(行反转)的驱动方式为例，其中一条数据线的驱动电压始终为128灰阶电位，另一条的驱动电压有2/3的时间为128灰阶电位、1/3的时间为255灰阶电位，两条数据线的电位周期性反转，导致公共电极线的电位也发生相应的变化，公共电极线电位变化导致的结果是画面整体偏暗，而255灰阶电位的横向区域则会由于公共电极线电位变化更大而出现颜色更暗的水平区块。通常情况下，水平串扰的解决方案是采用列反转(Column Inversion)或者行反转(Dot Inversion)的驱动方式，但是这种解决方案容易受到制程变化带来的影响，使得左右两条数据线对公共电极线的电容耦合作用不同，使得水平串扰不能被完全消除。
在4MASK制程下，数据线和公共电极线之间的电容CDC结构依次有第一金属层(Metal1)，N+层，AS层(烷基硅烷薄膜)，SiNx层(绝缘层)及第二金属层(Metal2)，Metal1和Metal2之间存在着AS层和N+层，导致了在正帧和负帧驱动下CDC的大小存在差异，分别表示为CDC+和CDC-，这样的变化使得左右两条数据线对公共电极线的电容耦合作用存在较大差异。
现有技术中，龙骨结构是横向贯穿在一起的，并通过两边的金属线提供DC驱动电压，这种设计易导致公共电极线ACOM驱动能力不足。因此，提供一种公共电极线ACOM驱动能力强的结构及方法就很有必要。
发明内容
本发明所要解决的技术问题是现有技术中存在的公共电极线ACOM驱动能力不足的技术问题，本发明提供一种将公共电极线ACOM与栅极信号线以一定方式短接在一起，提高公共电极线ACOM的驱动能力的画素结构。
为解决上述技术问题，本发明采用的技术方案如下：
本发明提供了一种画素结构，所述画素结构包括数据线、栅极、像素电极以及驱动所述栅极的公共电极线；所述公共电极线与像素电极之间的电容为存储电容；所述公共电极线与栅极电性连接。
进一步地，所述公共电极线与所述栅极同层设置且连接。
进一步地，公共电极线通过搭接金属线与栅极短接。
进一步地，所述公共电极线电位与栅极电位相等；所述栅极中第n级栅极信号与所述第n+1级存储电容的公共电极线电位相等；其中，n＝1,2,3，…。
本发明还提供了一种阵列基板，包括所述的画素结构，每一所述画素结构内的所述公共电极线和与其对应的一条栅极线电性连接。
进一步地，每一所述画素结构内的所述公共电极线和与其对应的一条栅极线电性连接。
本发明还提供了一种画素结构的工作方法，所述画素结构如权利要求1所述，所述方法包括：
(1)第n级栅极信号电位关闭后，保持在低电位，此时第n+1级存储电容的公共电极线的电位为低电位；
(2)第n+1级栅极信号电位开启后，为高电位，第n+1级存储电容的像素电极正常充电，第n+1级存储电容的公共电极线的电位维持为低电位，第n+2级存储电容的公共电极线的电位为高电位；
(3)第n+1级栅极信号电位关闭后，为低电位，第n+2级存储电容的公共电极线的电位为低电位；
(4)第n+2级栅极线信号电位开启后，为高电位，第n+2级存储电容的像素电极正常充电，第n+2级存储电容的公共电极线的电位维持为低电位；
(5)重复步骤(1)～(4)。
进一步地，所述工作方法中，第n级栅极信号电位开启之前，所述第n级存储电容的公共电极线的电位为低电位。
进一步地，所述第n级栅极信号电位关闭后经过时间t后开启，第n+1级栅极信号电位开启。本发明与现有技术相比公共电极线ACOM与扫描驱动栅极(Gate line)以一定方式短接在一起，提高公共电极线ACOM的驱动能力，在每条扫描驱动栅极Gate开启之前，公共电极线ACOM都可以维持一个稳定的电位Vlow不变。这种利用扫描驱动栅极Gate line驱动公共电极线ACOM的有益效果在于：扫描驱动栅极Gate line的电位由IC独立进行控制，其驱动能力相比一般设计强，且可以减少单独控制公共电极线的WOA走线(非COM信号阵列外布线(Wire on array，WOA))，为液晶面板的其他设计结构提供更为宽泛的空间。
本发明的有益效果：
效果一，提高了公共电极线的驱动能力；
效果二，减少公共电极线ACOM的WOA走线；
效果三，节省液晶面板的设计空间。
附图说明
图1是本发明的结构示意图；
图2是本发明的等效电路图；
图3是本发明公共电极线ACOM与第n级栅极线信号波形示意图；
图4本发明的工作方法流程图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
如图1和图2所示，本发明提供一种改善液晶面板共电极稳压性的画素结构，包括数据线3(DATA)、栅极1(Gate)、像素电极4(Pixel)以及驱动所述栅极的公共电极线2(ACOM)；所述公共电极线2(ACOM)与像素电极4(Pixel)之间的电容为存储电容Cst；所述公共电极线2(ACOM)与栅极1短接，公共电极线2与下方的栅极1为断开设置。
所述栅极1的电位由IC集成电路独立进行控制。所述公共电极线2(ACOM)及栅极1电位相等。
如图2，所述栅极1，第n级栅极信号Gate n与所述第n+1级存储电容Cst n+1的公共电极线2(ACOM)电位相等；其中，n＝1,2,3，…。
所述用于改善液晶面板共电极稳压性的画素结构用于TFT-LCD显示装置，其中，阵列基板包括所述的画素结构，每一所述画素结构内的所述公共电极线2和与其对应的一条栅极1电性连接。
如图2，为本实施例所述结构的等效电路图。基于此，本实施例还提供一种用于改善液晶面板共电极稳压性的画素结构的工作方法，如图4所示，所述方法包括：
(1)第n级栅极信号电位Gate n关闭后，保持在低电位Vlow，此时第n+1级存储电容Cstn+1的公共电极线2(ACOM)的电位为低电位Vlow；
(2)第n+1级栅极信号电位Gate n+1开启后，为高电位Vhigh，第n+1级存储电容Cstn+1的像素电极4(Pixel)正常充电，第n+1级存储电容Cstn+1的公共电极线2(ACOM)的电位维持为低电位Vlow，第n+2级存储电容Cstn+2的公共电极线2(ACOM)的电位为高电位Vhigh；
(3)第n+1级栅极信号电位Gate n+1关闭后，为低电位Vlow，第n+2级存储电容Cstn+2的公共电极线2(ACOM)的电位为低电位Vlow；
(4)第n+2级栅极信号电位Gate n+2开启后，为高电位Vhigh，第n+2级存储电容Cstn+2的像素电极4(Pixel)正常充电，第n+2级存储电容Cst n+2的公共电极线2(ACOM)的电位维持为低电位Vlow；
(5)重复步骤(1)～(4)。
如图3和图4所示，所述方法中，第n级栅极信号电位开启之前，所述第n级存储电容Cstn的公共电极线(ACOM)的电位为低电位Vlow。所述第n级栅极信号电位关闭后经过时间t后开启，第n+1级栅极信号电位Gate n+1开启。
作为本发明的另一种实施方式，公共电极线还可以通过搭接其他层的金属线以过孔连接栅极线。如在绝缘层中设置一层导电层，使公共电极线与栅极连接。
尽管上面对本发明说明性的具体实施方式进行了描述，以便于本技术领域的技术人员能够理解本发明，但是本发明不仅限于具体实施方式的范围，对本技术领域的普通技术人员而言，只要各种变化只要在所附的权利要求限定和确定的本发明精神和范围内，一切利用本发明构思的发明创造均在保护之列。

Claims (9)

1.一种画素结构，其特征在于：所述画素结构包括数据线(3)、栅极(1)、像素电极(4)以及驱动所述栅极的公共电极线(2)；所述公共电极线(2)与像素电极(4)之间的电容为存储电容；所述公共电极线(2)与栅极(1)电性连接。
2.根据权利要求1所述的画素结构，其特征在于：所述公共电极线(2)与所述栅极(1)同层设置且连接。
3.根据权利要求1所述的画素结构，其特征在于：公共电极线(2)通过搭接金属线与栅极(1)短接。
4.根据权利要求1所述的画素结构，其特征在于：所述公共电极线(2)电位与栅极(1)电位相等；所述栅极(1)中第n级栅极信号与所述第n+1级存储电容的公共电极线电位相等；其中，n＝1,2,3，…。
5.一种阵列基板，其特征在于：包括如权利要求1所述的画素结构，每一所述画素结构内的所述公共电极线(2)和与其对应的一条栅极(1)电性连接。
6.根据权利要求5所述的阵列基板，其特征在于：每一所述画素结构内的所述公共电极线(2)和与其对应的一条栅极(1)电性连接。
7.一种画素结构的工作方法，其特征在于，所述画素结构如权利要求1所述，所述方法包括：
(1)第n级栅极信号电位关闭后，保持在低电位，此时第n+1级存储电容的公共电极线(2)的电位为低电位；
(2)第n+1级栅极信号电位开启后，为高电位，第n+1级存储电容的像素电极(4)正常充电，第n+1级存储电容的公共电极线(2)的电位维持为低电位，第n+2级存储电容的公共电极线(2)的电位为高电位；
(3)第n+1级栅极信号电位关闭后，为低电位，第n+2级存储电容的公共电极线(2)的电位为低电位；
(4)第n+2级栅极线信号电位开启后，为高电位，第n+2级存储电容的像素电极(4)正常充电，第n+2级存储电容的公共电极线的电位维持为低电位；
(5)重复步骤(1)～(4)。
8.根据权利要求7所述的画素结构的工作方法，其特征在于：所述工作方法中，第n级栅极信号电位开启之前，所述第n级存储电容的公共电极线(2)的电位为低电位。
9.根据权利要求7所述的画素结构的工作方法，其特征在于：所述第n级栅极信号电位关闭后经过时间t后开启，第n+1级栅极信号电位开启。
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