CN106057108A - Display device - Google Patents

Abstract

The invention discloses a display device, which has a driving circuit, a plurality of driving lines, a plurality of transistor switches and reading lines. Each driving line has a first end and a second end, and the first end of each driving line is connected to the driving circuit. Each transistor switch has a first terminal, a second terminal and a control terminal. The first terminal of each transistor switch is electrically connected to the first voltage terminal, and the control terminal of each transistor switch is electrically connected to the second terminal of a corresponding driving line. The reading line is electrically connected to the second terminal of each transistor switch.

Description

display device

technical field

The present invention relates to a display device, in particular to a display device capable of detecting broken wires.

Background technique

In the display device, the brightness of each pixel is updated by the source driving circuit and the gate driving circuit through the source driving line (data line) and the gate driving line (scanning line), so as to update the picture. However, the gate driving line and the source driving line are often prone to disconnection due to manufacturing processes. In addition, there may be a disconnection problem in the gate driving line or the source driving line at any time during production, transportation and use. Therefore, how to simply and quickly detect whether there is a disconnection problem in the display device after leaving the factory is a problem to be solved.

Contents of the invention

In view of the above problems, the present invention proposes a display device that can simply detect whether the driving lines therein are disconnected after the display device leaves the factory.

A display device according to an embodiment of the present invention has a driving circuit, a plurality of driving lines, a plurality of transistor switches, and a reading line. Each driving line has a first end and a second end, and the first end of each driving line is connected to the driving circuit. Each transistor switch has a first terminal, a second terminal and a control terminal. The first end of each transistor switch is electrically connected to the first voltage end, and the control end of each transistor switch is electrically connected to the second end of a corresponding driving line. The read line is electrically connected to the second end of each transistor switch.

In summary, the present invention adds a transistor switch controlled by the gate drive line or the source drive line, and through the signal provided by the corresponding voltage terminal, the gate drive circuit or the source drive circuit can determine whether There is a problem with any driver wires being disconnected.

The above descriptions about the present disclosure and the following descriptions of the embodiments are used to demonstrate and explain the spirit and principle of the present invention, and to provide further explanations of the patent application scope of the present invention.

Description of drawings

FIG. 1 is a schematic diagram of a circuit structure of a display device according to an embodiment of the invention.

FIG. 2A is a signal timing diagram of a normal display device according to an embodiment of the invention.

FIG. 2B is a signal timing diagram of an abnormal display device according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a circuit structure of a display device according to another embodiment of the present invention.

FIG. 4A is a signal timing diagram of a normal display device according to an embodiment of the present invention.

FIG. 4B is a signal timing diagram of an abnormal display device according to an embodiment of the present invention.

FIG. 4C is a signal timing diagram of a normal display device according to an embodiment of the present invention.

FIG. 4D is a signal timing diagram of an abnormal display device according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a circuit structure of a display device according to another embodiment of the present invention.

FIG. 6A is a signal timing diagram of a normal display device according to an embodiment of the present invention.

FIG. 6B is a signal timing diagram of an abnormal display device according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of a circuit structure of a display device according to another embodiment of the present invention.

FIG. 8 is a schematic diagram of a circuit structure of a display device according to yet another embodiment of the present invention.

Among them, reference signs:

1000 display devices

1100 gate drive circuit

1110 Voltage reset circuit

1200 source drive circuit

S ₁ ~S _N gate drive line

D ₁ ~ D _M source drive line

TS ₁ ~TS _N Transistor switch

TD ₁ ~ TD _M Transistor switch

READ read line

V ₁ , V ₁₁ ~V _1M first voltage terminal

PF picture time interval

P ₁ ～P _N , PB time interval

VREAD, VS ₁ ~ VS _N , VD ₁ , VD ₂ signals

detailed description

The detailed features and advantages of the present invention are described in detail below in the implementation manner, and its content is enough to make any person skilled in the art understand the technical content of the present invention and implement it accordingly, and according to the content disclosed in this specification, the scope of protection of the claims and With the accompanying drawings, any person skilled in the art can easily understand the related objects and advantages of the present invention. The following examples further illustrate the concept of the present invention in detail, but do not limit the scope of the present invention in any way.

The thin film transistor circuit structure used in the display device disclosed in the present invention can be freely designed by those skilled in the art according to the following embodiments of the present invention. The following embodiments of the present invention take an N-type thin-film transistor (N-type thin-film transistor, N-type TFT) as an example. Please refer to FIG. 1 , which is a schematic diagram of a circuit structure of a display device according to an embodiment of the present invention. As shown in FIG. 1 , a display device 1000 according to an embodiment of the present invention has a gate driving circuit 1100, a source driving circuit 1200, a plurality of gate driving lines (scanning lines) _{S 1} -SN , a plurality of source driving circuits lines (data lines) D ₁ ˜D _M , a plurality of transistor switches TS ₁ ˜TS _N and a read line READ. Each gate driving line has a first end and a second end. Taking FIG. 1 as an example, the first end of the gate driving line is the left end (in FIG. The second end of the pole driving line is the right end (in FIG. 1 , the end with the larger X-axis coordinate). The first end of each gate driving line is connected to the gate driving circuit 1100 . Each transistor switch has a first terminal, a second terminal and a control terminal. A first terminal of each transistor switch is electrically connected to the first voltage terminal V ₁ , and a control terminal of each transistor switch is electrically connected to a second terminal of a corresponding gate driving line. The read line READ is electrically connected to the second end of each transistor switch. In this embodiment, although the read line READ is electrically connected to the gate driving circuit 1100 . However, in other embodiments, the readout line READ is either externally connected to a signal output terminal for user or detector to perform measurement, or is electrically connected to the source driving circuit 1200 , which is not limited in the present invention. In addition, although the gate driving circuit 1100 and the source driving circuit 1200 in the present invention are located on the left side and the lower side of the display device 1000 respectively, those skilled in the art should be able to configure the driving circuit and drive the circuit according to the spirit of the present invention. The position and connection relationship between the wire and the corresponding transistor switch are not limited by the present invention.

Therefore, please refer to FIG. 2A , which is a signal timing diagram of a normal display device according to an embodiment of the present invention. As shown in FIG. 2A, the signal VS ₁ to the signal VS _N are sent by the gate drive circuit 1100 to the voltages of the gate drive lines S ₁ to S _N , the signal V ₁ is the voltage of the first voltage terminal V ₁ , and the signal VREAD Then it is the voltage read by the read line READ. In the first time interval P ₁ to the Nth time interval P _N , the gate driving circuit 1100 provides high-level pulses (pulses) to the gate driving line S ₁ to the gate driving line _SN respectively, and at each time interval In the interval, the first voltage terminal V ₁ also provides a high level pulse. The pulse of the gate driving line is a vertical synchronization signal (vertical synchronization signal, V-sync), and the width of the pulse provided by the _first voltage terminal V1, for example, is smaller than the pulse on each gate scanning line ( Vertical sync signal) width. Therefore, in each time interval, the voltage of the signal VREAD should be substantially synchronized with the pulse provided by the _first voltage terminal V1 as shown in FIG. 2A .

In contrast, please refer to FIG. 2B , which is a signal timing diagram of an abnormal display device according to an embodiment of the present invention. The state corresponding to FIG. 2B is that there is a broken line on the gate drive line S2, so in the _second time interval P2, the transistor switch _TS2 will not be turned _on , so that the signal VREAD and the signal of the _first voltage terminal V1 asynchronous, so that the user, the gate drive circuit 1100 or the source drive circuit 1200 can judge whether there is a gate drive line disconnection and which gate drive line is broken by comparing the signal of the _first voltage terminal V1 with the signal VREAD. The line breaks. More specifically, in one embodiment, the first voltage terminal V ₁ is electrically connected to the gate driving circuit 1100 , and the pulse provided by the first voltage terminal V ₁ is substantially generated by the gate driving circuit 1100 . Therefore, the gate driving circuit 1100 can directly determine whether the pulses generated by the gate driving circuit 1100 to the _first voltage terminal V1 and the signal VREAD detected from the read line READ correspond to each other.

In another embodiment of the present invention, please refer to FIG. 3 , which is a schematic diagram of a circuit structure of a display device according to another embodiment of the present invention. Compared with the display device in FIG. 1 , in the embodiment of FIG. 3 , the gate driving circuit 1100 further has a voltage reading circuit 1110 for reading the signal V ₁ input to the reading line. From the _first time interval P1 to the last time interval _PN , the _first voltage terminal V1 maintains a high voltage (for example, the power supply voltage VDD). Please refer to FIG. 4A , which is a signal timing diagram of a normal display device according to an embodiment of the present invention. It can be seen from FIG. 4A that as long as the voltage of any scan line is a high voltage, the signal VREAD will be a high voltage. If the scan line _S2 is disconnected, please refer to FIG. 4B , which is a signal timing diagram of an abnormal display device according to an embodiment of the present invention. Since the scanning line S2 is disconnected, in the _second time interval _P2 , even though the gate driving circuit 1100 sends a high voltage to the scanning line _S2 , the gate voltage of the transistor switch _TD2 does not become a high voltage. , but maintain a low voltage. Therefore, during the _second time interval P2, the transistor switch TD2 is not turned _on , so the signal VREAD maintains a low voltage during the _second time interval P2. Therefore, the user, the gate driving circuit 1100 or the source driving circuit 1200 can judge whether there is a disconnection of the gate driving line and which gate driving line is broken by comparing the signal of the _first voltage terminal V1 with the signal VREAD. .

However, the voltage provided by the _first voltage terminal V1 is not necessarily a DC voltage. Please refer to FIG. 4C , which is a signal timing diagram of a normal display device according to an embodiment of the present invention. Compared with the embodiment of FIG. 4A, the voltage provided by the _first voltage terminal V1 can have an arbitrary waveform substantially, while in the embodiment of FIG. 4C, the voltage provided by the _first voltage terminal V1 is a sawtooth wave. wave). Therefore, whenever the voltage on any scan line is a high voltage, the waveform of the signal VREAD corresponds to the waveform provided by the _first voltage terminal V1. If the scan line _S2 is disconnected, please refer to FIG. 4D , which is a signal timing diagram of an abnormal display device according to an embodiment of the present invention. Since the scanning line S2 is disconnected, in the _second time interval _P2 , even though the gate driving circuit 1100 sends a high voltage to the scanning line _S2 , the gate voltage of the transistor switch _TD2 does not become a high voltage. , but maintain a low voltage. Therefore, during the _second time interval P2, the transistor switch TD2 is not turned _on , so the signal VREAD maintains a low voltage during the _second time interval P2. Therefore, the user, the gate driving circuit 1100 or the source driving circuit 1200 can judge whether there is a disconnection of the gate driving line and which gate driving line is broken by comparing the signal of the _first voltage terminal V1 with the signal VREAD. .

In another embodiment of the present invention, please refer to FIG. 5 , which is a schematic diagram of a circuit structure of a display device according to another embodiment of the present invention. As shown in FIG. 5 , a display device 1000 according to an embodiment of the present invention has a gate driving circuit 1100, a source driving circuit 1200, a plurality of gate driving lines (scanning lines) _{S 1} -SN , a plurality of source driving circuits lines (data lines) D ₁ ˜D _M , a plurality of transistor switches TD ₁ ˜TD _M and a read line READ. Each source driving line has a first end and a second end. Taking FIG. 5 as an example, the first end of the source driving line is the lower end (in FIG. The second end of the pole driving line is the upper end (in FIG. 5 , the end with the larger Y-axis coordinate). The first end of each source driving line is connected to the source driving circuit 1100 . Each transistor switch has a first terminal, a second terminal and a control terminal. A first terminal of each transistor switch is electrically connected to the first voltage terminal V ₁ , and a control terminal of each transistor switch is electrically connected to a second terminal of a corresponding source driving line. The read line READ is electrically connected to the second end of each transistor switch. In this embodiment, although the read line READ is electrically connected to the source driving circuit 1200 . However, in other embodiments, the readout line READ is either externally connected to a signal output terminal for users or testers to perform measurements, or is electrically connected to the gate driving circuit 1100 , which is not limited in the present invention.

Therefore, please refer to FIG. 6A , which is a signal timing diagram of a normal display device according to an embodiment of the present invention. As shown in FIG. 6A, the signal VS ₁ to the signal VS _N are sent to the voltages of the gate driving lines S ₁ to S _N by the gate driving circuit 1100, and the signal VD ₁ and the signal VD ₂ are respectively sent to _The voltage _of the source driving lines D1 and D2, the signal V1 is the voltage _of the _first voltage terminal V1, and the signal VREAD is the voltage read by the read line READ. A picture time interval PF includes the first time interval P ₁ to the Nth time interval _PN (that is, the update time interval) and the blank time interval PB. From the first time interval P ₁ to the Nth time interval _PN , the gate drive The circuit 1100 provides high _- level pulses to the gate driving line S1 to the gate driving line S _N respectively, and in the blank time interval PB, the source driving circuit 1200 supplies the source driving line _D1 to the source Part of the source driving lines of the driving lines D _M sequentially provide high-level pulses.

For example, in the blank time interval PB, the source driving circuit 1200 _first provides pulses to the source driving line _D1 , then provides pulses to the source driving line D2, and at the same time, the _first voltage terminal V1 also provides pulses. In one embodiment, the width of the pulse provided by the first voltage terminal is smaller than the width of the pulse provided by the source driving circuit 1200 to each source driving line, but it is not limited thereto. According to this embodiment, in each time interval, the voltage of the signal VREAD is substantially synchronized with the pulse provided by the first voltage terminal V ₁ as shown in FIG. 6A . The blank time interval PB of each frame time interval PF is, for example, divided into four detection time intervals, and the source drive circuit 1200 respectively performs four dependent detection on the four source drive lines in the four detection time intervals of a blank time interval PB. sequence to provide voltage. The supplied voltage (drive voltage) needs to be able to turn on the transistor switch.

In contrast, please refer to FIG. 6B , which is a signal timing diagram of an abnormal display device according to an embodiment of the present invention. The state corresponding to FIG. 6B is that there is a disconnection _on the source drive line D2, so in a certain blank time interval PB, the signal VREAD is not synchronized with the signal of the _first voltage terminal V1, so that the user, the gate drive The circuit 1100 or the source driving circuit 1200 can determine whether any gate driving line is disconnected and which gate driving line is disconnected by comparing the signal of the _first voltage terminal V1 with the signal VREAD.

Please refer to FIG. 7 , which is a schematic diagram of a circuit structure of a display device according to another embodiment of the present invention. As shown in FIG. 7 , a display device 1000 according to another embodiment of the present invention has a gate driving circuit 1100, a source driving circuit 1200, a plurality of gate driving lines (scanning lines) _{S 1} -SN , a plurality of source Driving lines (data lines) D ₁ ˜D _M , a plurality of transistor switches TD ₁ ˜TD _M and a read line READ. Each source driving line has a first end and a second end. Taking FIG. 7 as an example, the first end of the source driving line is the lower end (the smaller end of the Y-axis coordinate in FIG. 7 ), and the source The second end of the driving line is the upper end (the end with the larger Y-axis coordinate in FIG. 7 ). The first end of each source driving line is connected to the source driving circuit 1200 . Each transistor switch has a first terminal, a second terminal and a control terminal. A first terminal of each transistor switch is electrically connected to the first voltage terminal V ₁ , and a control terminal of each transistor switch is electrically connected to a second terminal of a corresponding source driving line. The read line READ is electrically connected to the second end of each transistor switch. More specifically, in the embodiment of FIG. 7, the first terminal of the transistor switch TD1 is connected to the _first voltage terminal V1, the _first terminal of the transistor switch TD2 is connected to the _second terminal _of the transistor switch TD1, each The transistor switches are connected in series, the first end of the transistor switch TD _M is connected to the second end of the transistor switch TD _M-1 and the second end of the transistor switch TD _M is connected to the read line READ. Therefore, in this embodiment, the first voltage terminal V1 provides _a pulse in the blank time interval PB, and the source driving circuit 1200 provides high voltage to each source driving line D1 to D _M at the same time in the blank time interval PB _. voltage, so that the transistor switches TD ₁ to TD _M can be turned on simultaneously. Therefore, the user, the gate driving circuit 1100 or the source driving circuit 1200 can judge whether there is any source driving circuit by detecting whether the signal VREAD in the blank time interval PB corresponds to the pulse provided by the _first voltage terminal V1. The line has an abnormal problem of disconnection.

In another embodiment, please refer to FIG. 8 , which is a schematic diagram of a circuit structure of a display device according to another embodiment of the present invention. As shown in FIG. 8 , a display device 1000 according to an embodiment of the present invention has a gate driving circuit 1100 , a source driving circuit 1200 , multiple gate driving lines (scanning lines) _{S 1} -SN , multiple source driving circuits lines (data lines) D ₁ ˜D _M , a plurality of transistor switches TD ₁ ˜TD _M and a read line READ. Each source driving line has a first end and a second end. Taking FIG. 8 as an example, the first end of the source driving line is the lower end (the smaller end of the Y axis in terms of FIG. 8 ), and the source The second end of the driving line is the upper end (the end with the larger Y-axis coordinate in FIG. 8 ). The first end of each source driving line is connected to the source driving circuit 1200 . Each transistor switch has a first terminal, a second terminal and a control terminal. The first end of the transistor switch TD ₁ is electrically connected to the first voltage end V ₁₁ , the first end of the transistor switch TD ₂ is electrically connected to the first voltage end V ₁₂ , and the first end of the transistor switch TD _M is electrically connected to the first voltage end V 11 . The first voltage terminal V _1M , and the control terminal of each transistor switch is electrically connected to the second terminal of a corresponding source driving line. The read line READ is electrically connected to the second end of each transistor switch. More specifically, in the embodiment of FIG. 6, the first terminal of the transistor switch TD2 is connected to the _second terminal of the transistor switch TD1, each transistor switch is connected in series, and the _first terminal of the transistor switch _TDM is connected to the transistor The second terminal of the switch TDM _-1 and the second terminal of the transistor switch _TDM are connected to the read line READ. Therefore, in this embodiment, the first voltage terminal V ₁₁ to the first voltage terminal V _1M respectively provide a pulse sequentially in the blank time interval PB, and the source driving circuit 1200 simultaneously controls each source electrode in the blank time interval PB. The driving lines D1 to D _M provide _a high voltage, so that the transistor switches _{TD1 to TD M can} be turned on at the same time. Therefore, the user, the gate driving circuit 1100 or the source driving circuit 1200 can determine whether the signal _VREAD in the blank time interval PB corresponds to the pulse provided by the first voltage terminal V11 to the first voltage terminal _V1M . Is there any abnormal problem that any source driver line is disconnected? Specifically, if the source drive line D2 connected to the control terminal _of the transistor switch _TD2 has a disconnection problem, the pulses provided by the first voltage terminal _V11 and the first voltage terminal _V12 cannot be transmitted to the reader. Line READ, so via the signal VREAD, such a disconnection problem can be checked out.

In summary, the present invention adds a transistor switch controlled by the gate drive line or the source drive line, and through the signal provided by the corresponding voltage terminal, the gate drive circuit or the source drive circuit can determine whether There is a problem with any driver wires being disconnected.

Although the present invention is disclosed above with the foregoing embodiments, they are not intended to limit the present invention. Without departing from the spirit and scope of the present invention, all changes and modifications made belong to the scope of patent protection of the present invention. For the scope of protection defined by the present invention, please refer to the appended claims.

Claims (10)

1. A display device, characterized in that it comprises: a driving circuit; N driving lines, each of which has a first end and a second end, and the first end of each of the driving lines is connected to the driving circuit, and N is an integer greater than 2; N transistor switches, where the i-th transistor switch contains: A first terminal, the first terminal of the ith transistor is electrically connected to a first voltage terminal, i is a positive integer less than or equal to N; a second end; and a control terminal electrically connected to the second terminal of the i-th driving line among the N driving lines; and A readout line is electrically connected to the second end of each transistor switch. 2. The display device according to claim 1, wherein the driving circuit is a source driving circuit, and a frame period of the display device is divided into a refresh time interval and a blank time interval, the source driving The circuit provides at least one driving voltage to at least one of the N driving lines in the blank time interval. 3. The display device according to claim 2, wherein the source driving circuit provides the driving voltage to M driving lines in the N driving lines in the blank time interval, and M is less than N and greater than An integer equal to 1. 4. The display device according to claim 3, wherein the blank time interval is divided into M detection time intervals, and the source driver circuit is provided to the M driving lines in the kth detection time interval The driving voltage of the kth driving line, k is a positive integer less than or equal to M. 5. The display device according to claim 2, wherein the i-th transistor switch is connected to the (i-1)-th transistor switch and the (i+1)-th transistor switch respectively, and the i-th transistor switch is A transistor switch is electrically connected to the read line through the (i+1)th transistor switch, and the i-th transistor switch is electrically connected to the i-th transistor switch through the (i-1)th transistor switch. a voltage terminal. 6. The display device as claimed in claim 5, wherein the source driving circuit provides the driving voltage to each of the driving lines simultaneously in the blank time interval. 7. The display device as claimed in claim 1, wherein the driving circuit is a gate driving circuit for providing a driving voltage to the driving lines. 8. The display device as claimed in claim 1, wherein the readout line is directly connected to the second end of each transistor switch. 9. The display device according to any one of claims 2-7, wherein the first voltage terminal provides a test signal, and the voltage level of the driving voltage is higher than the voltage level of the test signal. 10. The display device according to any one of claims 1-8, wherein the voltage provided by the first voltage terminal is a DC voltage or an AC voltage.