CN105182377B - A kind of receiver board and receiver - Google Patents

Abstract

The embodiment of the invention discloses a receiver board and a receiver. In the embodiment of the present invention, the baseband processing module is used to obtain the first data according to the satellite digital intermediate frequency signal, write the first data in N dual-port RAMs, and send the first instruction to the positioning calculation module; and after receiving the first data In the case of two instructions, read the second data from N dual-port RAMs; N is an integer greater than 1; Read the first data in the dual-port RAM; obtain the second data according to the first data, write the second data into N dual-port RAMs through the EMIF bus, and send the second instruction to the baseband processing module. In the embodiment of the present invention, the capability of data interaction between the baseband processing module and the positioning solution module is effectively improved through the EMIF bus and N dual-port RAMs.

Description

A receiver board and receiver

technical field

The invention relates to the technical field of satellite navigation, in particular to a receiver board and a receiver.

Background technique

At present, the global satellite navigation receiving system mainly includes Chinese BDS (BeiDou Navigation Satellite System, Beidou Satellite Navigation System), American GPS (Global Navigation Satellite System, Global Positioning System), Russian GLONASS (GLONASS) and European Galileo (Galileo), each satellite system has multiple frequency point signals, adding up to more than a dozen frequency points. In order to design a multi-mode multi-frequency receiver that can accommodate more frequency points, the number of satellite tracking channels in the baseband may reach hundreds, and the amount of data interaction between the baseband processing module and the positioning calculation module will reach about 10K each time. The satellite navigation receiver baseband processing module and the positioning solution module communication method mainly contain two modes: the first way: the CPU (Central Processing Unit, processor) in the positioning solution module accesses the register in the baseband processing module through the bus; In the second way, the CPU in the positioning calculation module accesses the data of a single RAM (Random Access Memory, Random Access Memory) in the baseband processing module through a bus.

In the above-mentioned first method, the baseband processing module latches the satellite data into the register set at regular intervals, and then the CPU in the positioning solution module reads and writes the data in the register through the bus. Therefore, the bus data in this method is updated The rate is controlled by the clock of the baseband processing module, and the communication efficiency is very low. Generally, the maximum communication rate can only reach tens of megabits. In addition, all satellite channel registers are connected to the address logic through a data selector, which affects the FPGA synthesis of the baseband processing module. Wiring success rate.

In the above second method, using a single RAM as a data buffer between the bus and the baseband, on the one hand, the fan-in of the RAM will be too large when the baseband processing module is wired internally; on the other hand, the traditional single-port RAM has only one data address port, and the read Writing cannot be performed at the same time, and the communication efficiency is low. In addition, it takes a long time for the baseband processing module to write the data of all satellite channels into a RAM, which reduces the bus utilization efficiency during communication, and when there are enough channels, it may not be able to meet the real-time processing time required for satellite tracking.

To sum up, there is an urgent need for a stable and reliable method for data interaction between the baseband processing module and the positioning calculation module.

Contents of the invention

An embodiment of the present invention provides a receiver board, which is used to improve the data interaction capability between a baseband processing module and a positioning solution module.

A receiver board provided by an embodiment of the present invention includes a radio frequency module, a baseband processing module, and a positioning calculation module, the radio frequency module is connected to the baseband processing module, and the baseband processing module is connected to the positioning calculation module Connected through an external memory interface EMIF bus; the baseband processing module includes N dual-port RAMs; the radio frequency module is used to obtain a satellite digital intermediate frequency signal by processing the received satellite navigation signal, and convert the satellite digital intermediate frequency signal Send to the baseband processing module;

The baseband processing module is used to obtain first data according to the received satellite digital intermediate frequency signal, write the first data into N dual-port RAMs, and send a first instruction to the positioning calculation module; And in the case of receiving the second instruction, read the second data from the N dual-port RAMs; N is an integer greater than 1;

The positioning calculation module is configured to read the first data from the N dual-port RAMs through the EMIF bus when the first instruction is received; according to the first data, obtain The second data, and writing the second data into the N dual-port RAMs through the EMIF bus, and sending a second instruction to the baseband processing module.

Preferably, the dual-port RAM includes a first read-write port and a second read-write port;

The baseband processing module is used to write the first data into the N dual-port RAMs through the first read-write port, and read from the N RAMs through the first read-write port said second data;

The positioning calculation module is used to write the second data into the N dual-port RAMs through the second read-write port, and write data from the N dual-port RAMs through the second read-write port. Read the first data in.

Preferably, the speed at which the baseband processing module reads and writes data through the first read/write port is controlled by a first clock signal;

The speed of reading and writing data by the positioning solution module through the second read-write port is controlled by a second clock signal.

Preferably, the dual-port RAM includes a first storage area and a second storage area;

The baseband processing module also includes a first read-write selection unit; the first read-write selection unit is used to selectively write the first data into the N first storage areas or the N second storage areas. a storage area, and selectively read the second data from N first storage areas or N second storage areas;

The positioning calculation module also includes a second read-write selection unit; the second read-write selection unit is used to selectively write the second data into the N first storage areas or the N first storage areas. Two storage areas, and selectively read the first data from N first storage areas or N second storage areas;

The storage area where the first data is written by the first read-write selection unit is different from the storage area where the second data is written by the second read-write selection unit.

Preferably, the first read-write selection unit includes N internal logic controls corresponding to the N RAMs one-to-one;

The first read/write selection unit is used to selectively write the first data into the N first storage areas or the N second storage areas, and selectively write the first data from the N first storage areas. Reading the second data from the storage area or the N second storage areas includes:

The N internal logic controls to selectively write the first data into the N first storage areas or the N second storage areas through the write logic, and selectively write the first data from the N second storage areas through the read logic. Read the second data from the first storage area or the N second storage areas.

Preferably, the second read-write selection unit includes an EMIF bus controller; the baseband processing module also includes RAM selection logic;

The second read-write selection unit is used to selectively write the second data into the N first storage areas or the N second storage areas, and selectively write the second data from the N first storage areas. Reading the first data from the storage area or the N second storage areas includes:

The EMIF bus controller selectively writes the second data into the N first storage areas or the N second storage areas through the RAM selection logic, and selectively writes the second data from the N The first storage area or the N second storage areas read the first data.

Preferably, the first data includes the cumulative amount of each satellite IQ channel, the chip count value, the code cycle count value, and the carrier cycle count value; the second data includes the shift register tap word, the shift register initial state word , Shift register cut-off state, carrier frequency control word, carrier phase control word, code frequency control word, code phase control word.

Preferably, the baseband processing module is a field programmable gate array module FPGA; the positioning solution module is a digital signal processor DSP.

Preferably, the positioning solution module includes an enhanced direct memory access EDMA controller;

The EDMA controller is used to control the EMIF bus to read the first data from the N dual-port RAMs, and control the EMIF bus to write the second data into the N dual-port RAMs .

A receiver provided by an embodiment of the present invention includes an antenna and the receiver board described in the above embodiments;

The antenna is used to receive satellite navigation signals and send the satellite navigation signals to the receiver board.

The receiver board in the embodiment of the present invention includes a radio frequency module, a baseband processing module and a positioning solution module, the radio frequency module is connected to the baseband processing module, and the baseband processing module is connected to the positioning solution module through the EMIF bus; the baseband processing module includes N Dual-port RAM; the radio frequency module is used to obtain the satellite digital intermediate frequency signal by processing the received satellite navigation signal, and sends the satellite digital intermediate frequency signal to the baseband processing module; the baseband processing module is used to obtain the first satellite digital intermediate frequency signal according to the satellite digital intermediate frequency signal One data, write the first data into N dual-port RAMs, and send the first instruction to the positioning solution module; and read the second data from the N dual-port RAMs when receiving the second instruction ; N is an integer greater than 1; the positioning solution module is used to read the first data from N dual-port RAMs through the EMIF bus when the first instruction is received; according to the first data, the second data is obtained , write the second data into N dual-port RAMs through the EMIF bus, and send the second instruction to the baseband processing module. In the embodiment of the present invention, the baseband processing module and the positioning calculation module adopt a data communication method based on the EMIF bus and N dual-port RAMs, so that the baseband processing module can simultaneously read and write to N dual-port RAMs in a parallel manner, effectively shortening the The time for reading and writing RAM of the baseband processing module is reduced, and the success rate of FPFA integrated wiring of the baseband processing module is improved; moreover, the data interaction between the baseband processing module and the positioning calculation module is effectively improved through the EMIF bus and N dual-port RAMs. ability.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For Those of ordinary skill in the art can also obtain other drawings based on these drawings without any creative effort.

FIG. 1 is a schematic structural diagram of a receiver board provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a receiver board provided by an embodiment of the present invention;

FIG. 3 is a schematic diagram of data interaction provided by an embodiment of the present invention;

4 is a schematic diagram of the connection mode between the EMIF bus and the dual-port RAM in the FPGA provided by the embodiment of the present invention;

Fig. 5 is a schematic structural diagram of a receiver provided by an embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Figure 1 is a schematic structural diagram of a receiver board provided by an embodiment of the present invention, which is suitable for a navigation receiver, and the receiver board includes a radio frequency module 102 connected to an antenna 101, a baseband processing module 103 and a positioning calculation module 104 , the radio frequency module 102 is connected to the baseband processing module 103, and the baseband processing module 103 is connected to the positioning calculation module 104 through an EMIF (External Memory Interface, external memory interface) bus; the baseband processing module 103 includes N dual-port RAM;

The radio frequency module 102 is used to process the received satellite navigation signal to obtain a satellite digital intermediate frequency signal, and send the satellite digital intermediate frequency signal to the baseband processing module 103;

The baseband processing module 103 is used to obtain first data according to the received satellite digital intermediate frequency signal, write the first data into N dual-port RAMs, and send the first data to the positioning calculation module 104. instruction; in the case of receiving the second instruction, read the second data from the N dual-port RAMs; N is an integer greater than 1;

The positioning solution module 104 is configured to read the first data from the N dual-port RAMs through the EMIF bus when the first instruction is received; according to the first data, Obtaining the second data, writing the second data into the N dual-port RAMs through the EMIF bus, and sending a second instruction to the baseband processing module 103 .

In the embodiment of the present invention, the baseband processing module and the positioning calculation module adopt a data communication method based on the EMIF bus and N dual-port RAMs, so that the baseband processing module can simultaneously read and write to N dual-port RAMs in a parallel manner, effectively shortening the The time for the baseband processing module to read and write RAM is reduced, and the success rate of the FPGA integrated wiring of the baseband processing module is improved; moreover, the data interaction between the baseband processing module and the positioning calculation module is effectively improved through the EMIF bus and N dual-port RAMs. ability.

In the embodiment of the present invention, the satellite navigation signal received by the antenna can be a signal of various satellite navigation systems. Preferably, the satellite navigation signal is one or more of the following: Global Positioning System (Global Positioning System, GPS), BeiDou Navigation Satellite System (BDS), Global Satellite Navigation System (GLONASS), Galileo Satellite Navigation (GALILEO).

In the embodiment of the present invention, after the antenna receives the satellite navigation signal, it sends it to the radio frequency module in the receiver board, and the radio frequency module obtains the satellite digital intermediate frequency signal by processing the received satellite navigation signal, and sends the satellite The digital intermediate frequency signal is sent to the baseband processing module, and the baseband processing module obtains first data according to the received satellite digital intermediate frequency signal.

In the embodiment of the present invention, the first data includes the cumulative amount of each satellite IQ channel, the chip count value, the code cycle count value, and the carrier cycle count value; the second data includes the shift register tap word, the shift register initial Status word, shift register cut-off state, carrier frequency control word, carrier phase control word, code frequency control word, code phase control word.

In the embodiment of the present invention, the dual-port RAM includes a first read-write port and a second read-write port, so that the baseband processing module and the positioning calculation module can access N dual-port RAMs through different read-write ports. Specifically, the baseband The processing module writes the first data into the N dual-port RAMs through the first read-write port, and reads the second data from the N RAMs through the first read-write port The positioning calculation module is used to write the second data into the N dual-port RAMs through the second port, and read the N dual-port RAMs through the second port. first data.

Since the baseband processing module and the positioning calculation module can access N dual-port RAMs through different read and write ports, the speed of reading and writing data of the baseband processing module and the positioning calculation module can also be controlled by different clock signals.

Specifically, the speed at which the baseband processing module reads and writes data through the first read-write port is controlled by a first clock signal, and the speed at which the positioning calculation module reads and writes data through the second read-write port is controlled by a second clock signal, In this way, the operation clocks of the baseband processing module and the positioning calculation module for the dual-port RAM are independent of each other, and reading and writing do not interfere with each other. For example, the baseband processing module writes data into the dual-port RAM in parallel with a 50M clock. After writing, the positioning solution module can use a 200M clock to read data from the dual-port RAM. The two do not need to be synchronized, so that the positioning solution The module can access the dual-port RAM at a faster speed, which effectively improves the efficiency of accessing the dual-port RAM of the positioning solution module.

In the embodiment of the present invention, the first instruction may be a handshake signal sent from the baseband processing module to the positioning calculation module, and the second instruction may be a handshake signal sent from the positioning calculation module to the baseband processing module.

In the embodiment of the present invention, the baseband signal processing module may be FPGA (Field Programmable Gate Array, Field Programmable Gate Array module); the positioning solution module may be DSP (Digital Signal Processors, digital signal processor). The receiver board based on DSP and FPGA fully utilizes the programmable baseband processing process in FPGA and the powerful data processing capability of DSP.

FPGA and DSP are connected through EMIF bus to realize two-way communication. Specifically, after the FPGA writes the captured satellite data (first data) into N dual-port RAMs, it sends a handshake signal to the DSP. After receiving the handshake signal, the DSP reads the data from the N dual-port RAMs through the EMIF bus. The satellite data is obtained, and the loop parameter value (second data) is obtained according to the satellite data. The DSP writes the second data into N dual-port RAMs through the EMIF bus, and sends a handshake signal to the FPGA. After the FPGA receives the handshake signal, it takes out the second data from the N dual-port RAMs, so as to adjust the parameter values of each satellite channel according to the second data, so as to ensure close tracking of satellite signals.

In the embodiment of the present invention, the size of N can be set according to the data volume of one update of the baseband satellite channel, and the fan-in and fan-out size of the FPGA wiring should also be considered. For example, the number of baseband satellite tracking channels is M, the total data volume of each channel update is Q, and the data volume of each channel parameter adjustment is S, then the data volume in each RAM can be designed according to (Q+S)/N , N, Q and S determine the bit width and depth of RAM. In the embodiment of the present invention, when N is 1, the fan-in of the RAM wiring in the FPGA is the largest, which is not conducive to timing constraints. Therefore, preferably, N is an integer greater than 1.

Since the FPGA writes Q pieces of data into the dual-port RAM at one time, it sends a handshake signal to the DSP. Therefore, the larger the value of the number of channels M, the higher the value of the total amount of data Q. The longer it takes, the harder it is to meet the demand. In order to further improve the data transmission efficiency between the FPGA and the DSP, the embodiment of the present invention preferably divides the storage area of each dual-port RAM in the FPGA into two parts, namely the first storage area and the second storage area. The baseband processing module also includes a first read/write selection unit, configured to selectively write the first data into the N first storage areas or the N second storage areas, and selectively read from the N The first storage area or the N second storage areas read the second data; the positioning calculation module also includes a second read-write selection unit for selectively writing the second data into N the first storage areas or the N second storage areas, and selectively read the first data from the N first storage areas or the N second storage areas.

In the embodiment of the present invention, the storage area where the first data is written by the first read-write selection unit is different from the storage area where the second data is written by the second read-write selection unit. If the first read-write selection unit writes the first data into N first storage areas, then correspondingly, the second read-write selection unit writes the second data into N second storage areas; if the first read-write The selection unit writes the first data into the N second storage areas, and correspondingly, the second read/write selection unit writes the second data into the N first storage areas.

FIG. 2 is a schematic structural diagram of a receiver board provided by an embodiment of the present invention. As mentioned above, the value of N in the embodiment of the present invention can be set. Here, for the convenience of explaining the specific structure of the receiver board in the embodiment of the present invention, only two dual-port RAMs in the FPGA are shown, that is, dual-port RAM1 and dual-port RAM2. Wherein, the dual-port RAM1 includes a storage area 1a and a storage area 1b, and the dual-port RAM2 includes a storage area 2a and a storage area 2b. The structure of the N dual-port RAMs is similar to the structure of the two dual-port RAMs, and reference may be made to the structures of the two dual-port RAMs, which will not be repeated here.

Specifically, in the embodiment of the present invention, the first read-write selection unit may include N internal logic controls corresponding to N dual-port RAMs one-to-one, and each internal logic control includes a read logic and a write logic, wherein the read The logic is used to read data from one storage area of the dual-port RAM, and the write logic is used to write data into another storage area of the dual-port RAM. The N internal logic controls to selectively write the first data into the N first storage areas or the N second storage areas through the write logic, and selectively write the first data from the N second storage areas through the read logic. Read the second data from the first storage area or the N second storage areas.

The second read-write selection unit can be an EMIF bus controller, wherein, a part of the address lines in the EMIF bus is connected with the address lines in the dual-port RAM, and the other part is connected with the RAM selection logic in the FPGA, and this part of the address lines can be passed through Selecting all the dual-port RAMs sequentially in a combinational logic manner, so as to selectively write the second data into the N first storage areas or the N second storage areas through the RAM selection logic, And selectively read the first data from the N first storage areas or the N second storage areas.

The DSP in the embodiment of the present invention includes a processor, and the processor can control the EMIF bus to read and write data. Preferably, an EDMA (Enhanced Direct Memory Access, Enhanced Direct Memory Access) controller can also be included in the embodiment of the present invention. Since the EDMA controller has the ability to transfer batches of data in the background independent of the processor, therefore, through the EDMA control The controller controls the EMIF bus to read and write data, which can effectively reduce the usage rate of the processor in the DSP, give full play to the high-speed performance of the DSP, and enable the processor to have more resources to complete more channels of satellite positioning solutions. Calculated, reducing the cost of DSP selection.

FIG. 3 is a schematic diagram of data interaction provided by an embodiment of the present invention. Likewise, for the convenience of explaining the data interaction process in the embodiment of the present invention, only two dual-port RAMs in the FPGA are shown. The data exchange process of N dual-port RAMs is similar to the data exchange process of two dual-port RAMs, which can be obtained by referring to two dual-port RAMs, and will not be repeated here.

As shown in Figure 3, the FPGA includes dual-port RAM1 and dual-port RAM2, the first internal logic control is used to control the reading and writing of data in the dual-port RAM1, and the second internal logic control is used to control the data in the dual-port RAM2 read and write; wherein, the first internal logic control can write data into the storage area 1b through the write logic, read data from the storage area 1a through the read logic, and the second internal logic control can write the data through the write logic Write in the storage area 2b, read data from the storage area 2a through the read logic; or, the first internal logic control can also write data into the storage area 1a through the write logic, and read from the storage area 1b through the read logic Data, the second internal logic control can also write data into the storage area 2a through the write logic, and read data from the storage area 2b through the read logic. FIG. 3 only shows one of the situations, which is not specifically limited in this embodiment of the present invention. The FPGA may further include a first signal processing unit, configured to receive the handshake signal sent by the DSP and send the handshake signal to the DSP.

The DSP includes a processor, an EDMA controller, an EMIF bus controller, and may also include a second signal processing unit for receiving the handshake signal sent by the FPGA and sending the handshake signal to the FPGA. On the one hand, the processor is used to start the EDMA controller after the second signal processing unit receives the handshake signal sent by the FPGA, and controls the EMIF bus to read data from the dual-port RAM of the FPGA through the EMIF bus controller; on the other hand, the processing The controller is used to instruct the second signal processing unit to send a handshake signal to the FPGA to notify the FPGA that data is ready after writing data into the dual-port RAM of the FPGA through the EDMA controller, the EMIF bus controller and the EMIF bus.

The data interaction process between FPGA and DSP will be further introduced in conjunction with Fig. 3 below.

The FPGA calculates the satellite data including the coherent integral value and the code cycle count of the in-phase branch and the orthogonal branch of each channel by capturing and tracking the satellite, and writes the data through the first internal logic control and the writing logic in the second internal logic control The satellite data is written into the storage area 1b and the storage area 2b in the two dual-port RAMs; when the data is written, the FPGA sends a handshake signal to the DSP through the first signal processing unit, which is used to notify the DSP from the two dual-port RAMs Read data in the storage area 1b and storage area 2b in. After the processor in the DSP determines that the second signal processing unit receives the handshake signal sent by the first signal processing unit in the FPGA, it starts the EDMA controller, controls the EMIF bus through the EMIF bus controller, and uses combinational logic from the FPGA Data is read from storage area 1b and storage area 2b. The processor in the DSP processes the read data, and sends the calculated data such as carrier offset and chip offset to the EMIF bus through the EDMA controller and the EMIF bus controller, and then through the EMIF bus , written into the storage area 1a and storage area 2a of two dual-port RAMs by means of combinational logic; when the data is written, the second signal processing unit in the DSP sends a handshake signal to the first signal processing unit in the FPGA , which is used to notify the FPGA that the data writing has been completed. After receiving the handshake signal, the first signal processing unit in the FPGA reads data from the storage area 1a and the storage area 2a of the two dual-port RAMs through the read logic in the first internal logic control and the second internal logic control. The FPGA uses the read data in the storage area 1a and the storage area 2a to update the carrier frequency control words and code frequency control words of the M satellite channels, so as to better capture or track satellite signals.

The connection mode between the EMIF bus and the dual-port RAM in the FPGA in the embodiment of the present invention will be specifically introduced below.

The FPGA of Xilinx is selected in the embodiment of the present invention, and the block memory resources integrated in the FPGA can be configured as N dual-port RAMs, and the access speed can reach hundreds of megabytes. The dual-port RAM inside the FPGA has two completely independent read-write ports, which are the first read-write port and the second read-write port. The two read-write ports share the storage space of a RAM, and have independent address lines, data line, read and write control line, therefore, for any RAM, data can be read and written through the first read and write port, and data can also be read and written through the second read and write port. In the embodiment of the present invention, the DSP can access the dual-port RAM from the first read-write port through the EMIF bus, and the FPGA can access the dual-port RAM through the second read-write port, realizing the storage space of the dual-port RAM shared by the DSP and the FPGA.

FIG. 4 is a schematic diagram of a connection mode between an EMIF bus and a dual-port RAM in an FPGA provided by an embodiment of the present invention. Similarly, for the convenience of explaining the connection mode between the EMIF bus and the dual-port RAM in the embodiment of the present invention, only two dual-port RAMs in the FPGA are shown, namely RAM1 and RAM2. The connection method between the EMIF bus and the N dual-port RAMs can be obtained by referring to the EMIF bus and the two dual-port RAMs, and will not be repeated here.

In the embodiment of the present invention, the bit width of the EMIF data bus E_DATA can be configured according to actual conditions, for example, it can be configured as 8 bits, 16 bits, 32 bits, or 64 bits. The dual-port RAM in the embodiment of the present invention includes a first read-write port and a second read-write port, and the corresponding pins of the first read-write port include data input port DIA, data output port DOA, address line ADRRA, read/write Selection signal WEA, enable signal ENA, clock signal CLKA, the pins corresponding to the second read and write port include data input port DIB, data output port DOB, address line ADRRB, read/write selection signal WEB, enable signal ENB, clock Signal CLKB.

The connection relationship between each pin in the EMIF bus controller and the dual-port RAM will be described in detail below in conjunction with FIG. 4 . In the embodiment of the present invention, the pins of the EMIF bus controller include EMIF data bus E_DATA, SOE signal, EMIF address bus E_ADDR, clock output signal E_CLKOUT1, address strobe control signal ADS, read and write control signal WE, chip select signal CE, Byte controls BE.

As shown in Figure 4, the EMIF data bus E_DATA is respectively connected to the data input port DIA and the data output port DOA of the two dual-port RAMs through the data selector, and is controlled by the SOE signal to read data from the dual-port RAM or write data into the dual-port RAM. The EMIF address bus E_ADDR is divided into high order [22:13] address lines and low order [12:0] address lines. Among them, the high order [22:13] address lines are logically connected with the chip selection combination of dual-port RAM, chip selection The combinatorial logic is respectively connected to the ENA of the two dual-port RAMs, and selects which dual-port RAM the EMIF bus interacts with through the combinatorial logic; the low [12:0] address line and the first read-write port of the dual-port RAM The address line ADRRA is connected for accessing all storage spaces in RAM. The clock output signal E_CLKOUT1 in the EMIF bus controller is respectively connected to the clock signal CLKA of the first read and write ports of the two dual-port RAMs, and is used to control the speed of the DSP to read and write the dual-port RAMs. The ADS, WE, CE, and BE signals pass through the combined logic circuit inside the FPGA. On the one hand, they are used to control whether the RAM selection logic is valid. Read and write function of RAM.

The connection relationship between the internal logic control and the dual-port RAM in the FPGA is introduced in detail below in conjunction with Fig. 4 .

In the embodiment of the present invention, the FPGA includes a first internal read-write logic corresponding to the dual-port RAM1 and a second internal read-write logic corresponding to the dual-port RAM2. The first internal read-write logic and the second internal read-write logic are respectively connected to the address line ADRRB of the second read-write port of the dual-port RAM1 and the dual-port RAM2, and are used to access all storage spaces in the RAM. The first internal read-write logic is connected with the data input port DIB and the data output port DOB in the dual-port RAM1 through the first selector, and the second internal read-write logic is connected with the data input port DIB in the dual-port RAM2 through the second selector It is connected with the data output port DOB, so as to control whether the FPGA reads data from the dual-port RAM or writes data into the dual-port RAM through the first selector and the second selector. The first internal read-write logic is respectively connected to WEB and ENB in the dual-port RAM1, and the second internal read-write logic is respectively connected to WEB and ENB in the dual-port RAM2. The first internal read-write logic and the second internal read-write logic are also respectively connected to the clock signal pins CLKB of the dual-port RAM1 and the dual-port RAM2, and are used to control the speed of reading and writing the dual-port RAM by the FPGA.

In the embodiment of the present invention, since the speed at which DSP accesses two dual-port RAMs is controlled by the clock output signal in the EMIF bus controller, and the speed at which FPGA accesses two dual-port RAMs is controlled by its internal clock signal, therefore The operating clocks of DSP and FPGA to dual-port RAM are independent of each other, and reading and writing do not interfere with each other. For example, FPGA uses 50M clock to write data into dual-port RAM in parallel. After writing, DSP can use 200M clock to read data from dual-port RAM. The dual-port RAM effectively improves the efficiency of DSP's access to dual-port RAM.

The receiver board in the embodiment of the present invention includes a radio frequency module, a baseband processing module and a positioning solution module, the radio frequency module is connected to the baseband processing module, and the baseband processing module is connected to the positioning solution module through the EMIF bus; the baseband processing module includes N Dual-port RAM; the radio frequency module is used to obtain the satellite digital intermediate frequency signal by processing the received satellite navigation signal, and sends the satellite digital intermediate frequency signal to the baseband processing module; the baseband processing module is used to obtain the first satellite digital intermediate frequency signal according to the satellite digital intermediate frequency signal One data, write the first data into N dual-port RAMs, and send the first instruction to the positioning solution module; and read the second data from the N dual-port RAMs when receiving the second instruction ; N is an integer greater than 1; the positioning solution module is used to read the first data from N dual-port RAMs through the EMIF bus when the first instruction is received; according to the first data, the second data is obtained , write the second data into N dual-port RAMs through the EMIF bus, and send the second instruction to the baseband processing module. In the embodiment of the present invention, the baseband processing module and the positioning calculation module adopt a data communication method based on the EMIF bus and N dual-port RAMs, so that the baseband processing module can simultaneously read and write to N dual-port RAMs in a parallel manner, effectively shortening the The time for the baseband processing module to read and write RAM is reduced, and the success rate of the FPGA integrated wiring of the baseband processing module is improved; moreover, the data interaction between the baseband processing module and the positioning calculation module is effectively improved through the EMIF bus and N dual-port RAMs. ability.

FIG. 5 is a schematic structural diagram of a receiver provided by an embodiment of the present invention, the receiver includes an antenna 501 and a receiver board 502 as described in the above embodiments;

The antenna 501 is used for receiving satellite navigation signals and sending the satellite navigation signals to the receiver board 502 .

It can be seen from the above that the receiver board in the embodiment of the present invention includes a radio frequency module, a baseband processing module and a positioning calculation module, the radio frequency module is connected to the baseband processing module, and the baseband processing module is connected to the positioning calculation module through the EMIF bus The baseband processing module includes N dual-port RAMs; the radio frequency module is used to obtain the satellite digital intermediate frequency signal by processing the received satellite navigation signal, and sends the satellite digital intermediate frequency signal to the baseband processing module; the baseband processing module is used for Obtain the first data according to the satellite digital intermediate frequency signal, write the first data in N dual-port RAMs, and send the first instruction to the positioning solution module; and in the case of receiving the second instruction, from the N dual-port Read the second data in the RAM; N is an integer greater than 1; the positioning solution module receives and is used to read the first data from N dual-port RAMs through the EMIF bus when the first instruction is received; according to the first instruction First data, obtain second data, write the second data into N dual-port RAMs through the EMIF bus, and send the second instruction to the baseband processing module. In the embodiment of the present invention, the baseband processing module and the positioning calculation module adopt a data communication method based on the EMIF bus and N dual-port RAMs, so that the baseband processing module can simultaneously read and write to N dual-port RAMs in a parallel manner, effectively shortening the The time for the baseband processing module to read and write RAM is reduced, and the success rate of the FPGA integrated wiring of the baseband processing module is improved; moreover, the data interaction between the baseband processing module and the positioning calculation module is effectively improved through the EMIF bus and N dual-port RAMs. ability.

While preferred embodiments of the invention have been described, additional changes and modifications to these embodiments can be made by those skilled in the art once the basic inventive concept is appreciated. Therefore, it is intended that the appended claims be construed to cover the preferred embodiment as well as all changes and modifications which fall within the scope of the invention.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (10)

1. a kind of receiver board, which is characterized in that described including radio-frequency module, baseband processing module and positioning calculation module Radio-frequency module is connect with the baseband processing module, and the baseband processing module passes through external storage with the positioning calculation module Device interface EMIF buses connect；The baseband processing module includes N number of dual port RAM；N is the integer more than 1；

The receiver board includes M base band Satellite Tracking channel；The radio-frequency module is used to lead the satellite received Boat signal is handled, and obtains satellite digital intermediate-freuqncy signal, and the satellite digital intermediate-freuqncy signal is sent at the base band Manage module；

The baseband processing module is used to, according to the satellite digital intermediate-freuqncy signal received, obtain the M base band satellite First data of tracking channel；After first data of the M base band Satellite Tracking channel are written N number of dual port RAM simultaneously, to The positioning calculation module sends the first instruction；And in the case where receiving the second instruction, from N number of dual port RAM Read the second data of the M base band Satellite Tracking channel；

The positioning calculation module is used in the case where receiving first instruction, by the EMIF buses from the N The first data of the M base band Satellite Tracking channel are read in a dual port RAM；According to first data, the M are obtained Second data of base band Satellite Tracking channel and by the EMIF buses by the of the M base band Satellite Tracking channel After N number of dual port RAM is written in two data simultaneously, the second instruction is sent to the baseband processing module.

2. receiver board as described in claim 1, which is characterized in that the dual port RAM includes the first reading-writing port and the Two reading-writing ports；

The baseband processing module is used to first data N number of dual port RAM is written by first reading-writing port In and second data are read from N number of RAM by first reading-writing port；

The positioning calculation module is used to second data N number of dual port RAM is written by second reading-writing port In and first data are read from N number of dual port RAM by second reading-writing port.

3. receiver board as claimed in claim 2, which is characterized in that the baseband processing module is read and write by described first The speed of port read write data is controlled by the first clock signal；

The speed that the positioning calculation module reads and writes data by second reading-writing port is controlled by second clock signal.

4. receiver board as described in claim 1, which is characterized in that the dual port RAM includes the first storage region and the Two storage regions；

The baseband processing module further includes the first read-write selecting unit；The first read-write selecting unit is used for described first Data are selectively written N number of first storage region or N number of second storage region and selectively from N number of institutes It states the first storage region or N number of second storage region reads second data；

The positioning calculation module further includes the second read-write selecting unit；The second read-write selecting unit is used for described second Data are selectively written N number of first storage region or N number of second storage region and selectively from N number of institutes It states the first storage region or N number of second storage region reads first data；

The first read-write selecting unit is written the storage region of the first data and described second and reads and writes described in selecting unit write-in The storage region of second data is different.

5. receiver board as claimed in claim 4, which is characterized in that the first read-write selecting unit includes and the N A RAM N number of internal logic controls correspondingly；

The first read-write selecting unit is used to first data N number of first storage region or N is selectively written It a second storage region and is selectively read from N number of first storage region or N number of second storage region Second data, including：

By writing logic N number of first memory block is selectively written in first data by N number of internal logic control Domain or N number of second storage region and by reading logic selectively from N number of first storage region or N number of described Second storage region reads second data.

6. receiver board as claimed in claim 4, which is characterized in that the second read-write selecting unit includes EMIF buses Controller；The baseband processing module further includes RAM selection logics；

The second read-write selecting unit is used to second data N number of first storage region or N is selectively written It a second storage region and is selectively read from N number of first storage region or N number of second storage region First data, including：

The EMIF bus control units select logic that second data are selectively written N number of described the by the RAM One storage region or N number of second storage region and selectively from N number of first storage region or N number of described Two storage regions read first data.

7. receiver board as described in claim 1, which is characterized in that first data add up including each satellite IQ channels Amount, chip count value, code week count value, carrier cycle count value；Second data include shift register taps word, displacement is posted Storage initial status word, shift register cut-off state, carrier frequency control word, carrier phase control word, code frequency control word, Code phase control word.

8. receiver board as described in claim 1, which is characterized in that the baseband processing module is field-programmable gate array Row module FPGA；The positioning calculation module is digital signal processor DSP.

9. receiver board as described in claim 1, which is characterized in that the positioning calculation module includes enhanced directly interior Access EDMA controllers；

The EDMA controllers for control the EMIF buses read from N number of dual port RAM first data and Control the EMIF buses that second data are written in N number of dual port RAM.

A kind of 10. receiver, which is characterized in that the receiver card including antenna and as described in any in claim 1 to 9 Card；

The satellite navigation signals for receiving satellite navigation signals, and are sent to the receiver board by the antenna.