CN113615088B - Synchronization circuit and method across clock domains - Google Patents

Abstract

The embodiment of the present application discloses a cross-clock domain synchronization circuit. The cross-clock domain synchronization circuit of the present application includes a clock domain channel circuit, a write address generation circuit, a read address generation circuit, and a data cache circuit. The write address generation circuit is used to The write address is obtained from the enable signal, and the write address is used to control the data buffer circuit to receive input data, and the input data is in the write clock domain; the clock domain channel circuit is used to sample the write enable signal to obtain multiple sampling results, and according to the clock phase difference Select a sampling result from multiple sampling results as the read enable signal, and the clock phase difference is the phase difference between the write clock signal in the write clock domain and the read clock signal in the read clock domain; The read address is obtained from the energy signal, and the read address is used to control the data buffer circuit to generate output data, and the output data is in the read clock domain; the data buffer circuit is used to buffer the input data and generate output data according to the write address and the read address.

Description

Synchronization circuit and method across clock domains

technical field

The present application relates to the field of circuits, in particular to a synchronization circuit across clock domains and related methods.

Background technique

System-on-chip (SOC) refers to the integration of a complete system on a single chip. As more and more functions are carried on the chip, there will be more and more clocks inside the chip. Each clock The operating frequencies of different clock domains are different, which leads to multiple clock domains inside the chip. When communicating between multiple clock domains, synchronization of clock domains is required to complete data interaction across clock domains. Asynchronous circuit processing technology can complete this. a process.

A typical asynchronous circuit processing technology is an asynchronous first-in-first-out (fist-in-fist-out, FIFO) technology. Referring to FIG. into the FIFO storage circuit 104, and the read address generation logic circuit 103 in the read clock domain generates a binary read pointer to read the data from the FIFO storage circuit 104. Every time a read or write operation is performed, the corresponding pointer is incremented once to point to the next a memory address. When the full/empty mark generation logic circuit 102 generates the read empty mark, the read operation is no longer performed, but the write operation can be performed; when the full/empty mark generation logic circuit 102 generates the full mark, the write operation is no longer performed, but the to perform a read operation. The generation of the read empty flag needs to synchronize the write pointer of the write clock domain to the read clock domain. First, in order to avoid glitches, the binary write pointer must first be converted into Gray code, and then the Gray code uses two-level registers to perform two-beat processing. Or use multi-level registers to perform multi-beat processing, and then convert the processed write pointer into binary, and compare it with the binary read pointer. When the address bits and status bits of the two pointers are the same, a read empty signal is generated. The above process Among them, since the data stored in the register needs to ensure the setup time and hold time of the data, the setup time refers to the time before the rising edge of the clock signal, the data needs to be input into the register in advance, and the hold time is the time that the data needs to remain unchanged after the rising edge arrives. , it needs to wait for one clock cycle to use the register to perform one-shot processing, then use registers to perform two-beat processing, or use multiple registers to perform two-multiple processing, which will correspondingly generate a delay of two or more clock cycles, and the write pointer is determined by The process of synchronizing the write clock domain to the read clock domain requires a delay of at least two clock cycles. Similarly, the generation of the full mark needs to synchronize the read pointer of the read clock domain to the write clock domain. The synchronization process requires the register to perform two-beat or multi-beat processing, and there is also a delay of at least two clock cycles.

It can be seen that the write pointer in the write clock domain is synchronized to the read clock domain to obtain a read empty signal, which will generate a delay of at least two clock cycles. The same read pointer in the read clock domain is synchronized to the write clock domain to obtain a write full signal. Delay of at least two clock cycles. The full mark will control the increase of the write pointer, and the read empty mark will also control the increase of the read pointer, and the read and write pointer will control the writing and reading of data, thereby controlling the synchronization of the data in the write clock domain to the read clock domain, so The synchronization of data between the two clock domains also has a delay of at least two clock cycles. Due to the above factors, the asynchronous FIFO shown in FIG. 1 has a relatively large delay in cross-clock domain processing, thus reducing the efficiency of data cross-clock domain processing.

Contents of the invention

The first aspect provided by the present application provides a cross-clock domain synchronization circuit, which can synchronize input data from the write clock domain to the read clock domain. The cross-clock domain synchronization circuit includes a clock domain channel circuit, a write address generation circuit, a read The address generation circuit and the data cache circuit; the write address generation circuit can be driven by the write clock signal and obtain the write address according to the write enable signal, and the write address can control the data cache circuit to receive input data, and the input data is the data in the write clock domain; the clock The two input terminals of the domain channel circuit respectively input the write enable signal and the clock phase difference. The clock phase difference refers to the phase difference between the write clock signal in the write clock domain and the read clock signal in the read clock domain. The clock domain The channel circuit can sample the write enable signal to obtain a sample signal set, and the clock domain channel circuit selects the sample signal from the sample signal set as the read enable signal according to the clock phase difference; the read address generation circuit can be driven by the read clock signal, The read address can be obtained according to the read enable signal, and the read address can control the data buffer circuit to generate output data, and the output data is in the read clock domain, then the cross-clock domain synchronization circuit completes the process of synchronizing input data from the write clock domain to the read clock domain . The data buffer circuit receives input data according to the write address and buffers the input data, and then the data buffer circuit generates output data according to the read address.

The embodiment of the present application has the following advantages: the write address generation circuit obtains the write address according to the write enable signal, the write address is used to control the data buffer circuit to receive data, and the data buffer circuit caches the input data after receiving the input data, thereby completing the data writing The process of data cache circuit. The clock domain channel circuit can sample the write enable signal to obtain multiple sampling results. Among the multiple sampling results obtained, some or all of the sampling results are delayed within two clock cycles relative to the write enable signal. Secondly, the write There is a clock phase difference between the write clock signal in the clock domain and the read clock signal in the read clock domain. According to the clock phase difference, a read enable signal is selected from multiple sampling results, and the selected read enable signal is the same as The delay of the write enable signal can be controlled within two clock cycles. Then the read address generation circuit can obtain the read address according to the read enable signal, and the read address is used to control the data cache circuit to generate output data, thereby completing the data read process, then due to the delay control of the read enable signal and the write enable signal Within two clock cycles, the synchronization of data between the two clock domains is also within two clock cycles. Therefore, compared with the existing scheme of delaying at least two clock cycles for data synchronization between the two clock domains, this application The data synchronization delay can be controlled within two clock cycles, which reduces the data synchronization delay and improves the efficiency of data cross-clock domain processing.

In an optional implementation manner of the present application, the clock domain channel circuit specifically includes a plurality of flip-flops, and the plurality of flip-flops can respectively sample the write enable signal on the rising edge and the falling edge of the read clock signal to obtain a sampling signal set , the sampling signal set includes at least one sampling signal, and the clock domain channel circuit further includes a multiplexer, and the multiplexer can select from the preset mapping relationship between the clock phase difference and the write enable signal according to the clock phase difference The target mapping relationship is selected, and then the sampling signal is determined from the sampling signal set according to the target mapping relationship, and the determined sampling signal is used as the read enable signal. In this embodiment, multiple flip-flop groups can be sampled to obtain a set of sampling signals, and the mapping relationship between the clock phase difference and the read enable signal is preset, so the read enable signal determined by the change of the clock phase difference will also change. Therefore, under different clock phase difference conditions, the corresponding sampling signal can be selected from the sampling signal set as the read enable signal, so that the clock delay between the read enable signal and the write enable signal can be controlled within two clock cycles, The simultaneously obtained clock delay of the read enable signal and the write enable signal can also ensure enough time to synchronize the input data from the write clock domain to the read clock domain.

In an optional implementation manner of the present application, the cross-clock domain synchronization circuit further includes a phase detector; the phase detector can determine the clock phase difference between the received write clock signal and the received read clock signal; the phase detector The device can also generate a write enable signal according to the write clock signal, and the write enable signal is only valid when the clock phase difference is in a stable state, otherwise, the write enable signal is invalid. The phase detector outputs the clock phase difference and the write enable signal to the clock domain channel circuit. In this embodiment, the clock phase difference and the write enable signal can be generated through the phase detector, and the solution structure is more complete, which is beneficial to the implementation of the solution.

In an optional implementation manner of the present application, the clock domain channel circuit includes a first flip-flop, a second flip-flop, a third flip-flop, and a fourth flip-flop; the first flip-flop receives the write command generated by the phase detector After enabling the signal, you can sample the write enable signal on the falling edge of the read clock signal to obtain the first sampling signal, and the second flip-flop can sample the first sampling signal on the rising edge of the read clock signal to obtain the second sampling signal; the third trigger After receiving the write enable signal generated by the phase detector, the write enable signal can be sampled on the rising edge of the read clock signal to obtain the third sampling signal; the fourth flip-flop can be used to sample the third sampling signal on the rising edge of the read clock signal The fourth sampling signal is obtained by sampling, and the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal all belong to the sampling signal set. Compared with the prior art using registers to synchronize write pointers or read pointers, the registers need to ensure the setup time and hold time of the data, so at least two clock cycles need to be waited, and in this embodiment, the write enable signal is sampled with a flip-flop The sampling signal set is obtained, and the sampling signal in the sampling signal set can be used as a read enable signal. Since the flip-flop can sample the signal at the rising edge and the falling edge of the clock signal, the read enable signal obtained by the write enable signal can control Within two clock cycles, the synchronization of corresponding data from the write clock domain to the read clock domain can also be controlled within two clock cycles, which reduces the delay of data synchronization compared to the prior art.

In an optional implementation manner of the present application, the clock domain channel circuit further includes a multiplexer, and two input terminals of the multiplexer respectively input the sampling signal set and the clock phase difference, and output the read enable signal. The multiplexer is used to select the second sampling signal from the sampling signal set as the read enable signal when the value range of the clock phase difference is [0T, 1/4T), wherein, due to the write clock The clock cycle can be the same as the read clock domain clock, T is the clock cycle of the write clock domain or the clock cycle of the read clock domain; or, a multiplexer, used when the clock phase difference is [1/4T, 1/2T) In the case of , select the second sampling signal or the fourth sampling signal from the sampling signal set as the read enable signal, where the clock cycle of the second sampling signal and the fourth sampling signal relative to the write enable signal delay is the same, select Either the second sampling signal or the fourth sampling signal can be used; or, the multiplexer is used to select the fourth sampling signal from the sampling signal set when the clock phase difference is [1/2T, 3/4T). As a read enable signal; or, a multiplexer, used to select the second sampling signal or the The third sampling signal is used as the read enable signal, where the second sample signal and the third sample signal are delayed by the same clock period relative to the write enable signal, and either the second sample signal or the third sample signal can be selected. In this embodiment, the specific method of selecting the read enable signal under the four kinds of clock phase differences is introduced, covering all possible clock phase differences, and the flexible implementation of the utilization scheme. The selected read enable signal and write enable signal The clock delay of the enable signal can be controlled within two clock cycles, and the selected clock delay of the read enable signal and the write enable signal can also ensure enough time to synchronize the input data from the write clock domain to the read clock domain.

In an optional implementation manner of the present application, the cross-clock domain synchronization circuit further includes a write clock domain PLL and a read clock domain PLL, and the write clock domain PLL and the read clock domain PLL are connected to the same On the clock source; the write clock domain PLL can obtain the write clock signal according to the clock source signal, and the write clock signal is in the write clock domain; the read clock domain PLL can obtain the read clock signal according to the clock source signal, and the read clock signal in the read clock domain. In this embodiment, the PLL in the write clock domain and the PLL in the read clock domain are connected to the same clock source to ensure that the clock in the write clock domain and the clock in the read clock domain are homologous clocks, and that the two clocks are not Frequency deviation, then the frequency of the obtained write clock signal and the read clock signal are equal or the frequency division ratio of the obtained write clock signal and the read clock signal is an integer multiple, and the phase difference between the two clock signals is random.

In an optional implementation manner of the present application, the data buffer circuit includes a plurality of flip-flop groups, an input multiplexer, and an output multiplexer; the input data selector includes multiple A plurality of output ports connected in one-to-one correspondence between the input terminals, the output multiplexer includes a plurality of input ports connected in one-to-one correspondence with a plurality of output terminals of a plurality of flip-flop groups; the input multiplexer is used to obtain After the data is input, according to the write address, output the cached data from a certain output port, and continuously change the write address, you can get multiple cached data from multiple output ports of the input multiplexer; multiple flip-flop groups are used in Driven by the write clock signal, the multi-channel buffer data is received, and the multi-channel buffer data output from the output ports of the multiple input multiplexers are respectively buffered in different flip-flop groups; the output multiplexer receives The multi-way cache data output by multiple flip-flop groups, and according to the read address, select one line of cache data from the multi-way cache data as the output data output, and the output data obtained by selection is different for different read addresses. In this embodiment, since the read enable signal changes with the clock phase difference, and the read enable signal can obtain the read address, then under different clock phase difference conditions, the read address is also different, and the read address is used as the read address carrying address information. address, it can be seen that the read address has multiple possible situations, so the application obtains multi-way cache data by inputting the multi-way data selector on data synchronization, and the multi-way cache data is cached in different trigger groups of multiple trigger groups, When the read address changes, the cached data corresponding to the flip-flop group in the plurality of flip-flop groups can be selected as the output data. It can be seen that the clock phase difference changes, the read address changes, and the selected output data also changes, so the solution of this application can meet the data synchronization requirements under different clock phase difference conditions.

In an optional implementation manner of the present application, the cross-clock domain synchronization circuit further includes a fifth D flip-flop; the fifth D flip-flop is used to receive the output selected by the output multiplexer under the drive of the read clock signal data, caches and outputs that output data. In this embodiment, the fifth D flip-flop is used to buffer and output the output data selected by the output multiplexer, and the fifth D flip-flop can prevent external interference from affecting the correctness of data transmission during data transmission.

The second aspect of the present application provides a cross-clock domain synchronization method, which includes: obtaining a write address according to the write enable signal, the write address carries address information, and can receive input data according to the control of the write address, and cache the input data , so as to complete the data writing process. The input data here is in the write clock domain. At the same time, the write enable signal can be sampled to obtain multiple sampling results, and one sampling result is selected from the multiple sampling results according to the clock phase difference as The read enable signal, wherein the clock phase difference is the phase difference between the write clock signal in the write clock domain and the read clock signal in the read clock domain; the read address is obtained according to the read enable signal, and the buffered input is controlled according to the read address Data output, thereby generating output data to complete the data reading process, and the output data is in the read clock domain.

This embodiment has the following advantages: the write address is obtained according to the write enable signal, and the input data can be received and buffered according to the control of the write address, thereby completing the data writing process. Multiple sampling results are obtained by sampling the write enable signal. Among the multiple sampling results obtained, the delay of some or all of the sampling results relative to the write enable signal is within two clock cycles. Secondly, the write clock in the write clock domain There is a clock phase difference between the signal and the read clock signal in the read clock domain. According to the clock phase difference, a read enable signal is selected from multiple sampling results, and the selected read enable signal and write enable signal are The delay can be controlled within two clock cycles. Then obtain the read address according to the read enable signal, output the buffered input data to generate output data according to the control of the read address, and complete the data reading process, then the delay between the read enable signal and the write enable signal is controlled within two clock cycle, the synchronization of data between the two clock domains is also within two clock cycles, so compared with the existing scheme of delaying at least two clock cycles for data synchronization between the two clock domains, this application can transfer the data The synchronization delay is controlled within two clock cycles, which reduces the data synchronization delay and improves the efficiency of data cross-clock domain processing.

In an optional implementation manner of the present application, the sampling the write enable signal to obtain multiple sampling results includes: sampling the write enable signal at the rising edge of the read clock signal, and simultaneously sampling the write enable signal at the rising edge of the read clock signal The falling edge samples the write enable signal, and multiple sampling results can be obtained. In this embodiment, compared with the prior art using registers to synchronize write pointers or read pointers, the registers need to ensure the setup time and hold time of the data, so it is necessary to wait for at least two clock cycles, and in this embodiment, the read clock signal Both the rising and falling edges of the clock can sample the signal, and the sampled signal can be controlled within two clock cycles, and the corresponding data can be synchronized from the write clock domain to the read clock domain within two clock cycles. There are technologies that reduce the delay of data synchronization.

In an optional implementation manner of the present application, sampling the write enable signal at the rising edge and the falling edge of the read clock signal respectively, so as to obtain multiple sampling results specifically includes: sampling the write enable signal at the falling edge of the read clock signal Sampling can obtain the first sampling signal; sampling the first sampling signal at the rising edge of the read clock signal can obtain the second sampling signal; sampling the write enable signal at the rising edge of the read clock signal can obtain the third sampling signal signal; the third sampling signal is sampled at the rising edge of the read clock signal to obtain the fourth sampling signal, and the multiple sampling results are specifically the obtained first sampling signal, second sampling signal, third sampling signal and fourth sampling signal . In this embodiment, compared with the prior art using registers to synchronize write pointers or read pointers, the registers need to ensure the setup time and hold time of the data, so it is necessary to wait for at least two clock cycles, and in this embodiment, the read clock signal Both the rising and falling edges of the clock can sample the signal, and the sampled signal can be controlled within two clock cycles, and the corresponding data can be synchronized from the write clock domain to the read clock domain within two clock cycles. There are technologies that reduce the delay of data synchronization.

In an optional implementation manner of the present application, selecting a sampling result from a plurality of sampling results according to the clock phase difference as the read enable signal includes: In this case, the second sampling signal is selected from multiple sampling results as the read enable signal, wherein, since the clock signal of the write clock domain and the clock signal of the read clock domain are generated by the same clock source, the clock cycle of the write clock domain or the read The clock periods of the clock domains are the same, and T can be the clock period of the write clock domain or the clock period of the read clock domain; or, when the value range of the clock phase difference is [1/4T, 1/2T), from multiple Select the second sampling signal or the fourth sampling signal as the read enable signal from one sampling result; or, when the value range of the clock phase difference is in [1/2T, 3/4T), from multiple sampling results Select the fourth sampling signal as the read enable signal; or, when the value of the clock phase difference is greater than or equal to 3/4 clock cycle T, select the second sampling signal or the third sampling signal from multiple sampling results as a read enable signal. In this embodiment, the specific method of selecting the read enable signal under the four kinds of clock phase differences is introduced, covering all possible clock phase differences, and the flexible implementation of the utilization scheme. The selected read enable signal and write enable signal The clock delay of the enable signal can be controlled within two clock cycles, and the selected clock delay of the read enable signal and the write enable signal can also ensure enough time to synchronize the input data from the write clock domain to the read clock domain.

In an optional implementation manner of the present application, the method further includes: determining the clock phase difference between the write clock signal and the read clock signal in the read clock domain according to the write clock signal; generating a write clock signal according to the write clock signal. Enable signal, wherein, when the clock phase difference between the write clock signal and the read clock signal is in a stable state, the write enable signal is valid, and when the clock phase difference between the write clock signal and the read clock signal is not in a stable state , the write enable signal is invalid. In this embodiment, the acquisition method of the clock phase difference and the write enable signal can be introduced. The write enable signal can be used in the data synchronization process of this application. The write enable signal is valid only when the clock phase difference is stable, which can avoid Data synchronization error occurs when the clock phase difference is unstable.

The third aspect of the present application provides a chip, which includes the cross-clock domain synchronization circuit described in the first aspect of the present application and any implementation manner thereof.

The embodiment of the present application has the following advantages: the write address generation circuit obtains the write address according to the write enable signal, the write address is used to control the data buffer circuit to receive data, and the data buffer circuit caches the input data after receiving the input data, thereby completing the data writing The process of data cache circuit. The clock domain channel circuit can sample the write enable signal to obtain multiple sampling results. Among the multiple sampling results obtained, some or all of the sampling results are delayed within two clock cycles relative to the write enable signal. Secondly, the write There is a clock phase difference between the write clock signal in the clock domain and the read clock signal in the read clock domain. According to the clock phase difference, a read enable signal is selected from multiple sampling results, and the selected read enable signal is the same as The delay of the write enable signal can be controlled within two clock cycles. Then the read address generation circuit can obtain the read address according to the read enable signal, and the read address is used to control the data cache circuit to generate output data, thereby completing the data read process, then due to the delay control of the read enable signal and the write enable signal Within two clock cycles, the synchronization of data between the two clock domains is also within two clock cycles. Therefore, compared with the existing scheme of delaying at least two clock cycles for data synchronization between the two clock domains, this application The data synchronization delay can be controlled within two clock cycles, which reduces the data synchronization delay and improves the efficiency of data cross-clock domain processing.

Description of drawings

Fig. 1 is the structural diagram of existing asynchronous FIFO;

FIG. 2 is a structural diagram of the cross-clock domain synchronization circuit of the present application;

Fig. 3 is the structural diagram of the clock domain channel circuit of the present application;

Fig. 4 (a) is a kind of phase relationship of the read-write clock domain of the present application;

Fig. 4 (b) is another kind of phase relationship of the read-write clock domain of the present application;

Fig. 4 (c) is another kind of phase relationship of the read-write clock domain of the present application;

Fig. 4 (d) is another kind of phase relationship of the read-write clock domain of the present application;

Fig. 5 (a) is a kind of signal sampling result of the present application;

Fig. 5 (b) is another kind of signal sampling result of the present application;

Fig. 5 (c) is another kind of signal sampling result of the present application;

Fig. 5(d) is another signal sampling result of the present application.

Detailed ways

The present application provides a cross-clock domain synchronization circuit, which can be applied to field-programmable gate array (field-programmable gate array, FPGA), and can also be applied to application specific integrated circuits (application specific integrated circuits, ASIC) chips, and can also be applied to Other devices are not limited here.

Referring to Fig. 2, the cross-clock domain synchronous circuit of the present application comprises write address generation circuit 01, read address generation circuit 02 and data cache circuit, wherein data cache circuit comprises circuit a plurality of flip-flop groups 05, input multiplex data selector 06 ( multiplexer, MUX) and output multiplex data selector 07, the cross-clock domain synchronization circuit also includes a fifth D flip-flop 08, a phase detector 03, a clock domain channel circuit 04, and a write clock domain phase-locked loop 09 (phase locked loop, PLL) and read clock domain PLL 010.

First, the write clock domain PLL 09 can generate the write clock signal in the write clock domain, the read clock domain PLL 010 can generate the read clock signal in the read clock domain, the input terminal of the write clock domain PLL 09 and the read clock domain The input of the phase-locked loop 010 is connected to the same clock source to ensure that the clock in the write clock domain and the clock in the read clock domain are homologous clocks. The purpose is to ensure that the two clocks have no frequency deviation and generate write clock signals with equal frequencies. and the read clock signal, or generate a write clock signal and a read clock signal whose frequency division ratio is an integer multiple, and at the same time, the clock phase difference between the write clock signal and the read clock signal is random.

Write address generation circuit 01: driven by the write clock signal in the write clock domain, when the write enable signal is valid, the write pointer can be continuously generated, and the write address can be used as the write address, wherein the write enable signal can be generated by the phase detector 03 generated. An input port of the write address generation circuit 01 is connected to the output port of the write clock domain PLL 09, and can receive the write clock signal, and another input port of the write address generation circuit 01 is connected to the first output port of the phase detector 03, The write enable signal can be received, the output port of the write address generating circuit 01 is connected to the input port of the input multiplexer 06, and the write address can be output.

The data cache circuit includes an input multiplexer 06, a plurality of flip-flop groups 05, and an output multiplexer 07. The data cache circuit can receive input data according to the write address, and then cache the input data. The data cache circuit can also be read according to the The address generates output data, the specific process is:

The write address is input to the input multiplexer 06, and after the input multiplexer 06 obtains the input data, the buffer data can be output from an output port of the input multiplexer 06 according to the address information indicated by the write address , so that the cache data is written into a certain trigger group of multiple trigger groups 05, the address information indicated by the write address can indicate that the cache data is written into a specific trigger group of multiple trigger groups 05, a certain trigger group The device group corresponds to a certain output port. The address information indicated by the write address is variable, so the input multiplexer 06 can output cached data from multiple ports of the input multiplexer 06 according to the indication of the write address, and the cached data output by multiple ports Correspondingly enter multiple trigger groups 05. The two data terminals of the input multiplexer 06 respectively receive the input data and the write address generated by the write address generation circuit 01, and the multiple input ports of the multiple flip-flop groups 05 and the multiple output ports of the input data multiplexer 06 The one-to-one correspondence connection can receive the cached data, and the multiple output ports of the multiple flip-flop groups 05 can be connected with the multiple input ports of the output multiplexer 07 in a one-to-one correspondence to output the cached data.

Further, regarding the above-mentioned multiple flip-flop groups 05, four groups of D flip-flop groups are taken as an example in FIG. The trigger input port of the group is connected to the write clock signal, driven by the write clock signal, the four-way buffer data processed by the input multiplexer 06 is respectively input to the four groups of D flip-flop groups.

A plurality of flip-flop groups 05 buffer the multi-way cache data, and then output the multi-way cache data to the output multiplex data selector 07, and the output multiple-way data selector 07 can select one way from the multi-way cache data according to the indication of the read pointer The buffer data is output as output data, and the specific read pointer can be used as a read address, which carries address information, and the address information indicated by the read address can instruct the output multiplexer 07 to output specific D from multiple flip-flop groups 05 The cache data obtained in the flip-flop group has different read addresses, and the cache data selected and output by the output multiplexer 07 is different. One input port of the output multiplexer 07 is connected to the output ports of a plurality of flip-flop groups 05 to receive cached data, and another input port of the output multiplexer 07 is connected to the output port of the read address generating circuit 02, A read address can be received.

The output data generated by the output multiplexer 07 is input to the fifth D flip-flop 08, driven by the read clock signal, the fifth D flip-flop 08 can buffer and output the output data generated by the data buffer circuit, the fifth D flip-flop 08 It can prevent the impact of external interference on the correctness of data transmission during data transmission.

The phase detector 03 (phase detector, PD) can calculate the clock phase difference between the write clock signal in the write clock domain and the read clock signal in the read clock domain. When the write clock domain and the read clock domain are stable, the phase detector 03 After entering the working state, after several clock cycles, the phase detector 03 generates a stable clock phase difference and outputs it to the clock domain channel circuit 04 . At the same time, the phase detector 03 can also process the write clock signal in the write clock domain to obtain a write enable signal, and output the write enable signal to the write address generation circuit 01 and the clock domain channel circuit 04, and the write enable signal is used as a phase detector The device 03 stably outputs the state indication of the clock phase difference. When the clock phase difference is in a stable state, the write enable signal is valid, otherwise the write enable signal is invalid. One input of the phase detector 03 is connected to the write clock domain PLL 09 to receive the write clock signal, and the other input of the phase detector 03 is connected to the read clock domain PLL 010 during writing to receive the read clock signal , the first output port of the phase detector 03 is connected to another input port of the write address generating circuit 01 and the first input port of the clock domain channel circuit 04, which can output a write enable signal, and the second output port of the phase detector 03 Connected to the second input port of the clock domain channel circuit 04, it can output the clock phase difference.

Clock domain channel circuit 04 circuit: The clock domain channel circuit 04 can synchronize the write enable from the write clock domain to the read clock domain according to the four states of the clock phase difference, obtain the read enable signal, and then output the read enable signal to the read address The generation circuit 02, the read address generation circuit 02 can be driven by the read clock signal in the read clock domain, and when the read enable signal is valid, continuously generate read pointers, which are output to the multiplexer 07 as read addresses. The output port of the clock domain channel circuit 04 is connected to an input port of the read address generation circuit 02, which can output a read enable signal, and another input port of the read address generation circuit 02 is connected to the output port of the read clock domain phase-locked loop 010, which can After receiving the read clock signal, the output port of the read address generating circuit 02 is connected to the other input port of the output multiplexer 07 to output the read address.

Based on the above structure, the write address generating circuit 01 generates a write address, writes data into the data cache circuit, and the clock domain channel circuit 04 can obtain a read enable signal according to the write enable signal and the clock phase difference, thereby converting the write enable signal from the write The clock domain is synchronized to the read clock domain, and the read address generation circuit 02 obtains the read address according to the read enable signal, and reads the data from the data buffer circuit, thereby realizing the synchronization of the input data from the write clock domain to the read clock domain.

At the same time, since the read enable signal changes with the clock phase difference, and the read enable signal can obtain the read pointer, then under different clock phase difference conditions, the read pointer is also different, the read address changes, and the output multiplexer 07 selects The obtained output data also changes, so the scheme of the present application sets four-way buffer data to meet the requirement of data synchronization under different clock phase difference conditions.

Based on the functions of the above-mentioned clock domain channel circuit 04, the generation process of the read address is described in detail below:

Figure 3 is the specific structure of the clock domain channel circuit 04 of the present application, the clock domain channel circuit 04 includes a first flip-flop 041, a second flip-flop 042, a third flip-flop 043, a fourth flip-flop 044 and a multiplexer 045 , the first output port of the phase detector 03 is specifically connected to the input port of the first flip-flop 041, the output port of the first flip-flop 041 is connected to the input port of the second flip-flop 042, and the first output port of the phase detector 03 Specifically, it is also connected to the input port of the third flip-flop 043, the output port of the third flip-flop 043 is connected to the input port of the fourth flip-flop 044, the output port of the first flip-flop 041, the output port of the second flip-flop 042, The output port of the third flip-flop 043 and the output port of the fourth flip-flop 044 are connected with another input port of the multiplexer, and the output port of the multiplexer 045 is connected with the input port of the read address generation circuit 02 Referring to Figure 3, taking the write clock domain and the read clock domain as an example with the same source, same frequency and asynchronous clock, the frequency between the write clock signal and the read clock signal is the same, and the clock phase difference is random. The clock domain channel circuit 04 of this application will write The specific process of synchronizing the enable signal from the write clock domain to the read clock domain is as follows:

As mentioned above, the phase detector 03 generates a write enable signal, and the write enable signal enters the write address generation circuit 01, and at the same time, the write enable signal also enters the clock domain channel circuit 04, specifically:

The write enable signal enters the first flip-flop 041, and the read clock signal is used as the sampling pulse, and the first flip-flop 041 samples the write enable signal at the falling edge of the read clock signal to obtain the first sampling signal, and subsequently, the first sampling signal Enter the second flip-flop 042, also read the clock signal as the sampling pulse, sample the first sampling signal on the rising edge of the read clock signal to obtain the second sampling signal, and the write enable signal of the write clock domain also enters the third flip-flop 043 , with the read clock signal as the sampling pulse, the third flip-flop 043 samples the write enable signal at the falling edge of the read clock signal to obtain the third sampling signal, and then the third sampling signal enters the fourth flip-flop 044, and the read clock The signal is used as a sampling pulse, and the third sampling signal is sampled at the rising edge of the read clock signal to obtain a fourth sampling signal. The first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal belong to the sampling signal set, and the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal are respectively output to the multiplexer 045, the clock phase difference obtained by the phase detection of the phase detector 03 is also input to the multiplexer 045, and the multiplexer 045 selects one sampling signal as the write-in signal according to the clock phase difference obtained by the phase detection of the phase detector 03 The enable signal is output to the read address generation circuit 02 to generate the read address.

Compared with the prior art using registers for write pointer synchronization or read pointer synchronization, the register needs to ensure the setup time and hold time of the data, so it needs to wait at least two clock cycles, and in this embodiment, the write enable signal is used to The sampling signal set is obtained by sampling, and the sampling signal in the sampling signal set can be used as a read enable signal. Since the flip-flop can sample the signal on both the rising edge and the falling edge of the clock signal, all the sampling signals in the sampling signal set can be obtained from the write enable signal. Or part of the sampling signal can be controlled within two clock cycles, and the corresponding data synchronization from the write clock domain to the read clock domain can also be controlled within two clock cycles, which reduces the delay of data synchronization compared with the prior art.

There are four possible situations for the clock phase difference of phase detector 03 in this application, and there are four possible situations for the selected read enable signal. The general idea of selection is to ensure that the write enable signal does not appear metastable, as follows Describe the four situations:

First, the clock phase difference refers to the phase difference between the write clock signal in the write clock domain and the read clock signal in the read clock domain. This application presets the mapping relationship between the clock phase difference and the read enable signal. The clock phase difference is different and the read enable signal is different. Specifically:

1. The clock phase difference obtained by the phase detector 03 is: the clock phase difference belongs to [0T, 1/4T), T is the clock period of the write clock domain, as shown in Figure 4(a), the write clock signal The clock phase difference between the read clock signal and the read clock signal is 1/8T as an example, corresponding to the clock phase difference in Figure 4(a), as shown in Figure 5(a), use the read clock signal to enable writing in the manner described above Signal sampling, the third sampling signal obtained by sampling will appear metastable, and the fourth sampling signal may also appear metastable, but the first sampling signal and the second sampling signal will not appear metastable, in order to ensure certain data Synchronous delay, so as to ensure that there is enough time to read data, but the data synchronization delay can not be too large, generally within 2 clock cycles, the multiplexer 045 selects the second sampling signal as the read enable signal and generates Read the address, the read address is about 1.25 clock cycles later than the write address, then the data synchronization delay from the read clock domain to the write clock domain is about 1.25 clock cycles.

2. The clock phase difference obtained by the phase detector 03 is: the clock phase difference between the write clock domain and the read clock domain belongs to [1/4T, 1/2T), and T is the clock period of the write clock domain, as shown in Figure 4 As shown in (b), taking the clock phase difference between the write clock signal and the read clock signal as 3/8T as an example, corresponding to the clock phase difference in Figure 4(b), as shown in Figure 5(b), using the read clock signal according to The method described above samples the write enable signal. The first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal obtained by sampling will not appear metastable. In order to ensure a certain data synchronization delay, Thereby ensure that there is enough time to read data, but the data synchronization delay can not be too large, generally within 2 clock cycles, the multiplexer 045 selects the second sampling signal or the fourth sampling signal as the read enable signal and Generate a read address, where the second sampling signal and the fourth sampling signal are delayed by the same clock cycle relative to the write enable signal, and the read address is about 1.5 clock cycles later than the write address, then from the read clock domain to the write clock domain The data synchronization delay is about 1.5 clock cycles.

3. The clock phase difference obtained by the phase detector 03 is: the clock phase difference between the write clock domain and the read clock domain belongs to [1/2T, 3/4T), and T is the clock period of the write clock domain, as shown in Figure 4 As shown in (c), taking the clock phase difference between the write clock signal and the read clock signal as 5/8T as an example, corresponding to the clock phase difference in Figure 4(c), as shown in Figure 5(c), using the read clock signal according to The method described above samples the write enable signal. The first sampled signal and the second sampled signal obtained by sampling appear metastable, and the third sampled signal and the fourth sampled signal do not appear metastable. In order to ensure certain data Synchronous delay, so as to ensure that there is enough time to read data, but the data synchronization delay can not be too large, generally within 2 clock cycles, the multiplexer 045 selects the fourth sampling signal as the read enable signal and generates Read address, the read address is about 1.5 clock cycles later than the write address, then the data synchronization delay from the read clock domain to the write clock domain is about 1.5 clock cycles.

4. The clock phase difference obtained by phase detector 03 is: the value of the phase difference between the write clock domain and the read clock domain is greater than or equal to 3/4 clock cycle T, and T is the clock cycle of the write clock domain, as shown in the figure As shown in 4(d), taking the clock phase difference between the write clock signal and the read clock signal as 7/8T as an example, corresponding to the clock phase difference in Figure 4(d), as shown in Figure 5(d), using the read clock signal according to The method described above samples the write enable signal. The first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal obtained by sampling will not appear metastable. In order to ensure a certain data synchronization delay, Thereby ensure that there is enough time to read data, but the data synchronization delay can not be too large, generally within 2 clock cycles, the multiplexer 045 selects the second sampling signal or the third sampling signal as the read enable signal and Generate a read address, where the second sampling signal and the third sampling signal are delayed by the same clock cycle relative to the write enable signal, and the read address is about 1 clock cycle later than the write address, then from the read clock domain to the write clock domain The data synchronization delay is about 1 clock cycle.

Based on the above cross-clock domain synchronization circuit, the clock domain channel circuit 04 can sample the write enable signal to obtain multiple sampling results. Among the multiple sampling results obtained, there are some or all of the sampling results with a delay relative to the write enable signal. Within two clock cycles, secondly, there is a clock phase difference between the write clock signal of the write clock domain and the read clock signal of the read clock domain, and according to the clock phase difference, a read enable signal is selected from multiple sampling results, The selected delay of the read enable signal and write enable signal can be controlled within two clock cycles. The data synchronization between the two clock domains is also within two clock cycles. Therefore, compared with the existing data synchronization between the two clock domains, which has a delay of at least two clock cycles, the data synchronization delay in this application is relatively small. .

The present application also provides a cross-clock domain synchronization method, which can be applied to the above-mentioned cross-clock domain synchronization circuit, so as to realize the functions of the above-mentioned cross-clock domain synchronization circuit.

Through the description of the above embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software plus necessary general-purpose hardware, and of course it can also be realized by special hardware including application-specific integrated circuits, dedicated CPUs, dedicated memories, Special components, etc. to achieve. In general, all functions completed by computer programs can be easily realized by corresponding hardware, and the specific hardware structure used to realize the same function can also be varied, such as analog circuits, digital circuits or special-purpose circuit etc. However, for this application, software program implementation is a better implementation mode in most cases. Based on this understanding, the essence of the technical solution of this application or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product is stored in a readable storage medium, such as a floppy disk of a computer , U disk, mobile hard disk, read-only memory (read-only memory, ROM), random access memory (random access memory, RAM), magnetic disk or optical disk, etc., including several instructions to make a computer device (which can be personal computer or server, etc.) to execute the methods described in the various embodiments of the present application.

In the above embodiments, all or part of them may be implemented by software, hardware, firmware or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product.

The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions according to the embodiments of the present application will be generated in whole or in part. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server, or data center Transmission to another website site, computer, server, or data center by wired (eg, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be stored by a computer, or a data storage device such as a server or a data center integrated with one or more available media. The available medium may be a magnetic medium (for example, a floppy disk, a hard disk, or a magnetic tape), an optical medium (for example, DVD), or a semiconductor medium (for example, a Solid State Disk (SSD)).

Claims (13)

1. A cross clock domain synchronous circuit, it is characterized in that, described cross clock domain synchronous circuit comprises clock domain channel circuit, write address generation circuit, read address generation circuit and data cache circuit, wherein: The write address generation circuit is used to obtain a write address according to a write enable signal, and the write address is used to control the data buffer circuit to receive input data, and the input data is in the write clock domain; The clock domain channel circuit is used to sample the write enable signal to obtain a plurality of sampling results, and select a sampling result from the plurality of sampling results according to the clock phase difference as the read enable signal, wherein the The clock phase difference is the phase difference between the write clock signal in the write clock domain and the read clock signal in the read clock domain; The read address generation circuit is used to obtain a read address according to the read enable signal, and the read address is used to control the data buffer circuit to generate output data, and the output data is in the read clock domain; The data cache circuit is used to cache the input data and generate the output data according to the write address and the read address. 2. The cross-clock domain synchronous circuit according to claim 1, wherein the clock domain channel circuit comprises: a plurality of flip-flops, which are used to control the Sampling the write enable signal to obtain the plurality of sampling results; A multiplexer, configured to select one sampling result from the plurality of sampling results according to the clock phase difference as the read enable signal. 3. The cross-clock domain synchronization circuit according to claim 2, wherein the plurality of flip-flops comprises a first flip-flop, a second flip-flop, a third flip-flop and a fourth flip-flop; The first flip-flop is configured to sample the write enable signal at the falling edge of the read clock signal to obtain a first sampling signal; The second flip-flop is configured to sample the first sampling signal at a rising edge of the read clock signal to obtain a second sampling signal; The third flip-flop is configured to sample the write enable signal at the rising edge of the read clock signal to obtain a third sampling signal; The fourth flip-flop is configured to sample the third sampling signal on the rising edge of the read clock signal to obtain a fourth sampling signal, wherein the first sampling signal, the second sampling signal, The third sampling signal and the fourth sampling signal are the plurality of sampling results. 4. The cross-clock domain synchronization circuit according to claim 3, wherein the multiplexer is specifically used for: In the case that the clock phase difference is [0T, 1/4T), the second sampling signal is selected from the plurality of sampling results as the read enable signal, wherein the T is the write The clock period of the clock domain or the clock period of the read clock domain; or, When the clock phase difference is [1/4T, 1/2T), select the second sampling signal or the fourth sampling signal from the plurality of sampling results as the read enable signal; or, When the clock phase difference is [1/2T, 3/4T), select the fourth sampling signal from the plurality of sampling results as the read enable signal; or, When the value of the clock phase difference is greater than or equal to 3/4 of the clock period T, selecting the second sampling signal or the third sampling signal from the plurality of sampling results as the Read enable signal. 5. The cross-clock domain synchronization circuit according to any one of claims 1 to 4, wherein the cross-clock domain synchronization circuit further comprises a phase detector; The phase detector is configured to determine the clock phase difference according to the write clock signal and the read clock signal; The phase detector is further configured to generate the write enable signal according to the write clock signal, wherein, when the clock phase difference between the write clock signal and the read clock signal is in a stable state, The write enable signal is valid. 6. The cross-clock domain synchronization circuit according to any one of claims 1 to 4, wherein the cross-clock domain synchronization circuit further comprises a fifth D flip-flop; The fifth D flip-flop is configured to buffer and output the output data generated by the data buffer circuit driven by the read clock signal. 7. The cross-clock domain synchronization circuit according to any one of claims 1 to 4, wherein the cross-clock domain synchronization circuit also includes a write clock domain phase-locked loop and a read clock domain phase-locked loop; The write clock domain phase-locked loop is used to obtain the write clock signal according to the clock source signal; The read clock domain phase-locked loop is used to obtain the read clock signal according to the clock source signal. 8. The cross-clock domain synchronization circuit according to any one of claims 1 to 4, wherein the data buffer circuit comprises a plurality of flip-flop groups, an input multiplexer and an output multiplexer, The input data selector includes a plurality of output ports that are connected to the plurality of input terminals of the plurality of flip-flop groups in one-to-one correspondence, and the output multiplex data selector includes a plurality of The output ports are connected to multiple input ports in one-to-one correspondence; The input multiplexer is configured to receive the input data, and select an output port from the plurality of output ports of the input multiplexer to output buffer data according to the write address, so The buffer data is obtained from the input data; The multiple flip-flop groups are used to cache the cached data driven by the write clock signal; The output multiplexer is configured to receive a plurality of cache data output by the plurality of flip-flop groups, and select one cache data from the multiple cache data according to the read address as the The output data output described above. 9. A cross-clock domain synchronization method, characterized in that the method comprises: Obtain a write address according to the write enable signal, receive and buffer input data according to the control of the write address, and the input data is in the write clock domain; Sampling the write enable signal to obtain a plurality of sampling results, and selecting a sampling result from the plurality of sampling results according to the clock phase difference as the read enable signal, wherein the clock phase difference is at the The phase difference between the write clock signal in the write clock domain and the read clock signal in the read clock domain; A read address is obtained according to the read enable signal, and the buffered input data is output according to the control of the read address to generate output data, and the output data is in the read clock domain. 10. The method according to claim 9, wherein the sampling the write enable signal to obtain a plurality of sampling results comprises: The write enable signal is respectively sampled at a rising edge and a falling edge of the read clock signal to obtain the plurality of sampling results. 11. The method according to claim 10, wherein sampling the write enable signal at a rising edge and a falling edge of the read clock signal, so as to obtain the plurality of sampling results comprises: Sampling the write enable signal at the falling edge of the read clock signal to obtain a first sampling signal; Sampling the first sampling signal at a rising edge of the read clock signal to obtain a second sampling signal; Sampling the write enable signal at the rising edge of the read clock signal to obtain a third sampling signal; Sampling the third sampling signal at the rising edge of the read clock signal to obtain a fourth sampling signal, wherein the first sampling signal, the second sampling signal, the third sampling signal and the The fourth sampling signal is the plurality of sampling results. 12. The method according to any one of claims 11, wherein the selecting a sampling result from the plurality of sampling results according to the clock phase difference as the read enable signal comprises: In the case that the clock phase difference is [0T, 1/4T), the second sampling signal is selected from the plurality of sampling results as the read enable signal, wherein the T is the write The clock period of the clock domain or the clock period of the read clock domain; or, When the clock phase difference is [1/4T, 1/2T), select the second sampling signal or the fourth sampling signal from the plurality of sampling results as the read enable signal; or, When the clock phase difference is [1/2T, 3/4T), select the fourth sampling signal from the plurality of sampling results as the read enable signal; or, When the value of the clock phase difference is greater than or equal to 3/4 of the clock period T, selecting the second sampling signal or the third sampling signal from the plurality of sampling results as the Read enable signal. 13. The method according to any one of claims 9 to 12, further comprising: determining the clock phase difference according to the write clock signal and the read clock signal; The write enable signal is generated according to the write clock signal, wherein the write enable signal is valid when the clock phase difference between the write clock signal and the read clock signal is in a stable state.

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