CN1051879C - Double-layered polycrystal CMOS hybrid digital-analog integrated circuit and its manufacture - Google Patents

Abstract

A double-layer polysilicon CMOS digital-analog hybrid integrated circuit and its manufacturing method are based on the common CMOS process and use double-layer polysilicon to integrate digital circuits and analog circuits into an integrated circuit at the same time to make resistors with required resistance values. and the upper electrode of the capacitor. Therefore, the circuit of the present invention includes a semiconductor substrate, which is basically of the first conductivity type, and only has some surface layers of the second conductivity type on a part of the surface, and has some channels on the surface of the first conductivity type for the second conductivity type. A type of MOS transistor, the surface of the semiconductor substrate is partially covered with some thick insulators, which is characterized by resistance and capacitance on the insulators.

Description

Double-layer polysilicon CMOS digital-analog hybrid integrated circuit and its manufacturing method

The invention relates to a digital-analog hybrid CMOS integrated circuit and a manufacturing method thereof.

The development of VLSI technology has been able to integrate more and more system digital circuit functions into an integrated circuit, and is integrating the system's analog circuit functions into an integrated circuit at the same time. Digital-analog hybrid integrated circuits are attracting more and more attention. As a milestone in the development of integrated circuit technology, CMOS integrated circuit technology is beyond doubt, and it also has the potential of simultaneous integration of digital circuits and analog circuits. But the common single-layer polysilicon CMOS integrated circuit manufacturing process is not suitable for manufacturing digital-analog hybrid CMOS integrated circuits. In the single-layer polysilicon CMOS integrated circuit manufacturing process described on pages 215 to 219 of the book "LSI Prosess Engineering" edited by Zuo Gaozhengjun and published by Japan's O-M Publishing House, the resistance values of capacitors and resistors cannot be manufactured. It cannot be set arbitrarily as needed, therefore, it is impossible to manufacture a digital-analog hybrid circuit, which makes the current method: use an analog/digital conversion circuit or a digital/analog conversion circuit to transition between a digital integrated circuit and an analog circuit. The circuit combination form is often difficult to meet the user's requirements for system reliability and confidentiality.

The object of the present invention is to provide an easy-to-implement digital-analog hybrid integrated circuit and a manufacturing method.

The technical solution of the present invention is to adopt the method compatible with complementary metal-oxide-semiconductor (CMOS) integrated circuit manufacturing process with the manufacture of resistance and electric capacity, integrate on the integrated circuit simultaneously, i.e. the method of the present invention, comprises first using standard CMOS Single-layer polysilicon is prepared by the process, which is characterized in that the first layer of polysilicon is etched by photolithography to form the gate of the standard CMOS process P-channel MOS transistor and N-channel MOS transistor and the lower electrode of the polysilicon capacitor. The deposition method deposits a second layer of polysilicon, which forms the upper electrode of the polysilicon resistor and the polysilicon capacitor at the same time after ion implantation of two different doses of the second layer of polysilicon.

In the method of the present invention, the preparation of the polysilicon resistance is completed by performing boron fluoride (BF ₂ ⁺ ) ion implantation in the polysilicon deposited by low-pressure chemical vapor phase, annealing in the nitrogen atmosphere of the diffusion furnace, and then completing the etching by photolithography .

The upper and lower electrodes of polysilicon capacitors are composed of polysilicon deposited by low-pressure chemical vapor phase. Both the upper and lower electrodes are implanted with phosphorus ions, annealed in a nitrogen atmosphere of a diffusion furnace, and then photoetched and etched.

The digital-analog hybrid circuit of the present invention made according to the method of the present invention comprises a semiconductor substrate, which is basically of the first conductivity type, and only has some surface layers of the second conductivity type on the partial surface, and on the surface of the first conductivity type Some channels are MOS transistors of the second conductivity type, and the surface of the semiconductor substrate is partially covered by some thick insulators, which are characterized by resistance and capacitance on the insulators.

Further, in the circuit of the present invention, the lower electrode of the capacitor and the gate of the MOS transistor are made of the same layer of polysilicon material and the upper electrode of the capacitor and the resistor are made of the second layer of polysilicon, but the The dosage of dopant injection varies according to the requirement of conductivity.

The advantages of the present invention are: 1. A double-layer polysilicon CMOS digital-analog hybrid integrated circuit is prepared by using a method compatible with common CMOS standard processes, which is mature in technology and easy to implement; 2. Reduces the complexity of the system and the number of components used; 3. , Improve the reliability and confidentiality of the system.

The accompanying drawings of the present invention are briefly described as follows:

Fig. 1 is a schematic process flow diagram of the method of the present invention.

Fig. 2 is a schematic circuit diagram of the present invention.

Now provide a better embodiment of the present invention according to Fig. 1 and Fig. 2.

Please refer to Fig. 1, the preparation process of the present invention roughly includes 38 steps, and the process is as follows: P well oxidation 1, P well photolithography 2, P well implantation 3, P well advancement 4, base oxygen 5, LPCVD silicon oxide 6. Active area lithography 7, field implant lithography 8, field implant 9, field oxidation 10, removal of silicon oxide 11, pre-gate oxide 12, trench lithography 13, channel implant 14, gate oxidation 15, polysilicon 1 Deposition 16, Polysilicon 1 Lithography 17, Polysilicon 1 Oxidation 18, N+ Lithography 19, N+ Implantation 20, N+ Advancement 21, P+ Lithography 22, P+ Implantation 23, Source Drain Reoxidation 24, Polysilicon II Deposition 25, Polysilicon Resistance Implantation 26. Polysilicon resistance lithography 27, polysilicon II implantation 28, polysilicon II annealing 29, polysilicon II lithography 30, BPSG deposition 31, lead hole lithography 32, metal deposition 33, metal lithography 34, alloying 35, deposition passivation layer 36, indenter lithography 37 and test 38.

The feature of the present invention is that in the photolithography 17 of the polysilicon 1, not only the grid of the digital circuit part is prepared, but also the lower electrode of the capacitor of the analog circuit part is prepared. In the 25 to 30 process of polysilicon II deposition, the upper electrode of the resistance and capacitance of the analog circuit part was prepared by ion implantation twice with different doses. In this way, on the basis of the original process, the digital circuit and the analog circuit are integrated into an integrated circuit at the same time with double-layer polysilicon, and a digital-analog mixed CMOS integrated circuit is made.

Main process parameters

Silicon wafer substrate resistivity 4-7Ω·cm

P well oxide layer 4300A

P well sheet resistance 2.5KΩ/□

Base oxygen 550A

Silicon Nitride 1500A

Field oxygen 7000A

Pre-Oxygen 450A

Gate oxide 350A

Polysilicon 1 Thickness 4500A

Polysilicon 1 sheet resistance 25Ω/□

Polysilicon 1 oxide layer 600A

Polysilicon 2 thickness 4500A

Polysilicon 2 high-resistance sheet resistance 4KΩ/□

Polysilicon 2 upper electrode sheet resistance 25Ω/□

N+ sheet resistance 40Ω/□

P+sheet resistance 90Ω/□

NSG/BPSG 2000A/7000A

Al-Si 10000A

Enhanced P-channel MOS tube V _TP -0.70±0.10V BV≥14V

Enhanced N-channel MOS transistor V _TN -0.70±0.10V BV≥14V

Depletion N-channel MOS tube 1V _TND1 -0.15±0.10V

Depletion N-channel MOS tube 2V _TND2 -0.30±0.10V

Depletion N-channel MOS tube 3V _TND3 -0.45±0.10V

Polysilicon capacitor 5.76×10 ^-4 PF/μm ² BF≥30V

Please refer to shown in Fig. 2, the CMOS integrated circuit of the present invention has a substrate 41 that silicon or other semiconductor materials are made of, and this substrate (also known as substrate) is the first conductivity type, is n-type in the present embodiment, only There are some surface layers 42 of the second conductivity type (p-type in this embodiment) on part of the surface, and these surface layers are generally called wells 42 . In this way, some regions on the surface 43 of the semiconductor substrate are of the first conductivity type (n-type), while other regions are of the second conductivity type (p-type). On the surface of the first conductivity type, several channels are metal oxide semiconductor (MOS) transistors 44 (in this example, P channel MOS transistors) of the second conductivity type, and there are several grooves on the surface of the second conductivity type (the surface of the well). The channel is a metal-oxide-semiconductor (MOS) transistor 45 of the first conductivity type (in this embodiment, an N-channel MOS transistor). On the surface 43 of the semiconductor substrate 41, some areas are covered by thicker silicon oxide 46, and these thicker silicon oxides are generally called field oxide layers; some areas are covered by thinner silicon oxide 47, and these are thinner. The gate oxide layer is often referred to as the gate oxide layer. In the area of the gate oxide layer (also referred to as the active area), N-channel MOS transistors and P-channel MOS transistors are fabricated. These MOS transistors have a source 48 , a drain 49 and a gate 50 . In this embodiment, the source and drain of the N-channel transistor are prepared on the surface 43 of the well 42 , and the P-channel transistor is directly prepared on the semiconductor substrate 41 and the surface 43 . The gates of both N-channel transistors and P-channel transistors are formed by depositing polysilicon by low-pressure chemical vapor deposition (LPCVD). A double-layer polysilicon capacitor 51 and a polysilicon resistor 42 are fabricated on thicker silicon oxide (field oxide layer). The polysilicon capacitor 51 is composed of a lower electrode 53 , an interlayer insulator 54 and an upper electrode 55 . The lower electrode 53 of the polysilicon capacitor 51 and the gate 50 of the MOS transistors 44, 45 are made of polysilicon deposited by the same layer of LPCVD method, and its conductivity type and resistivity are also the same (polysilicon is n-type in this embodiment) , so it is the most beneficial for the integrated circuit production process. The interlayer insulator 54 of the polysilicon capacitor 51 can be made of silicon oxide formed by peroxidation of polysilicon, or a composite structure of silicon oxide/silicon nitride/silicon oxide. The upper electrode 55 of the polysilicon capacitor 51 and the polysilicon resistor 52 are made of another layer (second layer) of polysilicon deposited by LPCVD method, but their conductivity type and resistivity are different. Wherein the upper electrode 55 of the polysilicon capacitor 51 is made of n-type low-resistivity polysilicon by injecting phosphorus with a high dose of ion implantation, which is the same as the gate 50 of the above-mentioned MOS transistor and the lower electrode 53 of the polysilicon capacitor 51, and the polysilicon resistor 52 is made of P-type high-resistance polysilicon by implanting boron fluoride in an appropriate dose by ion implantation. The implanted dose of boron fluoride is determined by the resistance value of polysilicon resistor 52 required for integrated circuit design. Subsequent work of insulating dielectric deposition and metal wiring can be manufactured according to methods known to those skilled in the art, and will not be described in detail here.

In this way, on the basis of the original ordinary (CMOS process), the digital circuit and the analog circuit are integrated into an integrated circuit at the same time with double-layer polysilicon, and a digital-analog mixed CMOS integrated circuit is made.

Claims (6)

1. A method for manufacturing a double-layer polysilicon CMOS digital-analog hybrid integrated circuit, comprising first preparing a single-layer polysilicon with a standard CMOS process, characterized in that the first layer of polysilicon is photolithographically etched to form a standard CMOS process P-channel MOS transistor and N The gate of the ditch MOS transistor and the lower electrode of the polysilicon capacitor, and after the polysilicon is oxidized, the second layer of polysilicon is deposited by the method of low-temperature vapor deposition. Top electrode of polysilicon resistors and polysilicon capacitors. 2. The manufacturing method of double-layer polysilicon CMOS digital-analog hybrid integrated circuit according to claim 1, characterized in that the preparation of the polysilicon resistance is carried out by boron fluoride BF ₂ ⁺ ion implantation in the polysilicon deposited by low-pressure chemical vapor phase. After annealing in the nitrogen atmosphere of the diffusion furnace, it is completed after photoetching. 3. The method for manufacturing a double-layer polysilicon CMOS digital-analog hybrid integrated circuit according to claim 1, characterized in that the upper and lower electrodes of the polysilicon capacitor are made of polysilicon deposited by low-pressure chemical vapor phase, and the upper and lower electrodes are both After phosphorus ion implantation, annealing is carried out in the nitrogen atmosphere of the diffusion furnace, and it is completed after photoetching and etching. 4. A double-layer polysilicon CMOS digital-analog hybrid integrated circuit made according to the manufacturing method of the double-layer polysilicon CMOS digital-analog hybrid integrated circuit according to claim 1, comprising a semiconductor substrate, the substrate is basically the first conductivity type , there are some surface layers of the second conductivity type only on part of the surface, and some channels are MOS transistors of the second conductivity type on the surface of the first conductivity type, and the surface of the semiconductor substrate is partially covered by some thick insulators, and its characteristics There is resistance and capacitance on the insulator. 5. The double-layer polysilicon CMOS digital-analog hybrid integrated circuit according to claim 4, wherein the lower electrode of the capacitor and the gate of the MOS transistor are made of the same layer of polysilicon material. 6. The double-layer polysilicon CMOS digital-analog hybrid integrated circuit according to claim 4, characterized in that the upper electrode of the capacitor and the resistor are made of the second layer of polysilicon, but the doping dose is determined according to the conductivity requirements vary.

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