Guzmán et al., 2016 - Google Patents
FPGA implementation of the AES-128 algorithm in non-feedback modes of operationGuzmán et al., 2016
View HTML- Document ID
- 8640951933316378347
- Author
- Guzmán I
- Nieto R
- Bernal Ã
- Publication year
- Publication venue
- Dyna
External Links
Snippet
In this paper, we present a hardware implementation of the pipelined AES-128 algorithm that works on non-feedback modes of operation (ECB and CTR). The architecture was implemented using the Xilinx Virtex 5 FPGA platform. We compared two modes of operation …
- 230000001131 transforming 0 description 31
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- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0637—Modes of operation, e.g. cipher block chaining [CBC], electronic codebook [ECB] or Galois/counter mode [GCM]
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- H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
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- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
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