CN104868701A - Hybrid compensation circuit of power converter - Google Patents

Abstract

The present invention provides a hybrid compensation circuit for a power converter, which generates a digital signal according to a feedback signal and a reference value related to the output voltage of the power converter, converts the digital signal into an analog first signal, and offsets the first signal by a variable offset value to generate a second signal, and filters out the high-frequency component of the second signal to generate a third signal to stabilize the output voltage. The hybrid compensation circuit does not need to use a large capacitor, so it can be integrated into an integrated circuit.

Description

Hybrid Compensation Circuit for Power Converter

technical field

The invention relates to a power converter, in particular to a hybrid compensation circuit of the power converter.

Background technique

In the feedback loop of the power converter, a compensation circuit is required to compensate the phase margin to stabilize the loop. The traditional analog compensation circuit includes the EA type compensation circuit 10 shown in FIG. 1 or the gm type compensation circuit 14 shown in FIG. 2 . Referring to Fig. 1, the EA type compensation circuit 10 includes an error amplifier 12, the capacitor C1 and the resistor R3 are connected in series between the inverting input terminal and the output terminal of the error amplifier 12, the resistor R4 is connected in parallel with the capacitor C1 and the resistor R3, and the error amplifier 12 amplifies back The difference between the grant signal Vfb and the reference value Vref generates a signal Vcomp for stabilizing the output voltage Vo of the power converter, and the resistors R3, R4 and capacitor C1 are used to compensate the signal Vcomp. In some applications, resistor R4 in Figure 1 can be omitted. Referring to Fig. 2, the gm type compensation circuit 14 includes a transconductance amplifier 16, the resistor R3 and the capacitor C1 are connected in series between the output terminal of the transconductance amplifier 16 and the ground terminal GND, the capacitor C2 is connected in parallel with the resistor R3 and the capacitor C1, and the transconductance amplifier will The difference between the feedback signal Vfb and the reference value Vref is converted into a current Icomp, and the resistor R3 and the capacitors C1 and C2 generate a compensated signal Vcomp according to the current Icomp. Using an external compensation circuit needs to occupy a pin of the control IC. In order to reduce the number of pins, there are more and more solutions to integrate the compensation circuit into the IC, such as US Patent No. 7,504,888. Generally speaking, the gm-type compensation circuit 14 is easier to integrate into an integrated circuit (IC), but these solutions also have many limitations. Generally speaking, the control IC of a high switching frequency DC-to-DC power converter has poles and zeros greater than 10KHz. It is therefore easier to integrate the compensation circuit into the IC. In low-bandwidth applications, such as power factor correction (Power Factor Correction; PFC) power converters or other control ICs or power converters similar to PFC, the compensation circuit 14 requires large capacitors C1 and C2, but due to cost and area constraints Considering that it is difficult to fully integrate the large capacitors C1 and C2 into the IC. More specifically, the input voltage of the PFC power converter is an AC voltage with an AC frequency of 60 Hz, so its control IC requires low gain and low-frequency poles and zeros to achieve a low-bandwidth loop to filter out the AC frequency, so the compensation circuit 14 needs Large capacitors C1 and C2 are used to compensate, so that the signal Vcomp changes slowly, so that the AC frequency can be filtered out. However, the large capacitors C1 and C2 that meet the requirements cannot be realized in the IC, so it is necessary to use a pin to externally connect the large capacitors C1 and C2. If you want to reduce the capacitors C1 and C2 so that they can be integrated into the IC, you need to reduce the current Icomp Down to the nano-ampere level or pico-ampere level, but such a small current is easily affected by the process and cannot be accurately controlled, so it is difficult to achieve.

Since the analog compensation circuit is not easy to integrate, many digital compensation circuits have been proposed, such as US Patent Nos. 7,743,266 and 7,894,218. Although these digital compensation circuits can be integrated in the control IC of the PFC power converter, they usually require complex The digital signal processing (Digital Signal Processing; DSP) algorithm therefore needs to occupy a large chip area, resulting in an increase in cost and chip size. On the other hand, the slow-changing signal Vcomp will cause the power converter to fail to quickly respond to the transient load, resulting in a large voltage drop or overshoot of the output voltage Vo.

Contents of the invention

The object of the present invention is to overcome the deficiencies and defects of the prior art, and propose a hybrid compensation circuit for a power converter.

In order to achieve the above-mentioned purpose, from one point of view, the present invention proposes a hybrid compensation circuit for a power converter, including: a digital signal generator for providing a first pole, and the digital signal generator is based on a feedback signal and a reference A digital signal is generated, wherein the feedback signal is related to the output voltage of the power converter; and a digital-to-analog converter, coupled to the digital signal generator, converts the digital signal into an analog first signal.

In one embodiment, the above-mentioned hybrid compensation circuit may further include: an offset injector coupled to the digital-to-analog converter to provide a zero point, and the offset injector provides a variable offset value to offset The first signal generates a second signal, wherein the variable offset value is determined by the difference between the feedback signal and the reference value.

In one embodiment, the above-mentioned hybrid compensation circuit may further include: a low-pass filter coupled to the digital-to-analog converter to provide a second pole, and the digital-to-analog converter filters high frequencies of the first signal The components generate a second signal.

In one embodiment, the above-mentioned hybrid compensation circuit may further include: an offset injector coupled to the digital-to-analog converter, providing a variable offset value to offset the first signal to generate a second signal, wherein the offset injector may The variable offset value is determined by the difference between the feedback signal and the reference value; and a low-pass filter, coupled to the offset injector, filters out the high-frequency components of the second signal to generate a third signal for the The power converter stabilizes this output voltage.

In one embodiment, the above-mentioned hybrid compensation circuit may further include: a low-pass filter, coupled to the digital-to-analog converter, to filter out high-frequency components of the first signal to generate a second signal; and an offset injector, coupled to the low-pass filter, providing a variable offset value to offset the second signal to generate a third signal for the power converter to stabilize the output voltage, wherein the variable offset value is determined by the feedback signal and the reference The difference between the values is determined.

In one embodiment, the above-mentioned hybrid compensation circuit may further include: an offset injector, coupled to the digital signal generator, providing a variable offset value to offset the digital signal to generate a second signal, wherein the variable The offset value is determined by the difference between the feedback signal and the reference value; and an adder adds the first signal and the second signal to generate a third signal for the power converter to stabilize the output voltage.

In one embodiment, the above-mentioned hybrid compensation circuit may further include: an offset injector, coupled to the digital signal generator, providing a variable offset value to offset the digital signal to generate a second signal, wherein the variable The offset value is determined by the difference between the feedback signal and the reference value; a low-pass filter, coupled to the offset injector, filters out the high-frequency components of the second signal to generate a third signal; and an adder , adding the first signal to the third signal to generate a fourth signal for the power converter to stabilize the output voltage.

In order to achieve the above purpose, from another point of view, the present invention proposes a hybrid compensation circuit for a power converter, including: a digital signal generator, which generates a first and a second digital signal according to an output voltage feedback signal and a reference value, wherein The output voltage grant signal is related to the output voltage of the power converter; the digital offset injector is coupled to the digital signal generator to generate a variable offset value according to the second digital signal; the adder uses the first adding a digital signal to the variable offset value, or adding the first digital signal to a signal related to the variable offset value; and a digital-to-analog converter coupled to the adder, the output of the adder , or the output of the adder is converted to an analog signal.

In an embodiment, the hybrid compensation circuit may further include: a low-pass filter coupled to the digital-to-analog converter for filtering out high-frequency components of the analog signal.

In one embodiment, the hybrid compensation circuit may further include: a digital filter, coupled between the digital offset injector and the adder, for filtering the variable offset value to generate the variable Correlation signal for offset values.

In one embodiment, the hybrid compensation circuit may further include: a digital filter, coupled between the adder and the digital-to-analog converter, for filtering the output of the adder to generate the output of the adder related signals.

In one embodiment, the digital offset injector feedback controls an operating frequency of the digital signal generator.

In order to achieve the above purpose, from another point of view, the present invention proposes a hybrid compensation circuit for a power converter, including: a digital signal generator, which generates a first and a second digital signal according to an output voltage feedback signal and a reference value, wherein The output voltage grant signal is related to the output voltage of the power converter; the digital offset injector is coupled to the digital signal generator to generate a variable offset value according to the second digital signal; the first digital-to-analog converter, coupled to the digital signal generator, to convert the first digital signal into a first analog signal; a second digital-to-analog converter, coupled to the digital offset injector, to convert the variable offset value into a second analog signal and an adder that adds the first analog signal to the second analog signal, or adds a correlation signal of the first analog signal to the second analog signal.

In an embodiment, the hybrid compensation circuit may further include a low-pass filter coupled between the first digital-to-analog converter and the adder, or coupled to an output end of the adder.

In order to achieve the above purpose, from another point of view, the present invention proposes a hybrid compensation circuit for a power converter, including: a digital signal generator, which generates a first digital signal according to an output voltage feedback signal and a reference value, wherein the feedback signal The signal is related to the output voltage of the power converter; the digital filter is coupled to the digital signal generator to filter the first digital signal; and the digital-to-analog converter is coupled to the digital filter to filter the digital filter The output is converted to an analog signal.

In one embodiment, the digital signal generator includes: a successive approximation register analog-to-digital converter (SAR-ADC, Successive Approximation Register Analog to Digital Converter), which generates a signal according to the output voltage feedback signal and the reference value. an up-down signal; and an up-down counting circuit, wherein the output signal of the up-down counting circuit is controlled by the up-down signal to rise or fall correspondingly.

In one embodiment, the digital offset injector generates a number or code corresponding to α·(Vfb1−Vref1), where α is a positive real number, Vfb1 is the output voltage feedback signal, and Vref1 is the reference value.

In one embodiment, the digital filter includes a D flip-flop or a moving average circuit.

Description of drawings

Figure 1 is a traditional EA type compensation circuit;

Fig. 2 is a traditional gm type compensation circuit;

FIG. 3A is an embodiment of a hybrid compensation circuit according to the present invention;

3B-3H are other embodiments of the hybrid compensation circuit according to the present invention;

Fig. 4 is a specific embodiment of the hybrid compensation circuit of Fig. 3A;

Fig. 5 is the current-voltage characteristic curve of the transconductance amplifier of Fig. 2;

FIG. 6 is a characteristic curve of the voltage change rate dVa1/dt of the first signal Va1 of FIG. 4 versus the voltage Vref1-Vfb1;

Fig. 7 is another specific embodiment of the hybrid compensation circuit of Fig. 3A;

FIG. 8 is a timing diagram of the frequency signal and the pulse signal of FIG. 7;

FIG. 9 is a characteristic curve of the voltage change rate dVa1/dt of the first signal Va1 of FIG. 7 versus the voltage Vref1-Vfb1;

Fig. 10 is another specific embodiment of the hybrid compensation circuit of Fig. 3A;

Fig. 11 is the output voltage and signal Vcomp of the power converter produced by using the gm type analog compensation circuit of Fig. 2 and the hybrid compensation circuit of the present invention;

12A-12G are several other specific embodiments of the hybrid compensation circuit;

Fig. 13 is a specific embodiment of digital signal generator 122;

14A-14D are successive approximation registers (SAR, Successive Approximation Register) analog-to-digital converter (ADC, Analog to Digital Converter) 132, referred to as several specific embodiments of SAR-ADC;

Fig. 15 is a specific embodiment of up and down counting circuit 134;

16A-16I are several specific embodiments of the digital offset injector 126;

Two specific embodiments of the digital filter 128 are shown in FIGS. 17A-17B .

Description of symbols in the figure

10 EA type compensation circuit

12 Error Amplifier

14 gm type compensation circuit

16 transduction amplifier

20,20a-20g hybrid compensation circuit

22 Digital signal generator

24 Digital to Analog Converter

26 Offset Injector

28 Low-pass filter

29 Adder

30 comparators

32 Inverter

34 Hysteresis comparator

36 Hysteresis comparator

38 Operational transconductance amplifier

40 Oscillators

42 Controller

44 Up and down counter

46 Current Source

48 Current Source

50 Current Source

52 Current source

54 The first end of the resistor Rof

56 The second end of the resistor Rof

60 multitasker

62 Comparators

64 Pulse generator

70 Comparator

72 Comparator

74 Comparator

76 comparator

78 Comparator

80 Controller

82 frequency divider

84 Frequency divider

86 frequency divider

88 frequency divider

90 Operational Amplifier

92 Output voltage of power converter

94 Output voltage of power converter

96 feedback signal

98 feedback signal

120,120a～120f hybrid compensation circuit

122 Digital signal generator

123 adder

124,124a DAC

126 Digital Offset Injector

128 digital filter

129 LPF

132 SAR-ADC

134 Up and down counting circuit

136 OSC

141 Error Amplifier

142～144 Comparator

146 Controller and digital generator

148 DAC

152 Controller

154 up and down counter

162 Adder/subtractor

164 Digital Multiplier

166 frequency division circuit

168 DAC

Detailed ways

Referring to FIG. 3 , the hybrid compensation circuit 20 according to the present invention can be applied to various types of power converters, such as DC-DC power converters and PFC power converters. In the hybrid compensation circuit 20, the digital signal generator 22 generates the digital signal Sd according to the feedback signal Vfb1 and the reference value Vref1 related to the output voltage of the power converter, and the digital-to-analog converter (Digital-to-Analog Converter; DAC) 24 converts the digital signal Sd into an analog first signal Va1, an offset injector (offset injector) 26 provides a variable offset value to offset the first signal Va1 to generate a second signal Va2, and a low pass filter (Low Pass Filter; The LPF 28 filters the high-frequency components of the second signal Va2 to generate a third signal Vcomp for stabilizing the output voltage of the power converter. The hybrid compensation circuit 20 simulates the gm compensation circuit 14 shown in FIG. 2 . As we all know, the gm type compensation circuit 14 provides two poles and one zero, and the hybrid compensation circuit 20 can also provide two poles and one zero. In detail, the digital signal generator 22 and DAC24 can be regarded as the first pole generator/ The compensator is used to provide the first pole, the offset injector 26 can be regarded as a zero generator/compensator to provide a zero point, and the LPF 28 can be regarded as a second pole generator/compensator to provide a second pole.

It should be noted that according to the present invention, it is not absolutely necessary to generate/compensate two poles and one zero, that is, the number of generated/compensated poles and zeros can be changed. For example, in some applications it is possible to generate/compensate only one pole, or one pole and one zero, or two poles. 3B-3D illustrate examples of hybrid compensation circuits 20a-20c suitable for these applications. In addition, in the embodiment of generating/compensating two poles and one zero, the LPF 28 does not have to be arranged behind the offset injector 26 and connected in series with the digital signal generator 22 and the DAC 24 , but can be connected in other forms. For example, FIG. 3E shows an embodiment in which the LPF 28 is arranged in front of the offset injector 26; in the embodiment of FIG. 3F, the offset injector 26 and the LPF 28 are arranged on another path to provide a compensation of a zero point and a second pole , and the adder 29 adds the output of the DAC24 to the compensation signal generated by the other path; FIG. 3G shows an embodiment similar to that of FIG. 3F, but the LPF28 is omitted. In addition to the above arrangement, the LPF 28 can also be arranged in other positions, for example but not limited to the embodiment in FIG. 3H , the LPF 28 is arranged behind the adder 29 .

FIG. 4 is a specific embodiment of the hybrid compensation circuit 20 . To achieve the first pole at low frequencies, the transconductance amplifier 16 of the gm-type compensation circuit 14 is simulated using a digital signal generator 22 and a DAC 24 . The digital signal generator 22 in FIG. 4 includes a comparator 30 that compares the feedback signal Vfb1 and the reference value Vref1 to generate a comparison signal Sc1. The inverter 32 inverts the comparison signal Sc1 to generate a signal Sc2 to the controller 42. The oscillator 40 provides a frequency signal. Clk is sent to the controller 42 and the up-down counter 44. The controller 42 samples the signal Sc2 in response to the frequency signal Clk. When the sampling result indicates that the feedback signal Vfb1 is greater than the reference value Vref1, the controller 42 sends a control signal Down to the up-down counter 44 to lower One bit of the digital signal Sd is used to lower the output power of the power converter. When the sampling result indicates that the feedback signal Vfb1 is lower than the reference value Vref1, the controller 42 sends a control signal Up to the up-down counter 44 to up-up the digital signal Sd by one bit, and then up-up the output power of the power converter. The up-down counter 44 samples the control signals Up and Down output by the controller 42 according to the frequency signal Clk to adjust the digital signal Sd. DAC24 converts digital signal Sd into first signal Va1. DAC24 is a fairly common circuit, and its internal circuit and operation will not be repeated here. When the frequency signal Clk is low frequency, the sampling frequency is low, and the change of the digital signal Sd is relatively slow, resulting in the slow change of the third signal Vcomp output by the hybrid compensation circuit 20. This effect is similar to the gm type compensation circuit 14 using a large capacitor C1 and Same as C2.

When the power converter loads instantaneously, if the third signal Vcomp output by the hybrid compensation circuit 20 still changes slowly, it will not be able to respond quickly, resulting in a large voltage drop or overshoot of the output voltage Vo. In order to improve this problem, the digital signal generator 22 in FIG. 4 also includes a hysteresis comparator 34 to compare the feedback signal Vfb1 and the threshold value VH1 to generate a comparison signal SH to the controller 42. The hysteresis comparator 36 compares the feedback signal Vfb1 and the threshold value The value VL1 generates a comparison signal SL to the controller 42, and the operational transconductance amplifier 38 amplifies the difference ΔV between the feedback signal Vfb1 and the reference value Vref1 to generate a frequency adjustment signal Sfm to the oscillator 40 to adjust the frequency of the frequency signal Clk. When the difference ΔV between the feedback signal Vfb1 and the reference value Vref1 increases, the frequency adjustment signal Sfm will increase the frequency of the frequency signal Clk to speed up the sampling frequency, thereby speeding up the change of the digital signal Sd and the twisting of the third signal Vcomp rate (slew rate), when the feedback signal Vfb1 is greater than the critical value VH1 or less than the critical value VL1, the hysteresis comparator 34 or 36 sends a comparison signal SL or SH to the oscillator 40, so that the frequency of the frequency signal Clk rises to the maximum value, and then the digital signal Sd is adjusted up or down with the maximum frequency. In addition, when the feedback signal Vfb1 is greater than the critical value VH1, the controller 42 also sends a control signal Down_limit to the up-down counter 44 according to the comparison signal SL, so that the up-down counter 44 lowers the digital signal Sd to the minimum value at the maximum frequency to increase the second limit. The torsional rate of the three-signal Vcomp reduces the output power of the power converter rapidly, and the output voltage drops rapidly to a preset level. Similarly, when the feedback signal Vfb1 is less than the critical value VL1, the controller 42 sends a control signal Up_limit to the up-down counter 44 according to the comparison signal SH, so that the up-down counter 44 raises the digital signal Sd to the maximum value at the maximum frequency, thereby increasing The torsion rate of the third signal Vcomp increases the output power of the power converter, so that the output voltage rapidly rises to a preset level. In other embodiments, when the feedback signal VFB1 is greater than or less than the critical value VH1 or VL1 , the up-down counter 44 can immediately increase the digital signal Sd to the minimum value or the maximum value. When the load moment occurs, the difference ΔV between the feedback signal Vfb1 and the reference value Vref1 increases, so the sampling frequency of the controller 42 and the up-down counter 44 is accelerated, so the slew rate (slew rate) of the third signal Vcomp is accelerated, and When the feedback signal Vfb1 is larger than the critical value VH1 or smaller than the critical value VL1, the digital signal Sd can drop to the minimum value or rise to the maximum value immediately or at the fastest frequency, thereby effectively improving the load transient response of the power converter.

The current-voltage characteristic curve of the transconductance amplifier 16 of Fig. 2 is as shown in Fig. 5, can obtain from Fig. 2

Ce×Vcomp=Icomp×T, Formula 1

Where Ce is the equivalent capacitance of the capacitors C1 and C2, and T is the time for generating the current Icomp. It can be further deduced from formula 1 that

Icomp/Ce=Vcomp/T, Formula 2

From Formula 2, it can be seen that the current Icomp and the capacitance Ce determine a voltage change rate dVcomp/dt, and the capacitance Ce is a constant value, so the current Icomp is proportional to the voltage change rate dVcomp/dt, so the Y-axis in Figure 5 can also be regarded as the voltage change rate dVcomp/dt. The digital signal generator 22 of Fig. 3 A and DAC24 analog transconductance amplifier 16 also can obtain similar voltage change rate, for example Fig. 6 is the voltage change rate dVa1/dt (that is torsion rate) of the first signal Va1 of DAC24 of Fig. 4 vs. The characteristic curve of the input voltage Vfb1 of the digital signal generator 22 is the same as the curve in FIG. 5 between the critical values VL1 and VH1, and there is a hysteresis region at both ends. When the feedback signal Vfb1 rises above the critical value VH1 , the digital signal Sd is lowered at the fastest sampling frequency, so the first signal Va1 has the fastest negative voltage change rate -dVa1/dt_max, until the feedback signal Vfb1 drops below the hysteresis critical value Vhy1, the first signal Va1 The voltage change rate dVa1/dt returns to the original level; similarly, when the feedback signal Vfb1 drops below the critical value VL1, the digital signal Sd is raised at the frequency of the fastest frequency signal Clk, so the first signal Va1 has The fastest forward voltage change rate dVa1/dt_max, until the feedback signal Vfb1 rises above the hysteresis critical value Vhy2, the voltage change rate dVa1/dt of the first signal Va1 returns to the original level.

In the embodiment of FIG. 4 , the offset injector 26 includes a current source 46 and a switch M1 connected in series between the power supply terminal Vcc and the first end 54 of the resistor Rof, and the current source 48 and the switch M2 are connected in series with the first end of the resistor Rof Between 54 and the ground terminal GND, the current source 50 and the switch M3 are connected in series between the power supply terminal Vcc and the second terminal 56 of the resistor Rof, and the current source 52 and the switch M4 are connected in series between the second terminal 56 of the resistor Rof and the ground terminal GND. between. The switches M1 and M4 are controlled by the control signal Down from the controller 42, the switches M2 and M3 are controlled by the control signal Up from the controller 42, and the current Iof on the resistor Rof can be determined by controlling the switches M1, M2, M3 and M4 direction. The current sources 46 , 48 , 50 and 52 determine the magnitude of the current Iof according to the frequency adjustment signal Sfm from the operational transconductance amplifier 38 , and then determine the variable offset value Vof to offset the first signal Va1 to generate the second signal Va2 . Since the frequency adjustment signal Sfm is related to the difference ΔV between the feedback signal Vfb1 and the reference value Vref1 , the variable offset Vof also varies with the difference ΔV. In other embodiments, the current sources 46 , 48 , 50 and 52 can also be changed to determine the current Iof according to other signals related to the difference ΔV. The low-pass filter 28 in FIG. 4 includes an RC filter composed of a resistor Rf and a capacitor Cf, and filters the second signal Va2 to generate a third signal Vcomp. From the point of view of the physical meaning of the control loop, the zero point of the gm compensation circuit 14 is used as a phase lead (phase lead) compensation, while the second pole is similar to a low-pass filter, so the hybrid compensation circuit 20 of the present invention utilizes an offset injector 26 An instantaneous voltage change is provided to simulate the effect of the zero point, and an RC filter is used to realize the second pole.

FIG. 7 is another specific embodiment of the hybrid compensation circuit 20 in FIG. 3A. The digital signal generator 22 includes a multiplexer 60 to sequentially convert the threshold value VH1, threshold value VH2, reference value Vref1, threshold The value VL2 and the critical value VL1 are provided to the non-inverting input terminal of the comparator 62, wherein VH1>VH2>Vref1>VL2>VL1, the inverting input terminal of the comparator 62 receives the feedback signal Vfb1, and the comparator 62 will feedback the signal Vfb1 respectively compares the critical values VH1, VH2, VL1 and VL2 with the reference value Vref1, and sends the comparison signal to the controller 42, and the controller 42 samples the comparison signal output by the comparator 62 according to the frequency signal Clk and pulse signals Sp1-Sp5 , so as to determine whether the control signal Up or Down is given to the up-down counter 44 to raise or lower the digital signal Sd, and the controller 42 also judges whether the feedback signal Vfb1 is greater than the maximum critical value VH1 or smaller than the minimum critical value VL1 according to the comparison result, If the feedback signal Vfb1 is greater than the critical value VH1, the controller 42 sends the control signal Down_limit to make the up-down counter 44 reduce the digital signal Sd to the minimum value immediately or at the maximum frequency to increase the torsion rate of the third signal Vcomp. If the feedback signal When Vfb1 is smaller than the threshold value VL1, the controller 42 sends a control signal Up_limit to make the up-down counter 44 raise the digital signal Sd to a maximum value immediately or at a maximum frequency to increase the torsion rate of the third signal Vcomp. The controller 42 also determines the frequency adjustment signal Sfm to the oscillator 40 to adjust the frequency of the frequency signal Clk according to the comparison result. When the difference between the feedback signal Vfb1 and the reference value Vref1 is larger, the frequency of the frequency signal Clk is higher. By increasing the torsion rate of the third signal Vcomp, the load transient response is improved. When the feedback signal Vfb1 is larger than the critical value VH1 or smaller than the critical value VL1 , the frequency adjustment signal Sfm will increase the frequency of the frequency signal Clk to a maximum value to speed up the sampling frequency of the controller 42 and the up-down counter 44 . The pulse generator 64 generates pulse signals Sp1-Sp5 according to the frequency signal Clk, as shown in FIG.

The offset injector 26 in FIG. 7 changes the resistor Rof in FIG. 4 into a variable resistor controlled by a switch, and its resistance value changes with the difference ΔV between the feedback signal Vfb1 and the reference value Vref1, and the current sources 46 and 48 , 50 and 52 provide fixed current, so the current Iof passing through the variable resistor Rof is a constant value. In this implementation, the variable resistor Rof includes three series connected resistors Ra, Rb and Rc, each resistor Ra, Rb and Rc are connected in parallel with the switches Ma, Mb and Mc, and the signals Sa, Sb and Sc controls the switches Ma, Mb and Mc respectively to adjust the resistance of the variable resistor Rof, and then generates a variable offset value Vof varying with the difference ΔV to offset the first signal Va1 to generate the second signal Va2.

FIG. 9 is a characteristic curve of the voltage change rate dVa1/dt of the first signal Val of the DAC24 of FIG. 7 versus the input voltage Vfb1 of the digital signal generator 22. When the feedback signal Vfb1 rises above the critical value VH1, the digital signal Sd is The fastest frequency is lowered, so the first signal Va1 has the fastest negative voltage change rate -dVa1/dt_max, until the feedback signal Vfb1 drops below the critical value VH2, the voltage change rate of the first signal Va1 returns to the original Similarly, when the feedback signal Vfb1 drops below the critical value VL1, the digital signal Sd is raised at the fastest frequency, so the first signal Va1 has the fastest forward voltage change rate dVa1/dt_max, until the feedback signal When Vfb1 rises to be greater than the hysteresis critical value VL2, the change speed of the first signal Va1 returns to the original level. In the embodiment of FIG. 7 , as the number of set critical values increases, the characteristic curve in FIG. 9 will approach the characteristic curve in FIG. 6 .

FIG. 10 is another specific embodiment of the hybrid compensation circuit 20 shown in FIG. 3A. The digital signal generator 22 includes a comparator 70 for comparing the feedback signal Vfb1 and the threshold value VH1 to generate a comparison signal SB1. The comparator 72 compares the feedback signal Vfb1 and the threshold value VH1. The threshold VH2 generates a comparison signal SB2, the comparator 74 compares the feedback signal Vfb1 and the reference value Vref1 to generate a comparison signal SB3, the comparator 76 compares the feedback signal Vfb1 and the threshold VL2 to generate a comparison signal SB4, and the comparator 78 compares the feedback signal Vfb1 and the critical value VL1 to generate a comparison signal SB5, the controller 80 selects one of the frequency signals Clk1, Clk2, Clk3, Clk4 and Clk5 as the frequency Clk to the up-down counter 44 according to the comparison signals SB1, SB2, SB3, SB4 and SB5. When the grant signal Vfb1 is greater than the maximum critical value VH1 or less than the minimum critical value VL1, the controller 80 selects the frequency signal Clk1 with the highest frequency to the up-down counter 44, and the up-down counter 44 samples the comparison signal SB3 in response to the frequency signal Clk, and according to the sampling result To increase or decrease the digital signal Sd by one bit, when the feedback signal Vfb1 is greater than the maximum critical value VH1 or less than the minimum critical value VL1, the up-down counter 44 adjusts the digital signal Sd immediately or at the maximum frequency in response to the comparison signal SB1 or SB5. Reduce to the minimum value or increase to the maximum value to increase the torsion rate of the third signal Vcomp, the oscillator 40 provides the frequency signal Clk1 with the frequency f, the frequency divider 82 divides the frequency signal Clk1 to generate the frequency signal Clk1 with the frequency f/2 Frequency signal Clk2, frequency divider 84 divides frequency signal Clk2 to generate frequency signal Clk3 with frequency f/4, frequency divider 86 generates frequency signal Clk4 with frequency f/8 to frequency signal Clk3 division, frequency divider 88 Dividing the frequency signal Clk4 generates a frequency signal Clk5 having a frequency f/16. In this hybrid compensation circuit, the characteristic curve of the voltage change rate dVa1/dt of the first signal Va1 of the DAC 24 versus the input voltage Vfb1 of the digital signal generator 22 is shown in FIG. 9 .

The LPF28 of FIG. 10 includes a low-bandwidth operational amplifier 90 with an inverting input terminal receiving the second signal Va2 from the offset injector 26, and a non-inverting input terminal connected to the output terminal Vcomp of the LPF28. The resistor R5 and the compensation capacitor C3 are connected in series. Between the output terminal of the operational amplifier 90 and the output terminal Vcomp of the LPF28, in order to stabilize the third signal Vcomp, the transistor M5 is connected between the power supply terminal Vcc and the output terminal Vcomp of the LPF28, and the gate of the transistor M5 is connected to the output of the operational amplifier 90 The resistor R6 is connected between the output terminal Vcomp of the LPF28 and the ground terminal GND.

It should be noted that although Figures 4, 7, and 10 illustrate several specific embodiments according to the hybrid compensation circuit 20 in Figure 3A, obviously the hybrid compensation circuits 20a-20g shown in Figures 3B-3H can also be The circuits shown in Figs. 4, 7, and 10 are used to form components, so the circuits shown in Figs. 3B-3H can also be implemented in practice, and the details will not be repeated here.

Fig. 11 shows the effectiveness of the present invention. The output voltage Vo and signal Vcomp of the power converter generated by the gm type analog compensation circuit 14 of Fig. 2 are shown in waveforms 92 and 96 respectively, and are generated by the hybrid compensation circuit 20 of the present invention. The output voltage Vo of the power converter and the third signal Vcomp are respectively shown as waveforms 94 and 98, which are almost the same as the effect of using the gm-type analog compensation circuit 14, and when the instantaneous load shown at time t1 occurs, there is also Good transient response, so the hybrid compensation circuit 20 can indeed replace the traditional analog compensation circuit 14 . The hybrid compensation circuit 20 can reduce the frequency of the frequency signal Clk to achieve the effect of the large capacitors C1 and C2 in the analog compensation circuit 14 to stabilize the signal Vcomp, so the hybrid compensation circuit 20 does not need to use the large capacitors C1 and C2, and can be easily integrated into control IC to reduce pin count. The hybrid compensation circuit 20 is a hybrid analog circuit and digital circuit, so compared to the digital compensation circuit, the hybrid compensation circuit 20 is simpler, so it takes up less chip area, and does not need to use complex DSP algorithms, which can simplify design and cut costs.

FIG. 12A shows a hybrid compensation circuit 120 of another embodiment of the present invention; FIGS. 12B-12G show hybrid compensation circuits 120a-120f of several other embodiments of the present invention, and these circuits illustrate changes of the hybrid compensation circuit 120. form.

12A, the hybrid compensation circuit 120 includes a digital signal generator 122, an adder 123, a digital-to-analog converter (DAC) 124, a digital offset injector 126, and a digital filter 128, wherein the digital signal generator 122 is visible is a first pole generator/compensator for providing a first pole, the digital offset injector 126 may be regarded as a zero generator/compensator for providing a zero, and the digital filter 128 may be regarded as a second pole generator / compensator to provide the second pole. The difference between this embodiment and the embodiment in FIG. 3A includes: the zero point generator/compensator and the second pole generator/compensator are implemented by digital circuits and are arranged in front of the DAC 124 . However, this embodiment is only an example; the zero point generator/compensator and the second pole generator/compensator do not have to be implemented by digital circuits, but can be implemented by only one of the digital circuits, such as but not limited to Change the second pole generator/compensator to an analog low-pass filter. As shown in FIG. 12B, the digital filter 128 in FIG. 12A is replaced with an LPF129.

Returning to FIG. 12A , the digital signal generator 122 generates the digital signal Sd according to the reference value Vref1 and the feedback signal Vfb1 related to the output voltage of the power converter. The digital offset injector 126 generates a variable offset value according to another output signal Sfd output by the digital signal generator 122, which will be described later. The digital filter 128 filters the output signal So (variable offset value) of the digital offset injector 126 to generate a filtered offset value Sfo, and the filtered offset value Sfo is a correlation signal of the output signal So. The adder 123 adds the digital signal Sd and the filtered offset value Sfo to generate a digital signal Sd1, and the DAC 124 converts the digital signal Sd1 into a signal Vcomp.

It should be noted that according to the present invention, it is not absolutely necessary to generate/compensate two poles and one zero, that is, the number of generated/compensated poles and zeros can be changed. For example, in some applications it is possible to generate/compensate only one pole, or one pole and one zero, or two poles. When only one pole and one zero need to be generated/compensated, the digital filter 128 can be omitted, which would be the circuit of Fig. 12C. When only two poles need to be generated/compensated, adder 123 and digital offset injector 126 can be omitted, which will become the circuit of FIG. 12D. In addition, please note that the position of the digital filter 128 is not limited to that shown in FIG. 12A; for example, the digital filter 128 can be located behind the adder 123, as shown in FIG. signal, so the signal Sfd1 can be regarded as a related signal of the signal Sd1).

In addition to the above arrangements, of course, the addition of all digital signals can also be converted into analog signals and then added, for example, but not limited to, as shown in Figures 12F and 12G, the output signal Sd of the digital signal generator 122 and the output signal So of the digital offset injector 126 are respectively converted into analog signals by DAC124, 124a and then added; the difference between Fig. 12F and 12G is the position of LPF129 (in the embodiment of Fig. 12F, the output signal of LPF129 is the output signal of DAC124 The filtered signal of the signal can be regarded as the related signal of the DAC124 output signal).

FIG. 13 shows a specific embodiment of the digital signal generator 122 . As shown in the figure, in this embodiment, the digital signal generator 122 includes a successive approximation register (SAR, Successive Approximation Register) analog-to-digital converter (ADC, Analog to Digital Converter) 132, referred to as SAR-ADC, and a Up and down counting circuit 134. The SAR-ADC132 generates a rising and falling signal U/D according to the feedback signal Vfb1 and the reference value Vref1. The up-down signal U/D controls the up-down counting circuit 134 so that the output signal of the up-down counting circuit 134 (ie, the digital signal Sd) rises or falls correspondingly. The up and down counting circuit 134 operates according to the frequency signal CLK. In the embodiment of FIGS. 12A-12C and 12E, preferably but not necessarily, the digital offset injector 126 can selectively feed back the frequency of the control frequency signal CLK, for example, the frequency signal can be generated by the digital offset injector 126 CLK; or an oscillator (not shown) in the digital signal generator 122 generates the frequency signal CLK, and the digital offset injector 126 sends a signal to control the oscillator.

SAR-ADC 132 additionally generates an output signal Sfb. The output signal Sfb is a digital signal corresponding to the feedback signal Vfb1, or a digital signal corresponding to the difference between the feedback signal Vfb1 and the reference value Vr _e f1, which will be described in detail later.

14A-14D show several specific embodiments of SAR-ADC 132. In the embodiment of FIG. 14A , the reference value Vref1 is a digital signal, and the SAR-ADC 132 includes a comparator 144 , a controller and digital generator 146 , and a DAC 148 . The comparator 144 compares the feedback signal Vfb1 with the analog feedback signal generated by the DAC148; in response to the output signal of the comparator 144, the controller and the digital generator 146 generate an N-bit digital code (N is a positive integer), And transmit it to DAC148, and the analog feedback signal generated by DAC148 corresponds to this N-bit digital code. The N-bit digital code generated in this way is a digital signal that is related to the feedback signal Vfb1 and gradually approaches, so the circuit is called SAR-ADC. The controller and the digital generator 146 generate a digital signal Sfb in addition, and this digital signal Sfb can be the same as or different from the aforementioned N-bit digital encoding, that is, the digital signal Sfb can be N-bit or other arbitrary digits, and can be Use the same or different representation format as the N-digit code. In one embodiment, the digital signal Sfb also corresponds to the feedback signal Vfb1, or can be regarded as a digital representation of the feedback signal Vfb1. Through the feedback loop formed by the comparator 144 , the controller and digital generator 146 , and the DAC 148 , the digital signal Sfb can gradually approach to accurately represent the feedback signal Vfb1 in digital form. In addition, the controller and digital generator 146 further receives the reference value Vref1, and generates the up-down signal U/D according to the comparison result between the feedback signal Vfb1 and the reference value Vref1. In detail, since the reference value Vref1 is a digital signal, and both the N-bit digital code and the digital signal Sfb are digital representations of the feedback signal Vfb1, the above "comparison between the feedback signal Vfb1 and the reference value Vref1" can refer to The value Vref1 is digitally compared, eg subtracted, with either the N-bit digital code or the digital signal Sfb. When the feedback signal Vfb1 is greater than the reference value Vref1, that is, when the N-bit digital code or the digital signal Sfb is greater than the reference value Vref1, the up-down signal U/D instructs the up-down counting circuit 134 to increase the digital signal Sd (for example, increase the number 1). When the feedback signal Vfb1 is smaller than the reference value Vref1, that is, when the N-bit digital code or the digital signal Sfb is smaller than the reference value Vref1, the up-down signal U/D instructs the up-down counting circuit 134 to decrease the bit signal Sd (for example, decrease the number 1).

In another embodiment, the digital signal Sfb corresponds to the difference between the feedback signal Vfb1 and the reference value Vref1 , and can be regarded as a digital representation of the difference between the feedback signal Vfb1 and the reference value Vref1 . Similarly, since the reference value Vref1 is a digital signal, and the N-digit number is coded as a digital representation of the feedback signal Vfb1, the above-mentioned "difference between the feedback signal Vfb1 and the reference value Vref1" can convert the reference value Vref1 to the N-digit number Encodings are compared numerically, eg subtracted. Alternatively, the digital signal Sfb can be a digital code of the difference. Other parts of the circuit are similar to the aforementioned embodiment of "the digital signal Sfb corresponds to the feedback signal Vfb1".

In the embodiment of FIG. 14B , the reference value Vref1 is a digital signal, which is input to the DAC148 as an initial digital signal. Similarly, the digital signal Sfb may correspond to the feedback signal Vfb1 or the difference between the feedback signal Vfb1 and the reference value Vref1 (that is, the digital signal Sfb may be a digital representation of the feedback signal Vfb1 or the difference between the feedback signal Vfb1 and the reference value Numerical representation of the difference between Vref1). The rest of the circuit is similar to the Fig. 14A embodiment.

In the embodiment of FIG. 14C , the reference value Vref1 is an analog signal, and the SAR-ADC 132 includes an error amplifier 141 , a comparator 142 , a controller and digital generator 146 , and a DAC 148 . The error amplifier 141 compares the feedback signal Vfb1 with the reference value Vref1 to generate an error amplification signal. The comparator 142, the controller and digital generator 146 and the DAC 148 constitute a SAR, and its operation is similar to the embodiment of FIG. 14A, but the digital signal Sfb is a digital representation of the difference between the feedback signal Vfb1 and the reference value Vref1.

In the embodiment of FIG. 14D , the reference value Vref1 is an analog signal, and the SAR-ADC 132 includes two comparators 143 and 144 , a controller and digital generator 146 , and a DAC 148 . The comparator 143 compares the analog feedback signal generated by the DAC 148 with the reference value Vref1 , and inputs the comparison result to the controller and digital generator 146 . This embodiment is similar to the embodiment of FIG. 14A , but the controller and digital generator 146 receives the output signal of the comparator 143 instead of the digital reference value Vref1.

FIG. 15 shows an embodiment of the up and down counting circuit 134 . The up-down counting circuit 134 includes a controller 152 and a up-down counter 154 . The controller 152 is controlled by the up-down signal U/D, and operates at a frequency determined by the frequency signal CLK. The relationship between the controller 152 and the up-and-down counter 154 is similar to the relationship between the controller 42 and the up-and-down counter 44 , so it will not be repeated here.

One embodiment of digital offset injector 126 is shown in FIG. 16A . As mentioned above, the function of the digital offset injector 126 is to provide a variable offset value as a zero point generator/compensator, and the variable offset value is related to the difference between the feedback signal Vfb1 and the reference value Vref1 . According to the above, the digital offset injector 126 can be implemented in various ways, as long as it can generate a number or code corresponding to α·(Vfb1-Vref1), or generate a digital representation of α·(Vfb1-Vref1), Wherein α is a positive real number, representing a proportional constant, which corresponds to the transconductance coefficient of the transconductance amplifier 16 multiplied by the resistance value of the resistor R3 in the analog circuit shown in FIG. 2 . As shown in FIG. 16A , in one embodiment, the digital offset injector 126 can be implemented as a digital multiplier, which multiplies the digital signal Sfb by a factor β to generate a variable offset value So, where β is a positive real number. (Or, if the factor β is a positive real number less than 1, the digital multiplier can also be a digital divider, which divides the digital signal Sfb by (1/β).) In this embodiment, the digital signal Sfb corresponds to the feedback signal The difference between Vfb1 and the reference value Vref1 may be a digital representation of the difference between the feedback signal Vfb1 and the reference value Vref1. The factor β can be given by the designer of the hybrid compensation circuit. The variable offset value So output by the digital multiplier is equal to β·Sfb, corresponding to α·(Vfb1-Vref1).

In the embodiment of FIG. 16B , the digital signal Sfb corresponds to the feedback signal Vfb1 or is a digital representation of the feedback signal Vfb1 , and the digital offset injector 126 includes an adder/subtractor 162 and a digital multiplier 164 . The adder/subtractor 162 subtracts the digital signal Sref1 (or adds the negative value of the digital signal Sref1 ) from the digital signal Sfb, wherein the digital signal Sref1 corresponds to the reference value Vref1 , or is a digital representation of the reference value Vref1 . The digital multiplier 164 multiplies the difference between the digital signal Sfb and the digital signal Sref1 by a factor β. The variable offset value So output by the digital multiplier 164 is equal to β·(Sfb-Sref1), corresponding to α·(Vfb1-Vref1).

In addition to the above embodiments, the digital offset injector 126 also has multiple other implementations; for example, the digital offset injector 126 can be implemented as a memory, in which multiple addresses are pre-stored with multiple offset values, and The digital signal Sfb can represent the address of the memory, or be used to determine the address of the memory, as shown in FIG. 16C . The digital signal Sfb may correspond to the feedback signal Vfb1, or correspond to the difference between the feedback signal Vfb1 and the reference value Vref1.

Three additional embodiments of the digital offset injector 126 are shown in FIGS. 16D-16F . Referring to FIG. 16D , in this embodiment, the digital offset injector 126 includes a digital multiplier 164 and a frequency dividing circuit 166 . Digital multiplier 164 operates in a similar manner to the Figure 16A embodiment. Frequency divider circuit 166 receives frequency signal CLK_132, which is the frequency at which SAR-ADC 132 operates (eg, the frequency signal at which DAC 148 in SAR-ADC 132 operates). The frequency dividing circuit 166 divides the frequency signal CLK_132 to generate a divided frequency signal CLK. The generated frequency signal CLK can have different frequencies f1, f2, . . . depending on the value of the digital signal Sfb. That is, the frequency of the clock signal CLK is determined by the digital signal Sfb. The frequency signal CLK is sent to the up-down counting circuit 134 (refer to FIGS. 12A-12C , FIG. 12E , FIG. 13 and FIG. 15 ), so that the controller 152 operates according to the frequency signal CLK. In this way, the digital offset injector 126 can adjust the operating frequency of the up-down counting circuit 134 to achieve a function similar to that provided by the capacitor C1 in FIG. 2 .

FIG. 16E and FIG. 16F are respectively corresponding to FIG. 16B and FIG. 16C , the difference is that the digital offset injector 126 further includes a frequency division circuit 166 to generate a frequency-divided frequency signal CLK. The frequency division circuit 166 operates in a similar manner to the embodiment of FIG. 16D. Please note that in the embodiment of FIG. 16E, in addition to dividing the frequency signal CLK_132 according to the digital signal Sfb, another way (not shown, refer to FIG. 16H) is that the frequency dividing circuit 166 can also divide the frequency signal according to the addition/subtraction The output of the device 162 is used to divide the frequency signal CLK_132. In the latter method, because the digital signal Sref1 corresponds to the reference value Vref1 and the reference value Vref1 is a known signal, the frequency of the clock signal CLK is still determined by the digital signal Sfb.

Three additional embodiments of the digital offset injector 126 are shown in FIGS. 16G-16I. Referring to FIG. 16G , in this embodiment, the digital offset injector 126 includes a digital multiplier 164 and a DAC 168 . Digital multiplier 164 operates in a similar manner to the Figure 16A embodiment. DAC168 converts the digital signal Sfb into an analog signal, which can be a current or voltage signal. In addition, the digital signal generator 122 also includes an oscillator (OSC) 136, which can be a current-controlled or voltage-controlled oscillator, depending on whether the DAC 168 generates a current or voltage signal. The signal generated by the DAC168 controls the OSC136 to determine the frequency of the frequency signal CLK generated by the OSC136. The frequency signal CLK is the frequency on which the up-down counting circuit 134 operates. In this manner, the digital offset injector 126 can also adjust the operating frequency of the up-down counting circuit 134 to achieve a function similar to that provided by the capacitor C1 in FIG. 2 .

FIG. 16H and FIG. 16I correspond to FIG. 16B and FIG. 16C respectively, the difference is that the digital offset injector 126 further includes a DAC168, and the digital signal generator 122 further includes an OSC136. DAC 168 and OSC 136 operate in a similar manner to the embodiment of Figure 16G. Please note that in the embodiment of FIG. 16H , DAC 168 converts the output of adder/subtractor 162 into an analog signal to control OSC 136 . In another embodiment, the DAC 168 can convert the digital signal Sfb to an analog signal to control the OSC 136 .

Two embodiments of the digital filter 128 are shown in FIGS. 17A and 17B . Referring to Figure 17A, in a simpler form, digital filter 128 can be implemented as a D flip-flop. Taking the embodiment of FIG. 12E as an example, the digital filter 128 is connected between the adder 123 and the DAC 124 to receive the digital signal Sd1 to generate a filtered digital signal Sfd1. In this embodiment, the digital signal Sd1 can be input The D flip-flop. D The flip-flop operates according to the frequency signal CLK_128, the frequency of the frequency signal CLK_128 is lower than the frequency signal CLK_132 (the frequency on which the SAR-ADC132 operates), and preferably lower than the frequency signal CLK (the frequency on which the up-and-down counting circuit 134 operates) Frequency of). It should be noted that the number 128 has nothing to do with the actual ratio of 132 and frequency; the purpose of these numerical annotations is only to facilitate comparison of which circuit uses the frequency signal. Since the operating frequency of the D flip-flop is relatively slow, it can provide a function similar to that provided by the capacitor C1 in FIG. 2 .

Referring to Figure 17B, in a more complex form, digital filter 128 may be implemented as a moving average circuit. Also taking the embodiment of FIG. 12E as an example, the moving average circuit receives the digital signal Sd1 and generates a filtered digital signal Sfd1 according to the moving average calculation. There are many ways to calculate the moving average, all of which can be used, one example is as follows:

Sfd1 _t =sum _t /n=(sum _(t-1) -Sfd1 _(t-1) +Sfd _t )/n Formula 3

Among them, Sfd1 _t and Sfd1 _(t-1) are the digital signal Sfd1 at the current time point and the digital signal Sfd1 at the previous time point respectively; Sfd _t is the digital signal Sfd at the current time point; Sum _t and Sum _(t-1) are respectively The cumulative sum of the current time point and the cumulative sum of the previous time point; n is a divisor, usually a positive integer, to determine the smoothness and approach speed of the moving average.

Although FIG. 17A and FIG. 17B take the embodiment of FIG. 12E as an example, it is obvious that the circuit of FIG. 17A and FIG. 17B can also be applied to other embodiments.

The present invention has been described above with reference to preferred embodiments, but the above description is only for those skilled in the art to easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Under the same spirit of the present invention, various equivalent changes can be conceived by those skilled in the art. For example, the positive and negative terminals of the error amplifier, the transconductance amplifier or the comparator can be interchanged, the meaning of the high and low levels of the digital signal can be interchanged, and the related circuits can be modified accordingly; the circuits or components directly connected in the embodiments, Other circuits or elements, etc. that do not affect the main meaning of the signal may be interposed therein. The scope of the present invention is intended to cover the above and all other equivalent variations.

Claims (49)

1. a hybrid compensating circuit for power supply changeover device, is characterized in that, comprising:

Digital signal processor, in order to provide one first limit, this digital signal processor produces digital signal according to feedback signal and reference value, and wherein this feedback signal is relevant to the output voltage of this power supply changeover device; And

Digital analog converter, couples this digital signal processor, this digital signal is converted to the first signal of simulation.

2. hybrid compensating circuit as claimed in claim 1, wherein, also comprise: skew injector, couple this digital analog converter, in order to provide a zero point, this skew injector provides variable offset values to produce secondary signal to offset this first signal, and wherein this variable offset values is determined by the difference between this feedback signal and this reference value.

3. hybrid compensating circuit as claimed in claim 1, wherein, also comprises: low pass filter, couples this digital analog converter, and in order to provide one second limit, the radio-frequency component that this low pass filter filters this first signal produces secondary signal.

4. hybrid compensating circuit as claimed in claim 1, wherein, also comprises:

Skew injector, couples this digital analog converter, and provide variable offset values to produce secondary signal to offset this first signal, wherein this variable offset values is determined by the difference between this feedback signal and this reference value; And

Low pass filter, couples this skew injector, and the radio-frequency component of this secondary signal of filtering produces the 3rd signal and stablizes this output voltage for this power supply changeover device.

5. hybrid compensating circuit as claimed in claim 1, wherein, also comprises:

Low pass filter, couples this digital analog converter, and the radio-frequency component of this first signal of filtering produces secondary signal; And

Skew injector, couples this low pass filter, and provide variable offset values to stablize this output voltage to offset this secondary signal generation the 3rd signal for this power supply changeover device, wherein this variable offset values is determined by the difference between this feedback signal and this reference value.

6. hybrid compensating circuit as claimed in claim 1, wherein, also comprises:

Skew injector, couples this digital signal processor, and provide variable offset values to produce secondary signal to offset this digital signal, wherein this variable offset values is determined by the difference between this feedback signal and this reference value; And

Adder, is added this first signal with this secondary signal, produces the 3rd signal and stablizes this output voltage for this power supply changeover device.

7. hybrid compensating circuit as claimed in claim 6, wherein, also comprises low pass filter, couples the output of this adder.

8. hybrid compensating circuit as claimed in claim 1, wherein, also comprises:

Skew injector, couples this digital signal processor, and provide variable offset values to produce secondary signal to offset this digital signal, wherein this variable offset values is determined by the difference between this feedback signal and this reference value;

Low pass filter, couples this skew injector, and the radio-frequency component of this secondary signal of filtering produces the 3rd signal; And

Adder, by this first signal and the 3rd signal plus, produces the 4th signal and stablizes this output voltage for this power supply changeover device.

9. the hybrid compensating circuit of any one as described in claim 1 to 8, wherein, this digital signal processor comprises:

Comparator, compares this feedback signal and this reference value produces comparison signal;

Controller, couples this comparator, and respective frequencies signal samples this comparison signal to determine control signal; And

Up-down counter, couples this controller, provides this digital signal and samples this control signal to adjust this digital signal according to this frequency signal.

10. hybrid compensating circuit as claimed in claim 9, wherein, also comprises:

Second comparator, couples this controller, produces the second comparison signal to this controller when this feedback signal is greater than the first critical value; And

3rd comparator, couples this controller, produces the 3rd comparison signal to this controller when this feedback signal is less than the second critical value;

Wherein, this controller, according to this second comparison signal and the 3rd comparison signal, makes this digital signal be cut to minimum value or increase maximum.

11. hybrid compensating circuits as claimed in claim 9, wherein, also comprise:

Oscillator, couples this controller, provides this frequency signal; And

Computing transduction amplifier, couples this oscillator, and the difference of amplifying between this feedback signal and this reference value produces frequency adjusted signal to this oscillator, to adjust the frequency of this frequency signal;

Wherein, when the difference between this feedback signal and this reference value increases, the frequency of this frequency signal increases.

12. hybrid compensating circuits as claimed in claim 11, wherein, also comprise:

Second comparator, couples this oscillator, produces the second comparison signal to this oscillator when this feedback signal is greater than the first critical value; And

3rd comparator, couples this oscillator, produces the 3rd comparison signal to this oscillator when this feedback signal is less than the second critical value;

Wherein, this oscillator is according to this second comparison signal and the 3rd comparison signal, and the frequency increasing this frequency signal, to maximum, increases to maximum with peak frequency to make this digital signal or downgrades minimum value.

13. as described in claim 1 to 8 the hybrid compensating circuit of any one, wherein, this digital signal processor comprises:

Comparator, the signal comparing its two input produces comparison signal, and wherein the first input end of this two input receives this feedback signal;

Oscillator, provides frequency signal, and adjusts the frequency of this frequency signal according to frequency adjusted signal;

Multiplexer, couples this comparator, in each cycle of this frequency signal, sequentially multiple critical value and this reference value is fed to the second input of this two input;

Controller, couples this comparator and oscillator, determines control signal and this frequency adjusted signal according to this comparison signal;

Up-down counter, couples this controller and oscillator, provides this digital signal and samples this control signal to adjust this digital signal according to this frequency signal; And

Pulse generator, couples this oscillator and multiplexer, to producing multiple pulse signal to this multiplexer, with the second input making this multiplexer sequentially the plurality of critical value and this reference value are fed to this comparator by frequency signal.

14. hybrid compensating circuits as claimed in claim 13, wherein, the frequency of this frequency signal, when this feedback signal is greater than the maximum of the plurality of critical value or is less than the minimum value of the plurality of critical value, is adjusted to peak.

15. hybrid compensating circuits as claimed in claim 13, wherein, this digital signal, when this feedback signal is greater than the maximum of the plurality of critical value or is less than the minimum value of the plurality of critical value, is cut to minimum value or increases maximum by this up-down counter immediately or with peak frequency.

16. as described in claim 1 to 8 the hybrid compensating circuit of any one, wherein, this digital signal processor comprises:

First comparator, compares generation first comparison signal by this feedback signal with this reference value;

Multiple second comparator, compares this feedback signal with multiple critical value respectively and produces multiple second comparison signal;

Controller, couples this first comparator and the plurality of second comparator, selects one of them to export according to this first comparison signal and the plurality of second comparison signal from multiple frequency signal; And

Up-down counter, couples this first comparator and this controller, provides this digital signal, samples, and adjust this digital signal according to sampling result according to the frequency signal that this controller exports to this first comparison signal.

17. hybrid compensating circuits as claimed in claim 16, wherein, this controller, when this feedback signal is greater than the maximum of the plurality of critical value or is less than the minimum value of the plurality of critical value, selects the frequency signal that frequency is the highest.

18. hybrid compensating circuits as claimed in claim 16, wherein, this digital signal, when this feedback signal is greater than the maximum of the plurality of critical value or is less than the minimum value of the plurality of critical value, is cut to minimum value or increases maximum by this up-down counter immediately or with peak frequency.

19. hybrid compensating circuits as claimed in claim 4, wherein, this skew injector comprises:

Resistance, has first end and couple this digital analog converter, and the second end couples this low pass filter, provide this variable offset values;

First current source, provides the electric current changed with this difference;

First switch, is connected in series to this first end with this first current source, is controlled by the first control signal;

Second current source, provides the electric current changed with this difference;

Second switch, is connected in series to this first end with this second current source, is controlled by the second control signal;

3rd current source, provides the electric current changed with this difference;

3rd switch, is connected in series to this second end with the 3rd current source, is controlled by this second control signal;

4th current source, provides the electric current changed with this difference; And

4th switch, is connected in series to this second end with the 4th current source, is controlled by this first control signal.

20. hybrid compensating circuits as claimed in claim 4, wherein, this skew injector comprises:

Variable resistor, has first end and couple this digital analog converter, and the second end couples this low pass filter, provide this variable offset values, and wherein this variable-resistance resistance changes with this difference;

First current source, provides and determines electric current;

First switch, is connected in series to this first end with this first current source, is controlled by the first control signal;

Second current source, provides and determines electric current;

Second switch, is connected in series to this first end with this second current source, is controlled by the second control signal;

3rd current source, provides and determines electric current;

3rd switch, is connected in series to this second end with the 3rd current source, is controlled by this second control signal;

4th current source, provides and determines electric current; And

4th switch, is connected in series to this second end with the 4th current source, is controlled by this first control signal.

21. hybrid compensating circuits as claimed in claim 1, wherein, this low pass filter comprises the RC filter be made up of resistance and electric capacity.

22. hybrid compensating circuits as claimed in claim 1, wherein, this low pass filter comprises:

The operational amplifier of low frequency range, has first input end and receives secondary signal that this skew injector exports and the second input couples the output of this low pass filter; And

Building-out capacitor.

The hybrid compensating circuit of 23. 1 kinds of power supply changeover devices, is characterized in that, comprising:

Digital signal processor, produces first and second digital signal according to output voltage feedback signal and reference value, and wherein this output voltage feedback signal is relevant to the output voltage of this power supply changeover device;

Digimigration injector, couples this digital signal processor, to produce variable offset values according to this second digital signal;

Adder, is added this first digital signal with this variable offset values, maybe this first digital signal is added with the coherent signal of this variable offset values; And

Digital analog converter, couples this adder, and the coherent signal of the output of this adder or the output of this adder is converted to analog signal.

24. hybrid compensating circuits as claimed in claim 23, wherein, also comprise: low pass filter, couple this digital analog converter, in order to the radio-frequency component of this analog signal of filtering.

25. hybrid compensating circuits as claimed in claim 23, wherein, also comprise: digital filter, are coupled between this digimigration injector and this adder, produce the coherent signal of this variable offset values in order to filter this variable offset values.

26. hybrid compensating circuits as claimed in claim 23, wherein, also comprise: digital filter, are coupled between this adder and this digital analog converter, in order to filter the output of this adder and to produce the coherent signal of the output of this adder.

27. hybrid compensating circuits as claimed in claim 23, wherein, the back coupling of this digimigration injector controls a frequency signal of this digital signal processor.

The hybrid compensating circuit of 28. 1 kinds of power supply changeover devices, is characterized in that, comprising:

Digital signal processor, produces first and second digital signal according to output voltage feedback signal and reference value, and wherein this output voltage feedback signal is relevant to the output voltage of this power supply changeover device;

Digimigration injector, couples this digital signal processor, to produce variable offset values according to this second digital signal;

First digital analog converter, couples this digital signal processor, and this first digital signal is converted to the first analog signal;

Second digital analog converter, couples this digimigration injector, this variable offset values is converted to the second analog signal; And

Adder, is added this first analog signal with this second analog signal, is maybe added with the second analog signal by the coherent signal of this first analog signal.

29. hybrid compensating circuits as claimed in claim 28, wherein, also comprise: low pass filter, are coupled between this first digital analog converter and this adder or are coupled to the output of this adder.

The hybrid compensating circuit of 30. 1 kinds of power supply changeover devices, is characterized in that, comprising:

Digital signal processor, produces the first digital signal according to output voltage feedback signal and reference value, and wherein this voltage feedback signal is relevant to the output voltage of this power supply changeover device;

Digital filter, couples this digital signal processor, to filter this first digital signal; And

Digital analog converter, couples this digital filter, and the output of this digital filter is converted to analog signal.

31. as described in claim 23 to 30 the hybrid compensating circuit of any one, wherein, this digital signal processor comprises:

Successively ask nearly buffer memory analogue-digital converter, produce a lifting signal according to this output voltage feedback signal and this reference value; And

Lifting counting circuit, wherein the output signal of this lifting counting circuit is controlled by this lifting signal and rises accordingly or decline.

32. hybrid compensating circuits as claimed in claim 31, wherein, this successively asks nearly buffer memory analogue-digital converter to comprise:

Comparator, successively asks this output voltage feedback signal and compared with nearly buffer memory analogue-digital converter internal simulation feedback signal and produces an output signal;

Controller and digital generator, couple this comparator, and produce the digital coding of a N position in response to the output signal of this comparator, and wherein N is positive integer, and produce this lifting signal; And

Digital analog converter, couple this controller and digital generator, and produce this according to the digital coding of this N position and successively ask nearly buffer memory analogue-digital converter internal simulation feedback signal, thus, make this N position digital coding be relevant to this output voltage feedback signal and convergence gradually.

33. hybrid compensating circuits as claimed in claim 32, wherein, this reference value inputs this controller and digital generator, or inputs this digital analog converter, as initial number.

34. hybrid compensating circuits as claimed in claim 31, wherein, this successively asks nearly buffer memory analogue-digital converter to comprise:

Error amplifier, compares this output voltage feedback signal with this reference value and produces an error amplification signal;

Comparator, successively asks this error amplification signal and compared with nearly buffer memory analogue-digital converter internal simulation feedback signal and produces an output signal;

Controller and digital generator, couple this comparator, and produce the digital coding of a N position in response to the output signal of this comparator, and wherein N is positive integer, and produce this lifting signal; And

Digital analog converter, couple this controller and digital generator, and produce this according to the digital coding of this N position and successively ask nearly buffer memory analogue-digital converter internal simulation feedback signal, thus, make this N position digital coding be relevant to this output voltage feedback signal and convergence gradually.

35. hybrid compensating circuits as claimed in claim 31, wherein, this successively asks nearly buffer memory analogue-digital converter to comprise:

First comparator, successively asks this output voltage feedback signal and and produces one first compared with nearly buffer memory analogue-digital converter internal simulation feedback signal and output signal;

Second comparator, successively asks this reference value and this and produces one second compared with nearly buffer memory analogue-digital converter internal simulation feedback signal and output signal;

Controller and digital generator, couple this first and second comparator, and produce the digital coding of a N position in response to this first and second output signal, and wherein N is positive integer, and produces this lifting signal; And

Digital analog converter, couple this controller and digital generator, and produce this according to the digital coding of this N position and successively ask nearly buffer memory analogue-digital converter internal simulation feedback signal, thus, make this N position digital coding be relevant to this output voltage feedback signal and convergence gradually.

36. as described in claim 32 to 35 the hybrid compensating circuit of any one, wherein, this controller and digital generator separately produce this second digital signal, and this second digital signal corresponds to this output voltage feedback signal or corresponds to the difference of this output voltage feedback signal and this reference value.

37. as described in claim 23 to 29 the hybrid compensating circuit of any one, wherein, this digimigration injector produces numeral or the coding that corresponds to α (Vfb1-Vref1), and wherein α is arithmetic number, Vfb1 is this output voltage feedback signal, and Vref1 is this reference value.

38. as described in claim 23 to 29 the hybrid compensating circuit of any one, wherein, this digimigration injector comprises: digital multiplier, and this second digital signal is multiplied by Graph One factor β and produces this variable offset values, wherein β is arithmetic number.

39. as described in claim 23 to 29 the hybrid compensating circuit of any one, wherein, this digimigration injector comprises:

Addition/subtraction device, deducts corresponding to the three digital signal of this reference value and obtains difference in this second digital signal; And

Digital multiplier, is multiplied by Graph One factor β by this difference and produces this variable offset values, and wherein β is arithmetic number.

40. as described in claim 23 to 29 the hybrid compensating circuit of any one, wherein, this digimigration injector comprises: an internal memory, there is multiple address, and store multiple deviant in advance in the plurality of address, and this second digital signal represents the address of this internal memory or the address in order to determine this internal memory.

41. hybrid compensating circuits as claimed in claim 31, wherein, this successively asks nearly buffer memory analogue-digital converter to operate according to a first frequency signal, and this lifting counting circuit operates according to a second frequency signal, and this digimigration injector comprises:

Digital multiplier, this second digital signal is multiplied by Graph One factor β and produces this variable offset values, wherein β is arithmetic number; And

Frequency eliminating circuit, according to this second digital signal by this first frequency signal frequency elimination, to obtain this second frequency signal.

42. hybrid compensating circuits as claimed in claim 31, wherein this successively asks nearly buffer memory analogue-digital converter to operate according to a first frequency signal, and this lifting counting circuit operates according to a second frequency signal, and this digimigration injector comprises:

Addition/subtraction device, deducts corresponding to the three digital signal of this reference value and obtains difference in this second digital signal;

Digital multiplier, is multiplied by Graph One factor β by this difference and produces this variable offset values, and wherein β is arithmetic number; And

Frequency eliminating circuit, according to this second digital signal or this three digital signal by this first frequency signal frequency elimination, to obtain this second frequency signal.

43. hybrid compensating circuits as claimed in claim 31, wherein this successively asks nearly buffer memory analogue-digital converter to operate according to a first frequency signal, and this lifting counting circuit operates according to a second frequency signal, and this digimigration injector comprises:

One internal memory, has multiple address, and stores multiple deviant in advance in the plurality of address, and this second digital signal represents the address of this internal memory or the address in order to determine this internal memory; And

Frequency eliminating circuit, according to this second digital signal by this first frequency signal frequency elimination, to obtain this second frequency signal.

44. hybrid compensating circuits as claimed in claim 27, wherein, this digital signal processor also comprises an oscillator to produce this frequency signal, and this digimigration injector comprises:

Digital multiplier, this second digital signal is multiplied by Graph One factor β and produces this variable offset values, wherein β is arithmetic number; And

D/A conversion circuit, is converted to analog signal by this second digital signal, to control the frequency of this oscillator.

45. hybrid compensating circuits as claimed in claim 27, wherein, this digital signal processor also comprises an oscillator to produce this frequency signal, and this digimigration injector comprises:

Addition/subtraction device, deducts corresponding to the three digital signal of this reference value and obtains difference in this second digital signal;

Digital multiplier, is multiplied by Graph One factor β by this difference and produces this variable offset values, and wherein β is arithmetic number; And

D/A conversion circuit, is converted to analog signal by this second digital signal or this three digital signal, to control the frequency of this oscillator.

46. hybrid compensating circuits as claimed in claim 27, wherein, this digital signal processor also comprises an oscillator to produce this frequency signal, and this digimigration injector comprises:

One internal memory, has multiple address, and stores multiple deviant in advance in the plurality of address, and this second digital signal represents the address of this internal memory or the address in order to determine this internal memory; And

D/A conversion circuit, is converted to analog signal by this second digital signal, to control the frequency of this oscillator.

47. hybrid compensating circuits as described in claim 25,26 or 30, wherein, this digital filter comprises a D flip-flop.

48. hybrid compensating circuits as claimed in claim 47, wherein, this digital signal processor comprises:

Successively ask nearly buffer memory analogue-digital converter, produce a lifting signal according to this output voltage feedback signal and this reference value, this successively asks nearly buffer memory analogue-digital converter to operate according to a first frequency signal; And

Lifting counting circuit, wherein the output signal of this lifting counting circuit is controlled by this lifting signal and rises accordingly or decline, and this lifting counting circuit operates according to a second frequency signal;

And this D flip-flop operates according to one the 3rd frequency signal, the frequency of this 3rd frequency signal is lower than this first and second frequency signal.

49. as described in claim 25,26 or 30 the hybrid compensating circuit of any one, wherein, this digital filter comprises a rolling average circuit.