CN105406829B - A kind of variable gain amplifier of gain continuously adjustabe - Google Patents

Abstract

The invention discloses a switched capacitor variable gain amplifier circuit, comprising: an operational transconductance amplifier, used to convert an input signal into a current signal; a switched capacitor load, connected to the output terminal of the operational transconductance amplifier, used to convert The current signal output by the operational transconductance amplifier is converted into a voltage signal and amplified, wherein the amplification factor of the voltage signal depends on the equivalent impedance of the switched capacitive load; a resistance-controlled oscillator is used to generate and control the switch The control clock signal of the equivalent impedance of the capacitive load; the control clock signal can be adjusted through an off-chip adjustable resistor connected to the resistance-controlled oscillator. The VGA circuit can realize the frequency adjustment of the resistance-controlled oscillator with only one adjustable resistor outside the chip, and the resistance-controlled oscillator can adjust the load of the switch capacitor to realize the continuous adjustment function of the VGA gain. At the same time, the VGA circuit does not contain large resistors and large capacitors, which saves the silicon chip area of the VGA circuit.

Description

A Variable Gain Amplifier with Continuously Adjustable Gain

technical field

The invention relates to the field of integrated circuit design, in particular to a switched capacitor variable gain amplifier, which has the advantages of continuously adjustable gain, full on-chip integration, and small consumption of silicon chip area.

Background technique

In the field of detection of weak signals (such as bioelectrical signal detection, current detection, and inertial sensors, etc.), multi-stage amplifiers are usually used to amplify the weak measured signals, and have the functions of adjustable gain and adjustable bandwidth to adapt to different frequencies. And the detection requirements of the amplitude range, as shown in Figure 1. Among them, the function of adjustable gain is generally realized by using a variable gain amplifier (Variable Gain Amplifier, VGA); the function of adjustable bandwidth is generally realized by using a low-pass filter. In the traditional VGA implementation circuit, it is usually realized by digital programming, as shown in Figure 2, if the gain of the amplifier is infinite, then the gain expression of VGA can be expressed as R _F /R _P , where R _P is the input resistance , feedback resistance R _F ＝S ₁ *R _F1 +S ₂ *R _F2 +…+S _(N-1) *R _F(N-1) +R _FN , if S _i is disconnected, then S _i ＝1, On the contrary, S _i =0 (i=1, 2...N-1). By controlling the switches S1-S(N-1), the magnitude of the feedback resistor R _F can be controlled, thereby controlling the gain of the VGA.

The disadvantage of this structure is that only discrete and limited gain values can be adjusted, and if the number of gain values is to be increased, the number of control switches must be increased. However, the on-resistances of the actual control switches are not zero, and are not completely equal, which will result in unequal magnitudes of the feedback resistors on both sides of the amplifier OP, that is, mismatch. If the number of control switches increases, the mismatch of the feedback resistors will be more serious. The problem caused by the mismatch of the resistors is that the common mode rejection ratio of the VGA decreases and the linearity decreases. At the same time, due to the load effect of R _F on OP, in order to ensure that R _F will not reduce the open-loop gain of OP itself, R _F must be greater than the output resistance of OP. Therefore, the value of R _F is usually in the order of MΩ. In integrated circuit applications, especially in multi-channel detection circuits, if each channel needs a VGA, it will occupy a large amount of chip area.

Contents of the invention

The present invention provides a variable gain amplifier with continuously adjustable gain, which uses a switched capacitor circuit as the load of the amplifier, and generates a continuously adjustable square wave signal through a Resistor Controlled Oscillator (RCO). The capacitive load is controlled to realize continuous adjustment of the VGA gain.

According to the present invention, it provides a variable gain amplifier with continuously adjustable gain, comprising:

An operational transconductance amplifier for converting an input signal into a current signal;

A switched capacitor load, connected to the output terminal of the operational transconductance amplifier, is used to convert the current signal output by the operational transconductance amplifier into a voltage signal and amplify it, wherein the amplification factor of the voltage signal depends on the switch Equivalent impedance of capacitive load;

A resistance-controlled oscillator is used to generate a control clock signal for controlling the equivalent impedance of the switched capacitor load; the control clock signal can be adjusted through an off-chip adjustable resistor connected to the resistance-controlled oscillator.

The switched capacitor variable gain amplifier (VGA) circuit disclosed in the present invention can realize the frequency adjustment of the resistance-controlled oscillator with only one off-chip adjustable resistor, and the resistance-controlled oscillator can adjust the load of the switched capacitor to realize the frequency adjustment of the switched capacitor load. Continuous adjustment function of VGA gain. At the same time, the VGA circuit does not contain large resistors and large capacitors, which saves the silicon chip area of the VGA circuit.

Description of drawings

Figure 1 is a schematic diagram of a multi-stage amplification structure of a weak signal detection path;

Fig. 2 is a traditional variable gain amplifier (VGA) circuit structure schematic diagram;

Fig. 3 is a schematic structural diagram of a switched capacitor VGA circuit of the present invention;

FIG. 4 is a schematic diagram of the circuit structure of the switched capacitor load 201 in FIG. 3;

FIG. 5 is a schematic diagram of the input and output characteristics of the non-overlapping clock generator in FIG. 4;

FIG. 6 is a schematic diagram of the circuit structure of the resistance-controlled oscillator 202 in FIG. 3;

Fig. 7 is a schematic diagram of waveforms of key nodes of the circuit shown in Fig. 6;

FIG. 8 is a schematic diagram of the circuit structure of the fixed delay circuit 420 in FIG. 6;

Fig. 9 is the simulation curve schematic diagram of the gain of the switched capacitor VGA circuit of the present invention and the off-chip adjustable resistance;

FIG. 10 is a schematic diagram of the simulation curve of the transfer function of the switched capacitor VGA circuit and the off-chip adjustable resistance of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

As shown in Figure 3, the present invention proposes a variable gain amplifier (VGA) 200 with continuously adjustable gain, which includes an operational transconductance amplifier (Operational Transconductance Amplifier, OTA), a switched capacitor load 201 and a resistance control Oscillator 202.

An operational transconductance amplifier is used to convert an input voltage signal (the difference between V _IP and V _IN voltage) into a current signal. The characteristic of the operational transconductance amplifier is that its own output impedance is very large, ideally infinite.

The switched capacitor load is placed on the output terminal of the operational transconductance amplifier, and is used to convert the output current signal of the operational transconductance amplifier into a voltage signal. The equivalent impedance of the switched capacitor load is much smaller than the output impedance of the operational transconductance amplifier itself, so the output current of the operational transconductance amplifier will all flow to the switched capacitor load. Therefore, placing the switched capacitor load at the output of the operational transconductance amplifier can amplify the input voltage signal (difference between V _IP and V _IN voltage) into an output voltage signal (difference between V _OP and V _ON ). At the same time, the equivalent impedance of the switched capacitor load is inversely proportional to the frequency of the control clock (f _sc ), that is, the equivalent impedance of the switched capacitor load can be adjusted by controlling the size of the clock, and then the output voltage and input voltage of the operational transconductance amplifier can be adjusted. between magnifications.

The resistance-controlled oscillator is used to generate a control clock signal for the switched capacitor load, and is characterized in that the frequency of the output clock signal can be adjusted through an external adjustable resistor.

To sum up, through the joint action of the operational transconductance amplifier, the switched capacitor load and the resistance-controlled oscillator, the function of continuously adjustable gain of the variable gain amplifier through an off-chip adjustable resistor can be realized.

The inverting output terminal of the operational transconductance amplifier OTA is connected to the first input terminal N1 of the switched capacitor load 201 , and this connection terminal is used as the inverting output terminal V _ON of the VGA. The non-inverting output terminal of the OTA is connected to the second input terminal N2 of the switched capacitor load 201, and this connection terminal is used as the non-inverting output terminal V _OP of the VGA. The first output terminal N _C of the resistance-controlled oscillator 202 is connected to one end of the off-chip adjustable resistor R _OSC , the input terminal V _ref of the resistance-controlled oscillator 202 is connected to the output terminal V _BG of the on-chip reference voltage source, and the resistance-controlled oscillator The second output terminal clk_sc of 202 is connected to the third input terminal clk_in of the switched capacitor load 201 . The other end of the off-chip adjustable resistor R _OSC is grounded. The non-inverting input terminal and the inverting input terminal of the OTA serve as the non-inverting input terminal V _IP and the inverting input terminal V _IN of the VGA respectively.

As shown in FIG. 4 , the switched capacitor load 201 includes a non-overlapping clock generator 301 , two switches (S _N1 , S _N2 ), and a capacitor C ₀ . The input terminal of the non-overlapping clock generator 301 is used as the third input terminal clk_in of the switched capacitor load 201 for receiving the control clock signal output by the ZCO. The first output terminal clk of the non-overlapping clock generator 301 is connected to the control terminal ph1 of the first switch (S _N1 ). The second output terminal clk_b of the non-overlapping clock generator 301 is connected to the control terminal ph2 of the second switch (S _N2 ). One end of the first switch (S _N1 ) is used as the first input end N1 of the switched capacitor load 201 for receiving the current signal output by the inverting output end of the operational transconductance amplifier OTA, and one end of the second switch (S _N2 ) is used as the switched capacitor The second input terminal N2 of the load 201 is used to receive the current signal output from the non-inverting output terminal of the operational transconductance amplifier OTA. The other end of the first switch (S _N1 ) and the other end of the second switch (S _N2 ) are connected to the upper plate of the first capacitor (C ₀ ). The lower plate of the first capacitor (C ₀ ) is grounded.

The non-overlapping clock generator 301 has the following input and output characteristics: the input signal clk_in and the two output signals clk and clk_b of the non-overlapping clock generator 301 are square wave signals with the same frequency. The clk signal is in phase with the clk_in signal, and the clk_b signal is in phase inversion with the clk_in signal. The rising edge of the clk signal is delayed by a time interval of T _d from the falling edge of the clk_b signal, and the rising edge of the clk_b signal is delayed by a time interval of T _d compared to the falling edge of the clk signal, as shown in FIG. 5 . The function of the time interval T _d is to ensure that the first switch (S _N1 ) and the second switch (S _N2 ) cannot be turned on at the same time. The size of T _d is designed to be greater than twice the time constant of the first switch (S _N1 ), the second switch (S _N2 ) and the first capacitor (C ₀ ).

As shown in FIG. 6 , the resistance-controlled oscillator 202 is composed of a resistance-controlled delay circuit 410 , a fixed delay circuit 420 and a D flip-flop 430 . The resistance-controlled delay circuit 410 is composed of an operational amplifier (OP), a comparator 411, 3 PMOS transistors (PM1, PM2, PM3), 2 NMOS transistors (NM1, NM2), and a capacitor (C _OSC ).

The connection relationship of the resistance-controlled oscillator 202 is: the non-inverting input terminal of the operational amplifier OP is connected to the inverting input terminal of the comparator, and serves as the V _ref input terminal of the resistance-controlled oscillator 202 . The inverting input terminal of the operational amplifier OP is connected to the source of the first NMOS transistor ( NM1 ), and serves as the first output terminal N _C of the resistance-controlled oscillator 202 . The output end of the operational amplifier OP is connected to the gate of the first NMOS transistor (NM1). The gate and drain of the first PMOS transistor (PM1), the drain of the first NMOS transistor (NM1), are connected to the gate of the second PMOS transistor (PM2). The drain of the second PMOS transistor (PM2) is connected to the source of the third PMOS transistor (PM3). The drain of the third PMOS transistor ( PM3 ), the drain of the second NMOS transistor ( NM2 ), and the upper plate of the second capacitor C _OSC are connected to the non-inverting input terminal of the comparator 411 . The output terminal V _Com of the comparator 411 is connected to the input terminal V _D1 of the fixed delay circuit 420 . The output terminal V _D2 of the fixed delay circuit 420 , the gates of the second PMOS transistor ( PM2 ) and the gates of the third PMOS transistor ( PM3 ) are connected to the clock input terminal clk of the D flip-flop 430 . The data input terminal D of the D flip-flop 430 is connected to the inverting output terminal Qb. The non-inverting output terminal Q of the D flip-flop 430 is used as the second output terminal clk_sc of the resistance-controlled oscillator 202 to output a square wave signal with a duty cycle of 50%, that is, a control clock signal.

As shown in FIG. 8 , the fixed delay circuit 420 is composed of n identical inverters cascaded, where n is an even number. The input terminal of the first inverter (Inv1) is used as the input terminal V _D1 of the fixed delay circuit 420, the output terminal of the first inverter (Inv1) is connected with the input terminal of the second inverter (Inv2), and the second inverter The output terminal of the phase inverter (Inv2) is connected to the input terminal of the third inverter (Inv3). And so on until the nth inverter (Invn). The output terminal of the nth inverter (Invn) serves as the output terminal V _D2 of the fixed delay circuit 420 . The delay of the fixed delay circuit 420 is n times the delay of the inverter.

As shown in FIG. 3 , the OTA described in the present invention is an amplifier with a relatively high output impedance, and has a relatively constant transconductance value, and its output resistance and transconductance values are R _out and G _m , respectively. The equivalent resistance at both ends of the input ports N1 and N2 of the switched capacitor load 201 is R _SC , the value of R _SC is controlled by the resistance-controlled oscillator 202, and its value is much smaller than R _out , then the gain expression of the VGA is:

A _VGA ＝G _m (Ro _ut ||R _SC )≈G _m R _SC (1)

The switched capacitor load 201 is a switched capacitor resistor controlled by two-phase non-overlapping clocks clk and clk_b, as shown in FIG. 4 . Wherein clk and clk_b are non-overlapping square wave signals of period T, and the input signal clk_in and the two output signals clk and clk_b are both square wave signals with the same frequency. The signal waveform is shown in Figure 5, the clk signal is in phase with the clk_in signal, and the clk_b signal is in phase with the clk_in signal. The rising edge of the clk signal is delayed by a time interval of T _d from the falling edge of the clk_b signal, and the rising edge of the clk_b signal is delayed by a time interval of T _d compared to the falling edge of the clk signal.

As shown in Figure 5, during the clk_b phase period (that is, clk=0, _{clk_b} =1), SN1 is open, _SN2 is closed, the plate voltage on C ₀ is V _N2 , and the charge on C ₀ is Q ₂ =C ₀ V _N2 . During the clk phase (ie, clk=1, clk_b=0), the voltage at the N1 terminal charges C ₀ to V _N1 , and the charge on C ₀ at this time is Q ₁ =C ₀ V _N1 . In this period T, the average current flowing into the switched capacitor load 201 from the N1 terminal is I _avg =(Q ₁ −Q ₂ )/T. Then the expression of the equivalent resistance R _SC of the switched capacitor load 201 is

Where f _SC is the frequency of the output clock clk_sc of the resistance-controlled oscillator 202, and substituting formula (2) into formula (1) can obtain:

A _VGA =G _m /(f _SC C ₀ ) (3)

If you can control the size of f _SC , you can control the gain of the VGA. The structure of the resistance-controlled oscillator 202 is shown in FIG. 6 , which is composed of a resistance-controlled delay circuit 410 , a fixed delay circuit 420 and a D flip-flop 430 . In the resistance-controlled delay circuit, the negative feedback of the operational amplifier (OP1) makes the voltage at the non-inverting terminal approximately equal to the inverting terminal, that is, the voltage at the N _C terminal is approximately equal to the reference voltage V _ref . As shown in Figure 3, the N _C terminal is connected to one end of the off-chip adjustable resistor R _OSC , and the other end of R _OSC is grounded, so the current flowing through PM1 and NM1 is I ₁ =V _ref /R _OSC . Since PM1 and PM2 form a current mirror structure, and the size ratio is 1:k, the current flowing through PM2 is:

I ₂ =kV _ref /R _OSC (4)

The schematic diagram of the waveform of the resistance-controlled oscillator 202 is shown in FIG. 7 , and its oscillation working principle is as follows:

(a) When the output voltage V _D2 of the fixed delay circuit 420 jumps from 0 to the power supply voltage V _DD , the gate voltage V _C1 of PM3 and NM2 also jumps from 0 to V _DD , so that PM3 is turned off and NM2 is turned on , the charge of the voltage C _OSC is quickly discharged through NM2, the voltage of the non-inverting terminal of the comparator 411 jumps to 0, the voltage of the inverting terminal is V _ref , and the output voltage of the comparator 411 jumps from V _DD to 0.

(b) After the delay T _DF of the fixed delay circuit 420 , V _D2 also jumps to 0. Thus PM3 is turned on, NM2 is turned off, the current _I2 of PM2 starts to charge _COSC , the voltage of V _C2 rises gradually, when the voltage of V _C2 is greater than the voltage V _ref of the inverting terminal of comparator 411, the output voltage of comparator 411 changes from 0 jumps to V _DD , after the delay T _DF of the fixed delay circuit 420 , V _D2 jumps from 0 to V _DD . Repeat step (a), the oscillator can work. The data input terminal of the D flip-flop 430 is connected to the inverting output terminal Qb to form a structure of a frequency divider by two, and its function is to make the duty cycle of the output clock of the resistance-controlled oscillator 202 50%.

As shown in FIG. 8 , the fixed delay circuit 420 is formed by cascading n inverters, and the delay of each inverter is T _INV , so the delay of the fixed delay circuit 420 is T _DF =nT _INV . At the same time, n is an even number to ensure the in-phase characteristics of V _D1 and V _D2 , that is, the waveform of V _D2 in the time domain is obtained by delaying T _DF from V _D1 .

During the oscillation process, the delay contributed by the resistance-controlled delay circuit 410 is T _DR , and its expression is:

T _DR =V _ref C _OSC /I ₂ (5)

Based on the above, combined with (4) and (5), the frequency of the resistance-controlled oscillator can be obtained as:

So (3) formula can be changed into:

It can be seen from (6) and (7) that when the circuit parameters C _OSC , k and T _DF are all fixed, the frequency f _SC of the resistance-controlled oscillator and the gain A _VGA of VGA can be adjusted by the off-chip resistor R _OSC control, and A _VGA and R _OSC are proportional to the linear relationship. The off-chip adjustable resistor R _OSC can be continuously adjusted, so A _VGA also realizes the function of continuous adjustment.

In addition, the above-mentioned definition of the fixed delay circuit 420 is not limited to the structure shown in FIG. 8 , and it can be implemented by other delay circuits, as long as the in-phase characteristics of V _D1 and V _D2 are guaranteed.

(1) The beneficial effects of the circuit shown in Fig. 3 are illustrated below with examples of simulation waveforms. The circuit simulation model is a 0.18 μm standard CMOS process library. The G _m of the OTA used in the simulation is approximately equal to 7.8 μS, C ₀ is approximately 140 fF, C _OSC is approximately 40 fF, k=1, and T _DF is approximately 232 ns. Adjust R _OSC from 1MΩ to 51MΩ to obtain the relationship between DC gain A _VGA and R _OSC as shown in Figure 9. It can be seen that the VGA circuit shown in FIG. 3 can realize a continuously adjustable function, which can be adjusted from 13.8 times to 117.5 times. Figure 10 shows the relationship between the transfer function and R _OSC . It can be seen that with the linear increase of R _OSC , the gain in the passband also increases linearly.

(2) Since the circuit shown in Figure 3 does not use a large number of feedback resistors as shown in Figure 2, only C ₀ and C _OSC with smaller capacitances are used to realize the amplification function, which greatly reduces the silicon used by the integrated circuit piece area. If there are multiple VGA circuits in a multi-channel circuit, only one resistance-controlled oscillator 202 is needed to adjust the gains of the VGAs of multiple channels, further reducing the area of the silicon chip. At the same time, there are only two switches of the switched capacitive load 201 in the circuit, the number of switches is greatly reduced, and the problem of linearity degradation caused by mismatching switches in FIG. 2 is eliminated.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principles of the present invention, any modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the present invention.

Claims (6)

1. A variable gain amplifier with continuously adjustable gain, comprising: An operational transconductance amplifier for converting an input signal into a current signal; A switched capacitor load, connected to the output terminal of the operational transconductance amplifier, is used to convert the current signal output by the operational transconductance amplifier into a voltage signal and amplify it, wherein the amplification factor of the voltage signal depends on the switch The equivalent impedance of the capacitive load, the third input terminal of the switched capacitive load is used to receive the control clock signal output by the resistance-controlled oscillator, and the equivalent impedance of the switched capacitive load is inversely proportional to the frequency of the control clock; The resistance-controlled oscillator is used to generate a control clock signal that controls the equivalent impedance of the switched capacitor load; the control clock signal can be adjusted through an off-chip adjustable resistor connected to the resistance-controlled oscillator, and the off-chip can The adjustable resistance ROSC can be continuously adjusted, and the frequency f _SC of the control clock signal output by the resistance-controlled oscillator and the gain A _VGA of the variable gain amplifier can be controlled by the off-chip adjustable resistance ROSC. 2. The variable gain amplifier as claimed in claim 1, wherein the inverting output terminal of the operational transconductance amplifier is connected with the first input terminal of the switched capacitor load, and this connection terminal is used as the inverting phase of the variable gain amplifier Output terminal; the non-inverting output terminal of the operational transconductance amplifier is connected with the second input terminal of the switched capacitor load, and this connection terminal is used as the non-inverting output terminal of the variable gain amplifier; the first output of the resistance-controlled oscillator terminal is connected to one end of the off-chip adjustable resistor, the input terminal of the resistance-controlled oscillator is connected to the output terminal of the on-chip reference voltage source, and the second output terminal of the resistance-controlled oscillator is connected to the switched capacitor load The third input terminal is connected; the other end of the off-chip adjustable resistor is grounded; the non-inverting input terminal and the inverting input terminal of the operational transconductance amplifier are respectively used as the non-inverting input terminal and the inverting input terminal of the variable gain amplifier . 3. The variable gain amplifier of claim 1, wherein the switched capacitive load comprises a non-overlapping clock generator, a first switch, a second switch and a first capacitor, the non-overlapping clock generator's The input terminal is used as the third input terminal of the switched capacitor load, the first output terminal of the non-overlapping clock generator is connected to the control terminal of the first switch, and the second output terminal of the non-overlapping clock generator is connected to the control terminal of the second switch. One end of the first switch is used as the first input end of the switched capacitor load, one end of the second switch is used as the second input end of the switched capacitor load, the other end of the first switch, the other end of the second switch and the first capacitor The upper plates are connected, and the lower plate of the first capacitor is grounded. 4. variable gain amplifier as claimed in claim 3, wherein, the input signal of described non-overlapping clock generator and its first output signal, the second output signal are all square wave signals, and frequency is identical, described The input signal is in phase with the first output signal, the second output signal is in phase opposite to the input signal, and the rising edge of the first output signal is delayed by a first predetermined time interval from the falling edge of the second output signal , the rising edge of the second output signal is delayed by a first predetermined time interval from the falling edge of the first output signal. 5. The variable gain amplifier as claimed in claim 1, wherein said resistance-controlled oscillator comprises a resistance-controlled delay circuit, a fixed delay circuit and a D flip-flop, wherein said resistance-controlled delay circuit comprises an operational amplifier , a comparator, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor and a second capacitor; wherein, the non-inverting input terminal of the operational amplifier is connected to the inverting input terminal of the comparator , and as the input terminal of the resistance-controlled oscillator, the inverting input terminal of the operational amplifier is connected to the source of the first NMOS transistor, and is used as the first output terminal of the resistance-controlled oscillator, and the output terminal of the operational amplifier is connected to the first NMOS transistor The gate of the first PMOS transistor is connected to the drain, the drain of the first NMOS transistor is connected to the gate of the second PMOS transistor, and the drain of the second PMOS transistor is connected to the source of the third PMOS transistor. , the drain of the third PMOS transistor, the drain of the second NMOS transistor, and the upper plate of the second capacitor are connected to the non-inverting input terminal of the comparator, and the output terminal of the comparator is connected to the input terminal of the fixed delay circuit. The output end of the delay circuit, the gate of the second PMOS transistor, and the gate of the third PMOS transistor are connected to the clock input end of the D flip-flop, and the data input end of the D flip-flop is connected to the inverting output end of the D flip-flop. The non-inverting output terminal of the D flip-flop serves as the second output terminal of the resistance-controlled oscillator. 6. The variable gain amplifier as claimed in claim 5, wherein the fixed delay circuit is composed of n identical inverters cascaded, and n is an even number; wherein, the first of the n identical inverters The input terminal of the inverter is used as the input terminal of the fixed delay circuit, and the output terminal of the nth inverter is used as the output terminal of the fixed delay circuit, and the delay of the fixed delay circuit is n times the delay of the inverter.