CN104091800A - Forming method for SRAM detection structure map - Google Patents
Forming method for SRAM detection structure map Download PDFInfo
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- CN104091800A CN104091800A CN201410357261.9A CN201410357261A CN104091800A CN 104091800 A CN104091800 A CN 104091800A CN 201410357261 A CN201410357261 A CN 201410357261A CN 104091800 A CN104091800 A CN 104091800A
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- 238000001514 detection method Methods 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 84
- 238000013461 design Methods 0.000 claims abstract description 4
- 238000012360 testing method Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 239000010410 layer Substances 0.000 abstract description 71
- 238000012544 monitoring process Methods 0.000 abstract description 7
- 239000011229 interlayer Substances 0.000 abstract description 3
- 238000000682 scanning probe acoustic microscopy Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 239000004744 fabric Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
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Abstract
The invention discloses an SRAM detection structure and map and a forming method thereof. The forming method for the map of the SRAM detection structure is started with the design angle of a plane map and comprises the steps that according to the regularity of an SPAM chip map, parts needing to be connected and parts which do not need to be connected in a graph of a first metal layer are determined; the parts which do not need to be connected in the first metal layer are disconnected, and the connected parts in the first metal layer are connected by adding another metal layer graph; on the basis of the first metal layer and first connecting through holes, a second metal layer graph is redesigned for connecting the first adjacent connecting through holes. According to the method, the phenomenon of height difference formed between an SRAM chip region and a Via-1 detection structure due to difference of basic layer structures after the interlayer dielectric layer CMP process is carried out can be avoided, and the precision for monitoring an actual SRAM chip is further improved.
Description
Technical field
The invention belongs to technical field of semiconductors, specifically, relate to a kind of SRAM detection architecture, domain and forming method thereof.
Background technology
Along with the continuous progress of semiconductor fabrication node, the through hole occurring in back-end process or metal Joint failure become a main cause that affects product yield.The present inventor finds realizing in process of the present invention, in a certain test, in failure analysis, finds to have a Via-1 through hole of not opening, thus the reason that causes sram chip to lose efficacy.But, in being used for monitoring the whether normal test structure of Via-1 through hole, do not find this problem.According to conventional monitoring principle, the chain structure being formed by Via-1 and M2, if there is Via-1 not open, the M2 impedance Rs measuring so will be a very large numerical value.But to test out be but normal to M2 Rs in this example, that is to say and in being used for monitoring the whether normal test structure of Via-1 through hole, do not monitor the problem that the through hole of similar sram chip the inside is not opened.
Trace it to its cause, the present inventor's discovery, Via-1 monitoring of structures and sram chip physical structure have very large difference.As sram chip has comprised the levels such as Poly/CT/M1/Via-1/M2 from substrate to M2, and Via-1 detection architecture does not have Poly/CT, in unsettled state.In this case, after interlayer dielectric layer CMP technique because the difference of fabric can cause forming between sram chip region and Via-1 detection architecture a difference in height.This difference in height can be always in follow-up through hole and Metal Bonding Technology exists, and in Via-1 photoetching process, in the time that the focusing situation in detection architecture region is optimum, the focusing situation in sram chip region is probably because of this difference in height and in unoptimizable state.The result finally causing is exactly that Via-1 in detection architecture can normally open, but the phenomenon that Via-1 does not open has but appearred in SRAM region.
As can be seen here, in prior art, test structure can not be monitored the situation of actual sram chip accurately.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of SRAM detection architecture, domain and forming method thereof, in order to improve the monitoring precision of test structure to actual sram chip.
In order to solve the problems of the technologies described above, the invention provides a kind of formation method of SRAM detection architecture domain, it,, from plane domain design angle, comprising:
According to the regularity of sram chip domain, determine and in a first metal layer figure, need the part connecting and do not need the part connecting;
Disconnect the part that does not need connection in a described the first metal layer, by increasing another metal layer image, the part connecting in a described the first metal layer is coupled together;
Taking a described the first metal layer layer and the first connecting through hole as basis, redesign the second metal layer image, to connect adjacent described the first connecting through hole.
Preferably, in one embodiment of this invention, also comprise: from physical layer angle, shallow channel is set in substrate, and contact hole is directly dropped in described shallow channel, on described contact hole, form successively described the first metal layer, described the first connecting through hole and described the second metal level.
Preferably, in one embodiment of this invention, also comprise: at shallow channel, contact hole described in the chip testing region division of SRAM, so that the physical layer architecture in the physical layer architecture in sram chip region and chip testing region is in same vertical height place.
In order to solve the problems of the technologies described above, the invention provides a kind of SRAM detection architecture, it is characterized in that, comprise: substrate, shallow channel, contact hole, described the first metal layer, described the first connecting through hole and described the second metal level, described shallow channel is arranged in described substrate, described contact hole directly drops in described shallow channel, forms successively described the first metal layer, described the first connecting through hole and described the second metal level on described contact hole.
Preferably, in one embodiment of this invention, described shallow channel, contact hole are arranged on the chip testing region division of SRAM, so that the physical layer architecture in the physical layer architecture in sram chip region and chip testing region is in same vertical height place.
In order to solve the problems of the technologies described above, the invention provides a kind of SRAM detection architecture domain, it is characterized in that, in the first metal layer figure, need the part connecting to be connected by increasing another metal layer image, in the first metal layer figure, do not need the part connecting to disconnect, the second metal layer image is taking a described the first metal layer and the first connecting through hole as basis through redesigning, and described the second metal level connects the first adjacent connecting through hole.
Compared with existing scheme,, determine and in a first metal layer figure, need the part connecting and do not need the part connecting according to the regularity of sram chip domain due to first; Secondly, disconnect the part that does not need connection in a described the first metal layer, by increasing another metal layer image, the part connecting in a described the first metal layer is coupled together; Finally, taking a described the first metal layer layer and the first connecting through hole as basis, redesign the second metal layer image, to connect adjacent described the first connecting through hole.Therefore, avoid after interlayer dielectric layer CMP technique because the difference of fabric can cause forming between sram chip region and Via-1 detection architecture a difference in height, in Via-1 photoetching process in the time that the focusing situation in detection architecture region is optimum, the focusing situation in sram chip region is the state in optimizing also, Via-1 in detection architecture can normally open, the phenomenon that SRAM region Via-1 also normally opens, has improved actual sram chip monitoring precision.
Brief description of the drawings
Fig. 1 is the formation method flow schematic diagram of the embodiment of the present application one SRAM detection architecture domain;
Fig. 2 is the schematic diagram of the embodiment of the present application two sram chip domains;
Fig. 3 is the embodiment of the present application Three S's RAM detection architecture domain;
Fig. 4 is the physical layer schematic diagram of the embodiment of the present application five SRAM detection architecture.
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment, technical scheme of the present invention is at length set forth.Should be appreciated that, the embodiment below enumerating is only for description and interpretation the present invention, and do not form the restriction to technical solution of the present invention.
the application's core concept one:
The formation method of the SRAM detection architecture domain that the following embodiment of the application provides, its core concept is, from plane domain design angle, comprising:
According to the regularity of sram chip domain, determine and in a first metal layer figure, need the part connecting and do not need the part connecting;
Disconnect the part that does not need connection in a described the first metal layer, by increasing another metal layer image, the part connecting in a described the first metal layer is coupled together;
Taking a described the first metal layer layer and the first connecting through hole as basis, redesign the second metal layer image, to connect adjacent described the first connecting through hole.
the application's core concept two:
The SRAM detection architecture that the following embodiment of the application provides, its core concept is, comprise from physical layer angle: substrate, shallow channel, contact hole, described the first metal layer, described the first connecting through hole and described the second metal level, described shallow channel is arranged in described substrate, described contact hole directly drops in described shallow channel, forms successively described the first metal layer, described the first connecting through hole and described the second metal level on described contact hole.
the application's core concept three:
The SRAM that the following embodiment of the application provides detects domain, its core concept is, comprise from plane domain angle: the first metal layer figure, need the part connecting to be connected by increasing another metal layer image, in the first metal layer figure, do not need the part connecting to disconnect, the second metal layer image is taking a described the first metal layer and the first connecting through hole as basis through redesigning, and described the second metal level connects the first adjacent connecting through hole.
Fig. 1 is the formation method flow schematic diagram of the embodiment of the present application one SRAM detection architecture domain; As shown in Figure 1, it specifically can comprise:
S101, according to the regularity of sram chip domain, determine and in a first metal layer figure, need the part connecting and do not need the part connecting;
Fig. 2 is the schematic diagram of the embodiment of the present application two sram chip domains; As shown in Figure 2, sram chip domain is regular repetition, such as: the figure referring to the each level of Fig. 2 is.The minimum unit repeating is called bit, i.e. a byte.For the first metal layer Metal-1201 in Fig. 2 and the first connecting through hole Via-1202.As shown in Figure 2, two wire frame A, B have marked respectively two bytes.The figure that wire frame A comprises toward left and right and above the upset of mirror image, can obtain the left and right and figure of three directions above.In like manner, wire frame B toward left and right and below the upset of mirror image, can obtain the left and right and figure of three directions below.
In the time of the part of determining coupling part and do not need to be connected, taking the first connecting through hole Via-1 figure of horizontal direction as basic, the second metal level metal-2 on upper strata and the first metal layer metal-1 of lower floor are coupled together as primitive rule.
S102, disconnect and in a described the first metal layer, do not need the part that connects, by increasing another metal layer image, the part connecting in a described the first metal layer is coupled together;
Fig. 3 is the embodiment of the present application Three S's RAM detection architecture domain; As shown in Figure 3, the first connecting through hole representing taking digital 1-7 in scheming carries out exemplary illustration as example.
As shown in Figure 3, need to disconnect and need the rule that be connected to be exactly ", taking the Via-1 figure of horizontal direction as basis, the metal-1 of the metal-2 on upper strata and lower floor is coupled together ".Such as I have marked this line of 1～7 these numerals, 1 and 2 the first connecting through holes 202 that represent originally exist but disconnect each other, in like manner 6 and 7 the first connecting through holes 202 existence originally that represent but disconnect each other; Therefore be, that the second metal level metal-2 couples together by the black surround shown in Fig. 3.The local the first metal layer metal-1 of 3,4,5 these three of representing disconnects originally, so add 3,4,5 these three the first metal layer metal-1 figures that represent, a continuous the first metal layer metal-1 figure is coupled together 2,6 these two Via-1.Through above-mentioned processing, whole this line has just formed a path from leftmost the first connecting through hole Via-1 " 1 " to rightmost Via-1 " 7 ", has reached the object connecting.
S103, taking a described the first metal layer layer and the first connecting through hole as basis, redesign the second metal layer image, to connect adjacent described the first connecting through hole.
The second layer metal figure domain redesigning is referring to above-mentioned Fig. 3.
Fig. 4 is the physical layer schematic diagram of the embodiment of the present application five SRAM detection architecture; As shown in Figure 4, it can comprise: substrate 401, grid 402, shallow channel 403, contact hole 404, the first metal layer 405, the first connecting through hole 406 and described the second metal level 407, described grid 402 and shallow channel 403 are arranged in described substrate 401, described contact hole 404 directly drops in described shallow channel 403, forms successively described the first metal layer 405, described the first connecting through hole 406 and described the second metal level 407 on described contact hole 404.
In the present embodiment, at shallow channel 403, contact hole 404 described in the chip testing region division of SRAM, so that the physical layer architecture in the physical layer architecture in sram chip region and chip testing region is in same vertical height place.
Above-mentioned explanation illustrates and has described some preferred embodiments of the present invention, but as previously mentioned, be to be understood that the present invention is not limited to disclosed form herein, should not regard the eliminating to other embodiment as, and can be used for various other combinations, amendment and environment, and can, in invention contemplated scope described herein, change by technology or the knowledge of above-mentioned instruction or association area.And the change that those skilled in the art carry out and variation do not depart from the spirit and scope of the present invention, all should be in the protection range of claims of the present invention.
Claims (6)
1. a formation method for SRAM detection architecture domain, is characterized in that, from plane domain design angle, comprising:
According to the regularity of sram chip domain, determine and in a first metal layer figure, need the part connecting and do not need the part connecting;
Disconnect the part that does not need connection in a described the first metal layer, by increasing another metal layer image, the part connecting in a described the first metal layer is coupled together;
Taking a described the first metal layer layer and the first connecting through hole as basis, redesign the second metal layer image, to connect adjacent described the first connecting through hole.
2. method according to claim 1, it is characterized in that, also comprise: from physical layer angle, shallow channel is set in substrate, and contact hole is directly dropped in described shallow channel, on described contact hole, form successively described the first metal layer, described the first connecting through hole and described the second metal level.
3. method according to claim 2, it is characterized in that, also comprise: at shallow channel, contact hole described in the chip testing region division of SRAM, so that the physical layer architecture in the physical layer architecture in sram chip region and chip testing region is in same vertical height place.
4. a SRAM detection architecture, it is characterized in that, comprise: substrate, shallow channel, contact hole, described the first metal layer, described the first connecting through hole and described the second metal level, described shallow channel is arranged in described substrate, described contact hole directly drops in described shallow channel, forms successively described the first metal layer, described the first connecting through hole and described the second metal level on described contact hole.
5. detection architecture according to claim 4, it is characterized in that, described shallow channel, contact hole are arranged on the chip testing region division of SRAM, so that the physical layer architecture in the physical layer architecture in sram chip region and chip testing region is in same vertical height place.
6. a SRAM detection architecture domain, it is characterized in that, in the first metal layer figure, need the part connecting to be connected by increasing another metal layer image, in the first metal layer figure, do not need the part connecting to disconnect, the second metal layer image is taking a described the first metal layer and the first connecting through hole as basis through redesigning, and described the second metal level connects the first adjacent connecting through hole.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410357261.9A CN104091800A (en) | 2014-07-25 | 2014-07-25 | Forming method for SRAM detection structure map |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410357261.9A CN104091800A (en) | 2014-07-25 | 2014-07-25 | Forming method for SRAM detection structure map |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107885939A (en) * | 2017-11-09 | 2018-04-06 | 上海华力微电子有限公司 | A kind of method for improving monitoring pattern monitoring precision |
| CN110852029A (en) * | 2018-07-27 | 2020-02-28 | 熠芯(珠海)微电子研究院有限公司 | Semiconductor chip and layout design method and device thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1635638A (en) * | 2003-12-30 | 2005-07-06 | 中芯国际集成电路制造(上海)有限公司 | Multiple metal layer SRAM memory used as testing apparatus |
| WO2009090517A2 (en) * | 2008-01-14 | 2009-07-23 | Nxp B.V. | Redundant chain test structure for precise contact/via fail rate measurement |
| US20130163312A1 (en) * | 2011-12-22 | 2013-06-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Sram timing tracking circuit |
| CN104425293A (en) * | 2013-08-26 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Test structure for monitoring open circuit situation of SRAM through hole, and formation method thereof |
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2014
- 2014-07-25 CN CN201410357261.9A patent/CN104091800A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1635638A (en) * | 2003-12-30 | 2005-07-06 | 中芯国际集成电路制造(上海)有限公司 | Multiple metal layer SRAM memory used as testing apparatus |
| WO2009090517A2 (en) * | 2008-01-14 | 2009-07-23 | Nxp B.V. | Redundant chain test structure for precise contact/via fail rate measurement |
| US20130163312A1 (en) * | 2011-12-22 | 2013-06-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Sram timing tracking circuit |
| CN104425293A (en) * | 2013-08-26 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Test structure for monitoring open circuit situation of SRAM through hole, and formation method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107885939A (en) * | 2017-11-09 | 2018-04-06 | 上海华力微电子有限公司 | A kind of method for improving monitoring pattern monitoring precision |
| CN107885939B (en) * | 2017-11-09 | 2020-12-04 | 上海华力微电子有限公司 | Method for improving monitoring precision of monitoring graph |
| CN110852029A (en) * | 2018-07-27 | 2020-02-28 | 熠芯(珠海)微电子研究院有限公司 | Semiconductor chip and layout design method and device thereof |
| CN110852029B (en) * | 2018-07-27 | 2023-11-17 | 熠芯(珠海)微电子研究院有限公司 | Semiconductor chip and layout design method and device thereof |
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Application publication date: 20141008 |