JP2015041400A - Laminated semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect a faulty connection between semiconductor chips which are mutually connected via a through electrode.SOLUTION: A laminated semiconductor device includes a semiconductor chip 21 and a semiconductor chip 25. The semiconductor chip 21 includes: a memory cell array 31 that includes a plurality of memory cells MC; and a replica output circuit 35 that outputs a test signal TEST to a through electrode TSV irrespective of data stored in the memory cell array 31. The semiconductor chip 25 includes: an input terminal BB that is connected to the through electrode TSV; an output terminal FB; and a monitor circuit 46 that outputs a monitor signal MON to the output terminal FB on the basis of a test signal TEST received by the input terminal BB. According to this invention, a signal different from data, which is read from a memory cell array, is transmitted via a through electrode dedicated for testing, thereby allowing an accurate evaluation of a faulty connection irrespective of whether or not the memory cell array is defective.

Description

  The present invention relates to a stacked semiconductor device, and more particularly to a stacked semiconductor device in which a plurality of semiconductor chips are connected to each other through through electrodes.

  In recent years, a packaging method called a multi-chip package is known as a technique for packaging a plurality of semiconductor chips at a high density. In a multi-chip package, a plurality of semiconductor chips are stacked on a package substrate, and each semiconductor chip and the package substrate are connected using bonding wires.

  However, since a large number of bonding wires are used in a multichip package, not only the planar size of the package increases by the area required for bonding, but also the signal quality deteriorates due to parasitic inductance components of the bonding wires. It was. In recent years, in order to solve such a problem, a stacked semiconductor device in which a plurality of semiconductor chips are connected to each other through a through electrode has been proposed (see Patent Document 1).

  The stacked semiconductor device described in Patent Document 1 includes a test circuit, and it is possible to test whether there is a defect in the memory cell array using the test circuit even after stacking.

JP 2011-82448 A

  By the way, in the stacked semiconductor device using the through electrode, since the semiconductor chips adjacent in the vertical direction are connected via the bump electrodes, there is a possibility that poor connection occurs when a planar positional shift occurs during stacking. . Such a connection failure can be detected by a test operation or the like.

  However, since the test circuit described in Patent Document 1 compresses and outputs read data read from the memory cell array, even if a failure is detected, this is caused by a connection failure. It was difficult to determine whether it was caused by a memory cell array defect.

  According to an aspect of the present invention, there is provided a stacked semiconductor device including a first memory cell array including a plurality of memory cells, a first through electrode, and a first through electrode connected to the first through electrode regardless of data stored in the first memory cell array. A first chip including a first output circuit that outputs one signal; an input terminal connected to the first through electrode of the first chip; an output terminal; and an input signal received by the input terminal. And a second chip including a monitor circuit that outputs an output signal to the output terminal.

  A stacked semiconductor device according to another aspect of the present invention includes a first chip and a second chip stacked on the first chip, and at least one of the first chip and the second chip is the chip. The first chip includes a memory cell array that stores user data, an access control circuit that performs an access operation on the memory cell array, A plurality of output buffers for outputting the user data read from the memory cell array; and a replica circuit for outputting a test signal supplied from the access control circuit, wherein the second chip includes a plurality of input buffers. A plurality of output buffers and a plurality of input buffers via the plurality of first through electrodes. The replica circuit and the monitor circuit are connected to each other via the second through electrode, and the replica circuit outputs a test signal to the second through electrode during a test operation. The monitor circuit generates a monitor signal by monitoring the test signal supplied through the second through electrode during the test operation, and outputs the monitor signal to the external terminal. To do.

  According to the present invention, since a signal different from the data read from the memory cell array is transmitted through the test-dedicated through electrode, the connection failure is detected regardless of whether the memory cell array has a defect. Accurate evaluation is possible.

1 is a schematic cross-sectional view showing an appearance of a stacked semiconductor device according to a preferred embodiment of the present invention. It is a block diagram for demonstrating the circuit structure of the semiconductor chips 21-25 by 1st Embodiment. 3 is a circuit diagram showing a configuration of a main part of an I / O circuit 34 and a replica output circuit 35. FIG. 4 is a schematic diagram for explaining a connection relationship between an output buffer ROB provided in semiconductor chips 21 to 25 and a monitor circuit 46. FIG. 3 is a circuit diagram of a monitor circuit 46. FIG. It is a block diagram for demonstrating the circuit structure of the semiconductor chips 21-25 by 2nd Embodiment. It is a block diagram for demonstrating the circuit structure of the semiconductor chips 21-25 by 3rd Embodiment. It is a schematic diagram for demonstrating the connection relation by the modification of the output buffer ROB and the monitor circuit 46 which were provided in the semiconductor chips 21-25 by 4th Embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic cross-sectional view showing the appearance of a stacked semiconductor device according to a preferred embodiment of the present invention.

  As shown in FIG. 1, the stacked semiconductor device according to the present embodiment includes semiconductor chips 21 to 25 stacked on the surface of the interposer 10. As an example, a wide I / O type dynamic random access memory (DRAM) can be used for the semiconductor chips 21 to 24 and a controller for controlling the DRAM can be used for the semiconductor chip 25. As another example, a so-called COC (Chip On Chip) is used for the semiconductor chips 21 to 24 using a core chip in which a DRAM back-end part is integrated, and for the semiconductor chip 25 using an interface chip in which a DRAM front-end part is integrated. A layered structure of molds can be used. In the example shown in FIG. 1, the planar size of the semiconductor chip 25 is smaller than the planar size of the semiconductor chips 21 to 24, but the present invention is not limited to this. Further, the type and number of stacked semiconductor chips are not limited.

  In this embodiment, all of the semiconductor chips 21 to 25 are mounted by the face-down method. The face-down method is a method in which a semiconductor chip is mounted so that a circuit formation surface on which a transistor or the like is formed faces downward, that is, faces the interposer 10 side. The semiconductor chips 22 to 25 are provided with through electrodes TSV that penetrate the chips, and the semiconductor chips 21 to 25 are connected to the interposer 10 through the through electrodes TSV.

  As shown in FIG. 1, the front surface bump FB is connected to one end of the through silicon via TSV, and the back surface bump BB is connected to the other end. The front surface bump FB is a bump electrode provided on the circuit forming surface side, and the back surface bump BB is a bump electrode provided on the back surface side.

  The front surface bump FB of the semiconductor chip located in the upper layer is connected to the back surface bump BB of the semiconductor chip located in the lower layer. In the present embodiment, since the face-down method is used, the semiconductor chip 21 located in the uppermost layer is not provided with the through electrode TSV and the back surface bump BB. In this case, it is preferable to make the thickness of the semiconductor chip 21 thicker than that of the semiconductor chips 22 to 24. According to this, the mechanical strength of the stacked semiconductor device can be increased, thereby preventing warpage. It becomes. However, the penetrating electrode TSV and the back surface bump BB may also be provided on the uppermost semiconductor chip 21. In this case, all the semiconductor chips 21 to 24 can be manufactured in the same process.

  The surface bump FB of the semiconductor chip 25 located in the lowermost layer is connected to the substrate electrode 11 provided in the interposer 10. The substrate electrode 11 is connected to an external terminal 13 provided on the back surface through a through electrode 12 provided in the interposer 10.

<First Embodiment>
FIG. 2 is a block diagram for explaining a circuit configuration of the semiconductor chips 21 to 25 and corresponds to the first embodiment. Since the semiconductor chips 21 to 24 have the same circuit configuration, the circuit configuration of the semiconductor chip 21 is representatively shown in FIG.

  As shown in FIG. 2, the semiconductor chip 21 includes a memory cell array 31 including a plurality of memory cells MC, and an access control circuit 32 that performs an access operation to the memory cell array 31. The access control circuit 32 is supplied with the internal command address signal CAint, and the access control circuit 32 performs a predetermined operation based on this. Although not particularly limited, the internal command address signal CAint includes a command signal, an address signal, a clock signal, and the like.

  When the internal command address signal CAint indicates a read operation, the read operation is performed by accessing the memory cell array 31. The read internal user data DQint is supplied to the I / O circuit 34 via the data control circuit 33 and output to the outside of the semiconductor chip 21 via the surface bump FB. When the internal command address signal CAint indicates a write operation, the write operation is performed by accessing the memory cell array 31. During the write operation, internal user data DQint input to the surface bump FB is supplied to the memory cell array 31 via the I / O circuit 34 and the data control circuit 33.

  Further, when the internal command address signal CAint indicates a test operation, the access control circuit 32 supplies the test signal TEST to the replica output circuit 35. In response to this, the replica output circuit 35 buffers the test signal TEST and outputs it to the semiconductor chip 25 through the through silicon via TSV. The test signal TEST is a signal different from the user data read from the memory cell array 31, and is directly supplied from the access control circuit 32 to the replica output circuit 35.

  On the other hand, the semiconductor chip 25 includes an access control circuit 41 that receives an external command address signal CAext supplied from the outside and generates an internal command address signal CAint. The access control circuit 41 serves to convert the external command address signal CAext to an internal command address signal CAint and supply it to the semiconductor chips 21-24.

  Further, the semiconductor chip 25 is connected between the I / O circuit 42 that inputs and outputs internal user data DQint, the I / O circuit 43 that inputs and outputs external user data DQext, and these I / O circuits 42 and 43. The data control circuit 44 is provided. With this configuration, during the read operation, internal user data DQint input from the semiconductor chips 21 to 24 to the I / O circuit 42 is supplied to the I / O circuit 43 via the data control circuit 44, and external user data DQext. Is output to the outside. In the write operation, external user data DQext input from the outside to the I / O circuit 43 is supplied to the I / O circuit 42 via the data control circuit 44, and the semiconductor chips 21 to 24 are used as the internal user data DQint. To be supplied. The data control circuit converts the internal user data DQint to the external user data DQext by performing parallel serial conversion or the like, and converts the external user data DQext to the internal user data DQint by performing serial parallel conversion or the like. .

  Further, the semiconductor chip 25 includes a replica output circuit 45. The replica output circuit 45 is a circuit similar to the replica output circuit 35 provided in the semiconductor chips 21 to 24, and outputs a test signal TEST under the control of the access control circuit 41.

  The test signal TEST is input to a monitor circuit 46 provided in the semiconductor chip 25. The monitor circuit 46 receives the test signal TEST, generates a monitor signal MON, and outputs it to the outside. The circuit configuration of the monitor circuit 46 will be described later.

  As shown in FIG. 2, the power supply potential VDD and the ground potential VSS are supplied to the circuit blocks 31 to 35 and 41 to 46 included in the semiconductor chips 21 to 25 as operation power supplies.

  The fuse circuits F1 and F2 are inserted in the power supply lines VL1 and VL2 that supply the power supply potential VDD. The replica output circuit 35 is supplied with the power supply potential VDD via the fuse circuit F1, and the replica output circuit 45 and the monitor circuit. 46 is supplied with the power supply potential VDD via the fuse circuit F2. Therefore, when the fuse circuits F1 and F2 are disconnected, the replica output circuits 35 and 45 and the monitor circuit 46 are disconnected from the power supply lines VL1 and VL2.

  It is not essential that the circuit blocks 31 to 35 and 41 to 46 use the same power source, and power sources having different voltages may be used for each circuit block.

  Furthermore, the electrostatic protection element M for preventing electrostatic breakdown due to ESD is connected to each terminal (front bump FB and back bump BB) provided on the semiconductor chips 21 to 25. However, as shown in FIG. 2, the electrostatic protection element M is not connected to the terminals corresponding to the replica output circuits 35 and 45 and the monitor circuit 46. For this reason, the replica output circuits 35 and 45 and the monitor circuit 46 may cause electrostatic breakdown due to ESD, but the test signal TEST and the monitor signal MON are not affected by the load of the electrostatic protection element M, and are more accurate. Monitoring becomes possible.

  FIG. 3 is a circuit diagram showing the configuration of the main part of the I / O circuit 34 and the replica output circuit 35.

  As shown in FIG. 3, the I / O circuit 34 includes buffer circuits BF0 to BFn provided for the bits DQ0 to DQn constituting the internal user data DQint. Each of the buffer circuits BF0 to BFn includes an output buffer OB that is activated during a read operation and an input buffer IB that is activated during a write operation, and the corresponding front surface bump FB (and back surface bump BB), data control circuit 33, and the like. Connected between. The buffer circuits BF0 to BFn are supplied with a power supply potential VDD and a ground potential VSS as operation power supplies.

  On the other hand, the replica output circuit 35 includes an output buffer ROB, and no input buffer is provided. The output buffer ROB is a replica of the output buffer OB and has the same characteristics as the output buffer OB. As described above, the replica output circuit 35 is connected to the power supply line VL1 through the fuse circuit F1, and the electrostatic protection element M is not connected to the corresponding terminal.

  The I / O circuits 42 and 43 provided in the semiconductor chip 25 also have the same circuit configuration as the I / O circuit 34 shown in FIG. Therefore, during the read operation, the internal user data DQint is output from the output buffer OB on the semiconductor chip 21 to 24 side and supplied to the input buffer IB on the semiconductor chip 25 side through the corresponding through electrode TSV. In the write operation, the internal user data DQint is output from the output buffer OB on the semiconductor chip 25 side, and is supplied to the input buffer IB on the semiconductor chips 21 to 24 side via the corresponding through silicon via TSV.

  The replica output circuit 45 provided in the semiconductor chip 25 also has a circuit configuration similar to that of the replica output circuit 35 shown in FIG. 3, and is configured by an output buffer ROB that is a replica of the output buffer OB.

  FIG. 4 is a schematic diagram for explaining a connection relationship between the output buffer ROB provided in the semiconductor chips 21 to 25 and the monitor circuit 46.

  As shown in FIG. 4, the output nodes of the output buffers ROB provided in the semiconductor chips 21 to 24 are respectively connected to the surface bumps FB of the semiconductor chip. These front surface bumps FB are connected to the through silicon vias TSV via the back surface bumps BB of the semiconductor chips 22 to 25 located in the lower layers. The through electrode TSV is connected to the surface bump FB of the semiconductor chip.

  With this configuration, the through silicon vias TSV, the front surface bumps FB, and the back surface bumps BB provided in the semiconductor chips 21 to 25 form one signal path as shown in FIG. This signal path is connected to a monitor circuit 46 provided in the semiconductor chip 25. The monitor circuit 46 monitors the test signal TEST supplied through the signal path, and generates the monitor signal MON based on the test signal TEST. The monitor signal MON is output to the outside through the surface bump FB of the semiconductor chip 25.

  Here, the output buffers ROB provided in the semiconductor chips 21 to 25 are activated exclusively. Thus, the test signal TEST output from each of the semiconductor chips 21 to 25 is supplied to the monitor circuit 46 in a time division manner. Such control can be realized by exclusively selecting the access control circuits 32 and 41 in the semiconductor chips 21 to 25 by using a predetermined signal (for example, a chip selection signal) included in the internal command address signal CAint. is there.

  FIG. 5 is a circuit diagram of the monitor circuit 46.

  As shown in FIG. 5, the monitor circuit 46 is connected to an N-channel MOS transistor N1 that receives a bias potential Vb at its gate electrode, an N-channel MOS transistor N2 that receives a test signal TEST at its gate electrode, and transistors N1 and N2. And a P-channel MOS transistor P0 having a gate electrode connected to the point. The current flowing through the transistor P0 is input to a current mirror circuit composed of P-channel MOS transistors P1 and P2, and the output current is output to the outside as a monitor signal MON.

  With this configuration, the current value of the monitor signal MON changes linearly according to the potential level of the test signal TEST. Therefore, if the current value of the monitor signal MON is detected using an external tester, the potential level of the test signal TEST can be accurately evaluated.

  A fuse circuit F2 is connected to the power supply line VL2 connected to the monitor circuit 46, and power is supplied to the monitor circuit 46 by setting the fuse circuit F2 to a non-cut state (conducting state) during a test operation. Thereafter, when the test is completed, the fuse circuit F2 is cut.

  The above is the configuration of the stacked semiconductor device according to the present embodiment.

  As described above, according to the present embodiment, since the test signal TEST is transmitted to the monitor circuit 46 via the through-electrode TSV dedicated to the test, when the connection between the upper and lower semiconductor chips is poor, For example, when there is a deviation between the planar positions of the front surface bump FB of the semiconductor chip located in the upper layer and the rear surface bump BB of the semiconductor chip located in the lower layer, it is possible to detect this by analyzing the monitor signal MON. Become. Further, since the monitor signal MON has an analog current waveform, it is possible to evaluate not only a simple path / failure but also how much the signal path is increased due to a connection failure.

  Moreover, in the present embodiment, since the test signal TEST that is different from the internal user data DQint read from the memory cell array 31 is used, a connection failure is caused regardless of whether or not the memory cell array 31 is defective. Accurate evaluation is possible. Further, it is not necessary to write test data to the memory cell array 31.

  In this embodiment, since the electrostatic protection element M is not connected to the replica output circuits 35 and 45 and the monitor circuit 46, the load of the test signal TEST and the monitor signal MON is reduced. As a result, a more accurate test can be performed. After the test is completed, if the fuse circuits F1 and F2 are disconnected, the replica output circuits 35 and 45 and the monitor circuit 46 are disconnected from the power supply lines VL1 and VL2, so that the replica output circuits 35 and 45 and the monitor circuit 46 are connected. The applied ESD does not propagate to other circuits.

<Second Embodiment>
FIG. 6 is a block diagram for explaining another circuit configuration of the semiconductor chips 21 to 25 and corresponds to the second embodiment.

  As shown in FIG. 6, in the semiconductor chips 21 to 25 according to the present embodiment, the electrostatic protection element M is connected to the terminals (front surface bump FB and back surface bump BB) corresponding to the replica output circuits 35 and 45 and the monitor circuit 46. In addition, the second embodiment is different from the first embodiment shown in FIG. 2 in that the fuse circuits F1 and F2 are omitted. Since other configurations are the same as those of the first embodiment, the same reference numerals are given to the same elements, and duplicate descriptions are omitted.

  In the present embodiment, since the electrostatic protection element M is also connected to the replica output circuits 35 and 45 and the monitor circuit 46, the power supply lines VL1 and VL2 are connected using the fuse circuits F1 and F2 even after the test. There is no need to separate. Thereby, the cutting operation of the fuse circuit becomes unnecessary and the chip area can be reduced.

<Third Embodiment>
FIG. 7 is a block diagram for explaining still another circuit configuration of the semiconductor chips 21 to 25, and corresponds to the third embodiment.

  As shown in FIG. 7, the semiconductor chips 21 to 25 according to the present embodiment are different from the second embodiment shown in FIG. 6 in that an evaluation circuit 47 is included in the monitor circuit 46. Since other configurations are the same as those of the second embodiment, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  The evaluation circuit 47 is a circuit that generates a digitized monitor signal MOND by performing analog-digital conversion on the monitor signal MON having an analog waveform. In the first and second embodiments, the monitor signal MON is supplied to the tester as an analog value. Therefore, the tester needs to evaluate the analog signal as it is, or after analog-digital conversion. However, in the present embodiment, since the digitized monitor signal MOND can be output to the tester, the processing on the tester side can be simplified.

<Fourth Embodiment>
FIG. 8 is a schematic diagram for explaining a connection relationship according to a modification of the output buffer ROB and the monitor circuit 46 provided in the semiconductor chips 21 to 25, and corresponds to the fourth embodiment.

  In the fourth embodiment shown in FIG. 8, individual signal paths are used for the test signals TEST output from the semiconductor chips 21 to 24, respectively. These four signal paths are connected to the monitor circuit 46 via a selection circuit 48 provided in the semiconductor chip 25. The selection circuit 48 connects one of the four signal paths to the monitor circuit 46 based on the selection signal S. The selection signal S may be sent from the access control circuit to the selection circuit 48.

  Even when such a configuration is used, it can be appropriately combined with the first to third embodiments described above, and the effects of the embodiments described above can be obtained.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

DESCRIPTION OF SYMBOLS 10 Interposer 11 Substrate electrode 12 Through electrode 13 External terminals 21-25 Semiconductor chip 31 Memory cell array 32 Access control circuit 33 Data control circuit 34 I / O circuit 35 Replica output circuit 41 Access control circuit 42, 43 I / O circuit 44 Data control Circuit 45 replica output circuit 46 monitor circuit 47 evaluation circuit 48 selection circuit BB back surface bumps BF0 to BFn buffer circuit F1, F2 fuse circuit FB surface bump IB input buffer M electrostatic protection element MC memory cell OB output buffer ROB output buffer TSV through electrode VL1, VL2 power line

Claims (13)

A first memory cell array including a plurality of memory cells; a first through electrode; and a first output circuit that outputs a first signal to the first through electrode regardless of data stored in the first memory cell array. A first chip including:
An input terminal connected to the first through electrode of the first chip; an output terminal; and a monitor circuit that outputs an output signal to the output terminal based on an input signal received by the input terminal. A stacked semiconductor device comprising two chips. A second memory cell array including a plurality of memory cells; a second through electrode; and a second output circuit that outputs a second signal to the second through electrode regardless of data stored in the second memory cell array. A third chip including,
The stacked semiconductor device according to claim 1, wherein the input terminal of the second chip is connected to the second through electrode of the second chip. The first chip further includes a first power line for supplying power to the first output circuit through a first fuse circuit,
The second chip further includes a second power supply line for supplying power to the second output circuit through a second fuse circuit,
In a first period of testing the first chip, the first and second fuse circuits are in a conductive state;
3. The stacked semiconductor device according to claim 1, wherein the first and second fuse circuits are non-conducting in a second period after the first period. 4.   4. The stacked semiconductor device according to claim 1, wherein the second chip includes a protection element that protects the monitor circuit. 5.   The said 2nd chip | tip is connected to the said output terminal, The evaluation circuit which produces | generates a digital value by carrying out analog-digital conversion of the said output signal which the said monitor circuit produced | generated is characterized by the above-mentioned. The stacked semiconductor device according to claim 1.   The stacked semiconductor device according to claim 1, wherein the monitor circuit of the second chip includes a current mirror configuration. A third memory cell array including a plurality of memory cells, a third through electrode, and a third output circuit that outputs a third signal to the third through electrode regardless of data stored in the third memory cell array. A fourth chip including,
The second chip is inserted between an input terminal connected to the first through electrode of the first chip and the monitor circuit, and an input terminal connected to the first through electrode of the first chip; 7. The circuit according to claim 1, further comprising: a selection circuit that connects a selected one of the other input terminals connected to the third through electrode of the fourth chip to the monitor circuit. The stacked semiconductor device according to claim 1. A first chip and a second chip stacked on the first chip;
At least one of the first chip and the second chip has a plurality of first through electrodes and second through electrodes provided through the chip,
The first chip includes a memory cell array that stores user data, an access control circuit that performs an access operation on the memory cell array, a plurality of output buffers that output the user data read from the memory cell array, and the access A replica circuit that outputs a test signal supplied from the control circuit,
The second chip has a plurality of input buffers, a monitor circuit, and an external terminal,
The plurality of output buffers and the plurality of input buffers are connected to each other via the plurality of first through electrodes,
The replica circuit and the monitor circuit are connected to each other through the second through electrode,
The replica circuit outputs a test signal to the second through electrode during a test operation,
The monitor circuit generates a monitor signal by monitoring the test signal supplied through the second through electrode during the test operation, and outputs the monitor signal to the external terminal. A stacked semiconductor device. An electrostatic protection element is connected between the plurality of output buffers and the plurality of input buffers,
9. The stacked semiconductor device according to claim 8, wherein an electrostatic protection element is excluded between the replica circuit and the monitor circuit.   9. The electrostatic protection element is connected between the plurality of output buffers and the plurality of input buffers, and between the replica circuit and the monitor circuit, respectively. Multilayer semiconductor device. The first chip further includes a first power supply line for supplying power to the plurality of output buffers and the replica circuit,
The second chip further includes a second power supply line for supplying power to the plurality of input buffers and the monitor circuit,
A first fuse circuit provided between the plurality of output buffers and the replica circuit is connected to the first power line.
11. The second fuse circuit provided between the plurality of input buffers and the monitor circuit is connected to the second power supply line. 11. Multilayer semiconductor device.   9. The monitor circuit includes a current mirror circuit through which an input current based on the level of the test signal flows, and an output current of the current mirror circuit is output to the external terminal as the monitor signal. The stacked semiconductor device according to claim 1.   The monitor circuit includes a current mirror circuit in which an input current based on the level of the test signal flows, and an evaluation circuit that generates the monitor signal by performing analog-digital conversion on an output current of the current mirror circuit. The stacked semiconductor device according to any one of claims 8 to 11.

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