CA1278100C - Dispositif et methode pour determiner le temps de stabilisation d'un bus de systeme de traitement de donnees - Google Patents
Dispositif et methode pour determiner le temps de stabilisation d'un bus de systeme de traitement de donneesInfo
- Publication number
- CA1278100C CA1278100C CA000528363A CA528363A CA1278100C CA 1278100 C CA1278100 C CA 1278100C CA 000528363 A CA000528363 A CA 000528363A CA 528363 A CA528363 A CA 528363A CA 1278100 C CA1278100 C CA 1278100C
- Authority
- CA
- Canada
- Prior art keywords
- system bus
- data processing
- processing units
- bus
- logic signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bus Control (AREA)
- Small-Scale Networks (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US82377486A | 1986-01-29 | 1986-01-29 | |
| US823,774 | 1986-01-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1278100C true CA1278100C (fr) | 1990-12-18 |
Family
ID=25239674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000528363A Expired - Fee Related CA1278100C (fr) | 1986-01-29 | 1987-01-28 | Dispositif et methode pour determiner le temps de stabilisation d'un bus de systeme de traitement de donnees |
Country Status (7)
| Country | Link |
|---|---|
| EP (1) | EP0290472A1 (fr) |
| JP (1) | JPH01501426A (fr) |
| AU (1) | AU7033687A (fr) |
| CA (1) | CA1278100C (fr) |
| ES (1) | ES2002950A6 (fr) |
| IL (1) | IL81423A (fr) |
| WO (1) | WO1987004827A1 (fr) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2657740A1 (fr) * | 1990-01-26 | 1991-08-02 | Sgs Thomson Microelectronics | Procede et circuit de commande d'un bus de sortie de circuit integre. |
| US6188249B1 (en) * | 1998-06-30 | 2001-02-13 | Sun Microsystems, Inc. | Asymmetric arbiter with fast signal path |
| US7203779B2 (en) * | 2002-01-30 | 2007-04-10 | Stmicroelectronics, Inc. | Fast turn-off slow turn-on arbitrator for reducing tri-state driver power dissipation on a shared bus |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4186379A (en) * | 1977-04-28 | 1980-01-29 | Hewlett-Packard Company | High-speed data transfer apparatus |
| US4249093A (en) * | 1978-09-06 | 1981-02-03 | Lockheed Electronics Co., Inc. | Multiple request arbitration circuit |
-
1987
- 1987-01-28 CA CA000528363A patent/CA1278100C/fr not_active Expired - Fee Related
- 1987-01-28 ES ES8700201A patent/ES2002950A6/es not_active Expired
- 1987-01-29 AU AU70336/87A patent/AU7033687A/en not_active Abandoned
- 1987-01-29 IL IL81423A patent/IL81423A/xx not_active IP Right Cessation
- 1987-01-29 EP EP87901790A patent/EP0290472A1/fr not_active Withdrawn
- 1987-01-29 JP JP62501334A patent/JPH01501426A/ja active Pending
- 1987-01-29 WO PCT/US1987/000181 patent/WO1987004827A1/fr not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| ES2002950A6 (es) | 1988-10-01 |
| AU7033687A (en) | 1987-08-25 |
| IL81423A (en) | 1991-06-10 |
| WO1987004827A1 (fr) | 1987-08-13 |
| IL81423A0 (en) | 1987-08-31 |
| EP0290472A1 (fr) | 1988-11-17 |
| JPH01501426A (ja) | 1989-05-18 |
Similar Documents
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| CA1275328C (fr) | Dispositif et methode pour repondre a une interruption dans un echange de signaux entre les sous-systemes d'un systeme de traitement de donnees | |
| CA1164573A (fr) | Controleur d'arbitrage permettant a plusieurs unites centrales de traitement d'avoir acces a une ressource commune | |
| WO1982002440A1 (fr) | Arbitre de bus synchrone | |
| JPS6015765A (ja) | 共通バスのアクセス制御システム | |
| KR100847366B1 (ko) | 컴퓨터 시스템에서 다중-레벨 인터럽트 방식을 구현하기위한 시스템 및 방법 | |
| US5473762A (en) | Method and system for pipelining bus requests | |
| CA1278100C (fr) | Dispositif et methode pour determiner le temps de stabilisation d'un bus de systeme de traitement de donnees | |
| US6347352B1 (en) | Computer system having a plurality of bus agents coupled to bus requesters wherein each bus agent includes an internal arbiter that selects one of the bus requests | |
| US4514728A (en) | Store group bus allocation system | |
| CA1149040A (fr) | Controleur d'arbitrage donnant acces a une ressource commune a plusieurs unites centrales | |
| JPH10177544A (ja) | 1次装置および2次装置に対するデータ・バスの許可を平等にする方法および装置 | |
| US5029076A (en) | Apparatus and method for providing a settling time cycle for a system bus in a data processing system | |
| EP0425181B1 (fr) | Circuit de préférence pour un système calculateur | |
| US5898847A (en) | Bus arbitration method and appparatus for use in a multiprocessor system | |
| EP0432463B1 (fr) | Système d'arbitrage distribué équitable pour accès à un bus de communication de données | |
| KR100694086B1 (ko) | 멀티 마스터 버스 시스템에서 우선순위 조정 방법 및우선순위조정 기능을 구비한 중재기 | |
| KR100606701B1 (ko) | 계층적 구조의 중재 시스템 및 이를 이용한 중재 방법 | |
| JP2000029820A (ja) | バス間制御方法ならびに装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKLA | Lapsed |