CA1278100C - Apparatus and method for providing a settling time cycle for a system bus in a data processing system - Google Patents
Apparatus and method for providing a settling time cycle for a system bus in a data processing systemInfo
- Publication number
- CA1278100C CA1278100C CA000528363A CA528363A CA1278100C CA 1278100 C CA1278100 C CA 1278100C CA 000528363 A CA000528363 A CA 000528363A CA 528363 A CA528363 A CA 528363A CA 1278100 C CA1278100 C CA 1278100C
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- Prior art keywords
- system bus
- data processing
- processing units
- bus
- logic signal
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bus Control (AREA)
- Small-Scale Networks (AREA)
- Multi Processors (AREA)
Abstract
ABSTRACT
In a data processing system in which a plurality of data processing units or subsystems exchange logic signal groups by means of a system bus, apparatus is provided to allow sufficient time to permit transients on the system bus to decay, thereby increasing the integrity of the data. When the logic signal groups are applied to the system bus via conducting and nonconducting transistors, the presence of a logic signal on the system bus immediately prior to the application of a set of logic signals from a different data processing unit can delay the on-set of conduction of the most recently activated transistors, thereby resulting in transients of long duration. To accommodate these long transient conditions, the application of the new set of logic signals can be delayed until the transients on the system bus have been attenuated. Apparatus is disclosed for prohibiting access to the system bus by any subsystem during the system clock cycle following a subsystem access or by preventing access to the system bus by subsystems determined by the subsystem having access during the prior system clock cycle.
In a data processing system in which a plurality of data processing units or subsystems exchange logic signal groups by means of a system bus, apparatus is provided to allow sufficient time to permit transients on the system bus to decay, thereby increasing the integrity of the data. When the logic signal groups are applied to the system bus via conducting and nonconducting transistors, the presence of a logic signal on the system bus immediately prior to the application of a set of logic signals from a different data processing unit can delay the on-set of conduction of the most recently activated transistors, thereby resulting in transients of long duration. To accommodate these long transient conditions, the application of the new set of logic signals can be delayed until the transients on the system bus have been attenuated. Apparatus is disclosed for prohibiting access to the system bus by any subsystem during the system clock cycle following a subsystem access or by preventing access to the system bus by subsystems determined by the subsystem having access during the prior system clock cycle.
Description
DEC~O
APP~RATUS AND METHO~ FOR PROVIDIN13 A
5ETTLIN~ TI~E CYCLE FO~ A SYSTEM BUS
IN A DATA PRO~ESSINl3 SYSTE~
~AC~ ROUND OF THE INVENTION
1. Field of the In~entien This inventi~n relates generally t~ data pr~cessing systems and more parti.:ularly to the e~.:han~e of l~yi. signals 4n a $ystem bus in the data pr4cessin~ system~ Ttle e~.-hange of lo~ic signals by means of a system bus .:an .:ompromise the integrity of the ~i~nal exchange unless provision is made to permit the transient si~nal conditions, re~ulting fr~m the activation and deactivati,~n ~f the driver circuits applying the si~nals to system bus? to come to equilibrium.
~escription of the ~elated Art ~ eferrin~ t,~ Fi~ure 1, a typi,:al data pr~,:essing system is sh,~wn. The data processing system incl~de~ at least ~ne ,entr~l pr~cessin~ unit 10 ~ or 11~, at least one input/,~utput devi,:e 13 ~h~r 1~)~ clt least cJme mem4ry unit lS and a system bus l~? coupling the plurality ~f units or subsystems ~f the data prc~cessing system~ The central processin~ unit processes ~r~ups ~f l~gic si~nals a.-~ r~iing to software and/~r firmware instructi-~ns~ The l~gic sir~nal groups to be pr4ce~seri are typic.~lly st-~red in the memory unit 15. A .:onscle unit 12 can be couple~ t4 the central processin~ unitCs~ and typically . . . . , ~ .
.
', ' ' .
' ~ D~ 6 includes the apparatus and stored instructi~ns to initiali~e the system and can act as a terminal during the operation of the data processing system. The input/~utput units provide the interface to the remainder of the data pr~cessin~ system to terminal units, ma~s storaye units, ,cmmunication unitsr and any other units to be coupled t~ the data processing system.
The detailed function of the units ,:oupled to the system bus is less important than the fact that these units operate autonomc,usly and ,:ommuni,:ate with the remainder of the data processing units primarily by means of the system bus.
~eferring next to Figure 2, the technique ~or applying ,-lgi,: signal5 to the system bus is illustrated. The system bus 1~3 is ,:ompromised of a multiplicity of ,:onductinc3 elements, lga thrc,ugh l9g. The conductimg elements, as the cycle times ~f the data prl~cessing systems have decreased, have acquired the characteristi~s of transmission lines and must, for example, be terminated in su,h a manner ~not sh,~wn) as to avoid reflecti,~ns. Each data pr~cessin~ ~nit that can apply signals tc, the system has a multiplicity of transistors ,oupled t,~ the system bus. For example, data processing system unit ~1 has the emitter elements of transistors 21a through 219 coupled to system bus conduct,3rs l9a through 19~ respe,_tively, while data pr,~cessing system unit 23 has the emitter elements of transistors ~a through ~39 also coupled tc, conducting elements 13a throuc~h l~b~ When data processing system unit ~l i5 t,3 pl~ce a clroup of logic signals on the system bus, the base terminals of the transistors that are to assume a first logi~
state are maintained at a high level ~ir~ wllich the associ~ted ~; ~
~E~O
transistors are ,onducting~, while the base elements of the transistor 5 that are to assume a second lo~ic state are maintaineJ at low level ~:in which the assel-iated transistors are in a nonc"ndu,:ting state).
It will be ,:lear that the transient conditions on the system bus that result frorn a change state ~,f conductivi~y of a ,:oupled tr~nsistor can remain for the lQn~th of time neerled fcr the propagation, whichever is lcnger~ of the signal Cl.~ from the data processing system unit establishin~ the l~gi,: state ~f the bus to the data proces5ing system units identifylng the state of the system bus, or ~.) from the unit releasiny the lc,gic state of the bus tcl the unit ~5) identifyin~ the state c,f the bus.
However, the transient conditions on the system bus can remain for a lon~er p2ri~d ,:,f time as ,:an be underst~orJ by referen,-e to Figure 3 and Fi~ure 4. When the initial state of the condu~:tor 13~.~ of the system bus is the first ~high) logic state in which the transistor 21x, associated with data pro.:essing subsystem, is in the conducting state, the voltac7e leveL alonc conductor l9fi is essentially c.~nstant, position 21 indil:ating the 1,~c~til~n l~n the system bus ,-ondul-tl~r ,~f data processing system unit 21 and pcsiticn ~ indicatirl~ the lo.:ati..n cn the system bus ~ ndu.:t~r of data pr~cessin~ system unit ~3. This c.~ndition is shown by the curve in Figure 4a.
When the nefit .:onse.:utiv~ state in the system is one in which transistc-r ~1~ is in a nonconducting state and transistc~r ~
is a :-~nducting state~ then, imme~iately after the new state is entered, tran~istcr ~1 is rendered nonconducting~ A5 shown in DEr-66c) the curve in Fir~ure 4b immediately after the new state is entered the low voltage level indicating the application of no logic level propagates alon~ the conductiny element lgx.
Turning now to the operaticn of the transistor -~3x the b~se of transistor ~3x has a voltage applied thereto to pla:e t~7is transistor in a _or)ductin~ state~ However because the signal resultin~ from :easing of the prior conductlon of transistor ~lx has not yet propagated to the position of transi~tor ~3~ on the system bus condul:tor tranYistor ~3x rnay not be in the conducting st~te even th~ugh the voltage level of the base i5 at a level where :ondul:tion of the transistor normally takes place. At a later time as shown in Figure 4c the effect of rend~rin~ transistor lx non:ondu~ting will have propagated to position 23~ Immediately thereafter as shown in Figure 4d transistor ~ be:omes condu~ting and a volta~e level si~nal is proFarJated al~nr~ the system bus ~~onduet-~r~ After a period of time the voltar~e level resulting from initiation of condu-tion of transistor ~x will reach position ~1 as shown in Figure 4e. Therefore it will be :lear that transient signal effe ts on the system bus can persist for a longer period than the time :al:ulated for the transients to propagate along the distan:e defined by the physi-al separation of the data processing ~ystern elernents.
It has been known in the related art to provide ~ timing :y:le for the data pro:essinl3 <3ystem that :an a comm:date the longest required time~ However the adjustment of t~e systr~m timin~ :y:le to the worst _ase :an be ineffi:ient be~-ause for sele ted types of access tc the system bus a plurality of bus DEI'~F,O
access cycles ,:an ,-~ccur from a single data pro essiny subsystem without interruption~ The excessively lontl system cycle ti~e would make su,-h a transfer of siynals unnecessarily long in addition to the overall eompromise of the system performance resulting from a lont3 system cycle time.
A need has therefore been felt for apparatus ancd method c,f operation f~r the system bus that would permit the cycle time of the data processing system to remain short while simultaneously permittil7g any transient conditions on the system bus to decayr thereby maintainin~ the inte~rity of loyic state imposed on the data pr,:":essing system bus.
SUMMA~Y OF THE INVENTION
It is an obje,:t of the present invention to proYide an improved data processin~ unit.
It is a further object of the present invention to provide a ci.~ta pro,:essin~ system that ,-an provide for variable delays in the decay of tr~nsient conditic,ns on the system bus.
It i5 a particular object c~f the present invention to provide a delay in the ac,:ess of the system bus by a newly sele,:ted data prol:essin~ subsystem that i5 determined by the data pro,essiny subsystem havin~ system bus a~,:ess duriny the pri,~r system cll~,:k cycle.
It is a more partlcular ,~bject of the present invention, in a data processiny system in whi,:h conducti,~n of a first transistor ,:oupled to a system bus can delay the cclnduction of a se,:ond transistor coupled to the system bus, to provide s ~7~
66822~~5 apparatus for eliminating the effect of the interaction of the two transistors without increasing the system clock cycle.
The aforement:Loned and other objects are accomplished, accorcling to the present lnvention, by coupllng the data processlng ~ubsystems to a control unlt and by manipulzlting output sirJnal.s from an arhitration wnit itl a manner to provlcle aclditional time prior to application of the control unit signals when predetermined conditions are present. The arbitration unlt receives signals from each subsystem as the subsystem requires access to the system bus. In the event of conflict between two subsystems, the arbitration unit resolves the conflict according to an algorithm associated with a decision network device in the control unit. Accordiny to one embodiment o~ the present invention, associated with the arbitration unit ls apparatus tha~
permits the Request siynals to be disabled ~or a perlod of time prior ko the application of the Request signal to the decision network after any prior access to the system bus. According to a second embodiment of the present invention, the application of the Enable signal to a clata processin~ subsys-tem determined by the decision networlc can be delayed ~or selected subsystems, the remalning subsystems receiviny the ~nable siynal during -the present clock cycle. ~n thLs embod:lment, apparatus can be addecl to redetermine the suhs~stem receiving the ~nable siynal after a delay in the yenerat:Lon of the s:Lynal.
The inven~ion may be summarizecl, according to one aspect, as a data processing system, comprising, a system bus for carrying transmitted logic signal yroups having a transient time 66822-~5 period equal to the time for said logi~ signal groups ~ransmitted on said system bus to stabilize; A first data processing unit and a second data processlny unit coupled to said system bus, each of said ~irst and se~orld datc, processiny units in~ludingt means for transmitkiny lOCJ:IC slynal cJroUpS on sald system bus, and means for yenerakLng hus rec~les~ signals; central arbitration means coupled to sald firs~ and second data processlng units for permitting said ~irst and second d~ta processiny unlts to successlvely gain access to sald system bus including: declc:ion means for determining which of said 1rst and second data processiny units is permitted to gain access to said system bus in succession in response to said bus request signals and for generating one o~ a first enable signal and a second enable signal corresponding to said first and second data processing units respectively, means for generating an lnhibit signal ln response to generation of one of said first and second enable signals, sald inhibit signal generation means generating said inhibit sLgnal after generation of said one of said first and second enable slgnals for a period of time at least equal to the transient time period for logic signal groups transmitted by a preceding data processing unit permitted to gain successive access to the system bus; and means for inhib:Ltlng the trelnsmi~sion of successive bus request s.tgnals to sald declsion means ln response to an inhibit signal.
AccordincJ to another aspect, the invention provldes the method of controlllng the appllcation of logic signal yroups from data processing un:Lt~ ol a data processing system havlng a central arbitration unit to a system bus compr:lsing the steps of t 6~822~8S
determininy, by said central arbitration un.it, a one of said data processing units to be granted access to said system bus in order to apply a logic signal qroup to said system bus; generating, by said central arbitration un:Lt, a signal enabling said one of said data process:Lng units to gain access to said syetem bus; and pxevent.ln~ cJeneratlon of a slynal enabllng one of the remainlng clata processinq units to ga:Ln accese to said ~ystem bus during a system alock cycle following an aacess to said system bus.
These and other features oE the presenk invention will be underskood upon recadiny of the following description alonq with the drawings.
DEC~F.O
~2~
~IEF DESI~RIPTION OF THE DRAWIN13S
FI~. 1 i5 a block diagram of the components c~f a data pro,-essing system ,:apable ~f utilizing the present invention.
FI13~ ~ is a schematic diacgram c,f the c~upling ,~f units of the ciata processinc~ system to the system bus by means of transistc,rs.
Fl~. 3 is a s,:hematic dia~ram c~f the couplincl of twc~
transist,~rs to a ~:ondu,-tor in the system bus.
FIG. 4 is a diagrammatic representation of the si~nal levels on a system bus during the transitil~n from appli,-ation of a lc~gic sic~nal clrc,up by one data processiny system unit to an appli.-ation of a logi,- signal ~roup by a se~ond data processinc~ system unit t,~ the system bus.
FIO~. 5 i5 a blol-k diagram ,~f a data pr,~,-essin~ system ha~inc~ a unit tc, determine the next data prc,cessin~ subsystem t,~ apply a l.~gic siynal group to the system bus.
FI13. 6 is a block diac~ram of the apparatus for disabling the applicati,~n ,~f the loc~ic signal c~rl~up for a timing cycle.
FI13. 7 is a bloc~: diacJram of apparatus f,~r controlling the delay of applicati,3n of logic signal ~roups to the system bus determined by the partlcular ciata processinc~ subsystem havinc7 the last access~
DETAILED DESCF.:IPTION QF THE P~EFE~:ED EM~ODIMENT
1. Detailed Ves,:ripti,~n of the Figures ~78~ DF ~
Fi~ure 1 Fi~ure 2 Fi~ure 3 and Fiyure 4 have previously been des~ribed.
~ eferring ne~t to Fic~ure 5 the data pro~ssincl system ancl the data pro:essing subsystems as sh~wn and des:ribed with reference to Fi~ure 1 ls illustrated. In addition an arbitrati~n unit 5~ is indi:ated that :an control the appli~aticn oF the c~rjups of lor~ic signals to the system bus.
Su:h an apparatus i5 a c~ntr~1 unit that :an be referred t~ as a system bus arbitration unit cne su-h apparatus is des-ribed in U. S. Patent 4 7~3 7~1; entitled ~istributed ~rbitration Cireuitry for ~ata Processinr~ Systems; assir~ned to tl7e assir~nee of the present Patent Appli:ation. In the preferrecl embo~iment utili~ing central arbitration a eentralized arbitration unit 50 operates in the following manner~ When any of the subsystems has the requirem~nt that the subsystem must pla~e a ~roup of logil~ sir~nals on the system bus a Request lo~ic siClnal i5 applied to a mechanism couplinr~ the data pr~cessin~
subsystem and the arbitrati n unit 50. In the simplest situation the d~ta pr~cessincl sLlbsystem and the arbitration unit 5l~ are couplec1 by a cl~nductor a lorJi- siclnal ~pplied thereto indieatincl not only the presen:e -f a Request for a~cess to the system bus but als~ the identity l:f the subsystem requesting the access~ ~ased on an alr~rithrn preveriting monop~ly of ~he ;ystrm bu!3 by a partil:ul~r subsystem assignin~ prioritie~ to the various data pr~ces~inr~
unit subsystems~ and takin~ a:~:ount of any other fa:t~r deemed important in the acce~s to the system bus the arbitration unit 50 (ietermines the ne~t data pro:essinc~ subsystem to have a~:eess DE ~ 6 0 ~27~
to the system bus, and an Enable lo~i- si~nal is applied to the selected subsystem by a coupliny means, typically a condu,_t,3r.
The presen,e of this Enable logic siynal ,-ommuni~ates t" the selected data pro,-essiny subsystem that the 14~ic signal ~r~up can be applied to the system bus. The sele~ted subsystem can apply a Hl~ld lo~ic signal to the arbitration unit S~. Tlle Hold logi, si~nal i5 used in those situati4ns where the sele,:ted data pro,:essin~ subsystem must apply a plurality of logil-signal groups in sequen,:e to the system bus. The H~ld si~nal prevents the Enable signal frc,m bein~ removed from the s~lected data pr~,-essin~ subsystem until the ne~essary system clol:k cyc]es have passed for the plurality of related 14gir signal greups t~ have been applied to the system bus.
~ eferrin~ ne~t to Figure 6, the apparatus for preventing the appli,:ation of the Enable loyil- siynals to the sele,ted subsystem i5 shown. The arbitration unit 50 ~an re~eive Re~uest signals and Hold signals fr,3m the data pro,:essiny subsystems requiring ac~ess to the system bus. The Hold siynals are ,:oupled direl:tly t~ the de,:ision network 61 at terminals associated witll tlle particular data processin~
subsystem issuin~ the Hold si~nal. The ~equest line fr:,m ea,-h data pr~ essin~ subsystem is ~oupled to the first input terminal of a loyi,- AhlU yate G2a throuyh 62x associated with the data pr"cessin~ subsystem~ The output terminal~ clf the loyic AND yates ~2a thr4u~h 6~x are ,:oupled directly to terminals c,f th~ decision network 61 associated with the ~equest siynal line s data pro,:e~siny system. The output terminals of the decisi~n network 61 are c~upled t~ conducting ~EU6~0 ~78~
paths that apply the Enable si~nals to the associated dat processing sub~ystem. Each Enable line is also cc~upled t,~ an input terminal of logil: "NO~" gate ~3. The output terminal of ICJ9iC llNn~l gate ~3 i5 cc.upled to an input terminal of a one cy,:le delay netw,~rk &~, while the output terminal of one .:y,-le delay network 6~ i5,oupled to a second input terminal of each ,~f the logil~ "AN~" gates 6~:a tc~ ~-'`fi.
Referring next to Fi.gure 7, a block diagram is s~lown ~f apparatus for pr~vidingt t~ a ~;elected dat~ pr~cessing subsystem, an Enable signal that ._an be delayed when one of a gr.~up ,:,f preselected subsystems received an Enable signal durin~ a pr~vious timing ,-ycle. Each .~utput terminal of the decision netw~rk 61 is coupled to an input terminal of a delay network 7~a thr~ugh 7~x and a first input terminal ~f lc~ic "AND" yates 71a through 71x respe,tively~ E~ch second input terminal of logic "AND" gates 71a through 7ix~ is ~oupled t,-, an output terminal of ll~gil- "NOR" gate 7~a through 7~x respectively~ The ~-JUtpUt terminals of the delay networks 7~'a through 7~x are coupled to input terminals ~f logic "0~" gates 71a through 71x according t.~ the foll,-lwing relationship. When the two subsystems shoulli be activated cl:,n~el:utively only after a delay t,:, av.~id settlin~ time problems, t~e ~utp~t terminals c~f the delay networks asscl,:iated with the twc, subsy~tems sh~uld be coupled to the input terminal of the lc.gi.. "0~" gate associated with the .~ther subsystem. In this manner, the s~bsystems that sh~uld have a delay between ~c~~esses t.~ the system bus ~re insured .~f an enf.~r.ed delay~
.
~E1~6 . Operation ,f the Preferred Embodiment The use of the system bus in data pr~essin~ systems provides flexibility in ~-onfiyuration of the 6ystem. Data pr,seessing subsystems ean be added sr removed from the system relatively easily. However, thQ pri,:e ,~f this flexibility is that the time rr*quired to transfer l~,gi,- si~nal groups from one data pr,s,:essing system .:omp,-.nent unit t.s a se~.lnd is nlst precisely known, but ,:an be determined ,~nly within ,~ertain lirnits. The present inventl,sn permits the data pr.slessin~
system t~ a~csmmodate a l~sng settling time f,sr transients on the system bus. The prin.-iple of delayin~ the initiati,~n of the control s~gnal permitting ac,_ess to the system bus can be used in syn.-hr,sn,sus ~r nonsyn,:hronous data proeessing systems.
In the synehr~nous data pr.~essing systems in whil-h the ,-locking ,-y.:les are syn.-hroni~ed f~sr eaeh data pro.:essin~
subsystem, the a._tivation of the system bus ae.~ess control or enable signal .-an be delayed by ~sne .-.r m.sre system .-l...:k .-yeles. The present invention can be used as part .~f an arbitration unit. The arbitrati~sn unit is employed in a data pr~eessing system to reslslve confli-ts between tle data pro.-essin~ suhsystems f.sr a~cess t-s the system bus and t.s insure that one subsystem does not msn~poli~e the system bUCi.
In additi.-.n, in data pro~essing systems in whi.:h ..-onse.:utive system bus ac~esses are provided t~ e~pedite ~ertain signal ~r.~up tran~;fers, the arbitration unit .:an be resplsn~aive t.s the Hold signals, permittin~ the subsystem to maintain a.:cecis f..r e.snse.:utive ~l.s.:k .:ycles, and delay issuanee sf a .:~sntr~sl si~nal until the .:onsecutive a~.-ess pro,:edure has been DEu660 ~:ompleted.
~ eferring ~nce a~ain to Figure ~, it will be clear that the primary operation of netw~r~ ~4 is the delay of the Enable signal for one eycle by preventing appli,:ati,-,n ,~f the ~equest siynal to the de,-ision networlc 61 in the first embodiment. In the embodiment shown, the delay i5 f~r one cycler however other delay periods can be easily a,-rommodated. Upon generati,~n of an Enable signal~ the delay network ~4 delays a lcl~ic signal f"r one cycle and then applies a negative logil signal to the input terminal of all the logic AN~ gates 6~a to 6~Y~, thereby disablin~ the ll~(~il- AND ~ates until l~ne ~y~:le after the Enable signal is reml~ved from the ~utput terminals of the de,-ision network 61. When no Enable signal is applied to the output terminals of decision network ~1~ a pcsitive lo~i~
signal is applied to the output terminal of logil: NOF ~ate 63. One cycle later, the positive logil signal is applied, via delay netwl~rk 64, to the second input terminal of the lo~ic AN~ ~a~es ~a through ~?y~ and enables the logic AND gates.
The enabled l~gi- AND gates therefore ~-an transmit the Request siclnals to the decision network for determining the neYt data processin~ system to have a,:,:ess t,~ the system bus.
The foregoiny apparatus provides a unif~rm ~one cy,:le) delay after the ~eneratic,n of ea~:h Enable signal. I-lowever, it ,:an be desirable, in order t~ inerease the bus a~tivity~ to establish that, f~r sele~.ted data proces3ing subsystems, the delay in a,-cess to the system bus is not reqùired. In c,rder to implement a arbitration unit in which a delay can ~r ~:an not be required, the implementation illustrated in Fi~ure 7 ~an be l ~7 ~7~ DE~
used. The ceupling of the delay networks 72a through 7~x to the lo~ic "0~" ~ates 73a through 73x in the manner des~ribed previously delays the Enable sir~nal from passing throu~h t~
ass~ iated logic "A~" gate when one of the terminals asso,-iated with a preselected subsystem has been activated rJùring the previous timin~ cycle. The Enable si~nal is frad ba~k via its ass4ciated line 75a tilrough 75x in order to communicate to decision network 61 that the Enable si~nal issued. With this information, network 61 may update its priority state.
The apparatus for delayin~ the application of the Enable signal t,~ mpensate f4r system bus settlin~ times ~an either be performed on the in~~ominy Request signals clr ,-,n the Enable signals themselves. When the delay is imposed on the Enable signals and when de~isi~n network ~i makes priority decisions based upon previclus bus a,,ess suc,-ess, the actual transmission ~f the Enable signal must be communicated to t~e ~ecision network~
In the interactic,n by data pro,-essing subsystems wit~ the system bus, one m,~de of operati"n result~3 in a plurality of signal groups b~?ing applied t" the system bus ,-,n conse,-utive cy,les. T~le apparatus of the present invention is intended to provide a delay only when tl-e subsystem havinr~ access tc, the bus changes. For a multiplil:ity of sir~nal groups applied by a given subsystem to the system bus ,~n ,onsecutive ~lo~k cycles, only the ~irst si~nal group is delayed.
The foregoing descriptic~n is included t" illustrate the ,~peratlon "f the preferred embl~diment and is nc,t meant t" limit ~2~ DE1~6~(~
t~e s,-ope of the invention. The scope of the invention is to be limited only by the followin~ claims~ ~rom the fore~oin~
description many variations will be apparent to those skilled in the art that would yet be ~ncompassed by the spirit and s-ope of the invention.
1`~
APP~RATUS AND METHO~ FOR PROVIDIN13 A
5ETTLIN~ TI~E CYCLE FO~ A SYSTEM BUS
IN A DATA PRO~ESSINl3 SYSTE~
~AC~ ROUND OF THE INVENTION
1. Field of the In~entien This inventi~n relates generally t~ data pr~cessing systems and more parti.:ularly to the e~.:han~e of l~yi. signals 4n a $ystem bus in the data pr4cessin~ system~ Ttle e~.-hange of lo~ic signals by means of a system bus .:an .:ompromise the integrity of the ~i~nal exchange unless provision is made to permit the transient si~nal conditions, re~ulting fr~m the activation and deactivati,~n ~f the driver circuits applying the si~nals to system bus? to come to equilibrium.
~escription of the ~elated Art ~ eferrin~ t,~ Fi~ure 1, a typi,:al data pr~,:essing system is sh,~wn. The data processing system incl~de~ at least ~ne ,entr~l pr~cessin~ unit 10 ~ or 11~, at least one input/,~utput devi,:e 13 ~h~r 1~)~ clt least cJme mem4ry unit lS and a system bus l~? coupling the plurality ~f units or subsystems ~f the data prc~cessing system~ The central processin~ unit processes ~r~ups ~f l~gic si~nals a.-~ r~iing to software and/~r firmware instructi-~ns~ The l~gic sir~nal groups to be pr4ce~seri are typic.~lly st-~red in the memory unit 15. A .:onscle unit 12 can be couple~ t4 the central processin~ unitCs~ and typically . . . . , ~ .
.
', ' ' .
' ~ D~ 6 includes the apparatus and stored instructi~ns to initiali~e the system and can act as a terminal during the operation of the data processing system. The input/~utput units provide the interface to the remainder of the data pr~cessin~ system to terminal units, ma~s storaye units, ,cmmunication unitsr and any other units to be coupled t~ the data processing system.
The detailed function of the units ,:oupled to the system bus is less important than the fact that these units operate autonomc,usly and ,:ommuni,:ate with the remainder of the data processing units primarily by means of the system bus.
~eferring next to Figure 2, the technique ~or applying ,-lgi,: signal5 to the system bus is illustrated. The system bus 1~3 is ,:ompromised of a multiplicity of ,:onductinc3 elements, lga thrc,ugh l9g. The conductimg elements, as the cycle times ~f the data prl~cessing systems have decreased, have acquired the characteristi~s of transmission lines and must, for example, be terminated in su,h a manner ~not sh,~wn) as to avoid reflecti,~ns. Each data pr~cessin~ ~nit that can apply signals tc, the system has a multiplicity of transistors ,oupled t,~ the system bus. For example, data processing system unit ~1 has the emitter elements of transistors 21a through 219 coupled to system bus conduct,3rs l9a through 19~ respe,_tively, while data pr,~cessing system unit 23 has the emitter elements of transistors ~a through ~39 also coupled tc, conducting elements 13a throuc~h l~b~ When data processing system unit ~l i5 t,3 pl~ce a clroup of logic signals on the system bus, the base terminals of the transistors that are to assume a first logi~
state are maintained at a high level ~ir~ wllich the associ~ted ~; ~
~E~O
transistors are ,onducting~, while the base elements of the transistor 5 that are to assume a second lo~ic state are maintaineJ at low level ~:in which the assel-iated transistors are in a nonc"ndu,:ting state).
It will be ,:lear that the transient conditions on the system bus that result frorn a change state ~,f conductivi~y of a ,:oupled tr~nsistor can remain for the lQn~th of time neerled fcr the propagation, whichever is lcnger~ of the signal Cl.~ from the data processing system unit establishin~ the l~gi,: state ~f the bus to the data proces5ing system units identifylng the state of the system bus, or ~.) from the unit releasiny the lc,gic state of the bus tcl the unit ~5) identifyin~ the state c,f the bus.
However, the transient conditions on the system bus can remain for a lon~er p2ri~d ,:,f time as ,:an be underst~orJ by referen,-e to Figure 3 and Fi~ure 4. When the initial state of the condu~:tor 13~.~ of the system bus is the first ~high) logic state in which the transistor 21x, associated with data pro.:essing subsystem, is in the conducting state, the voltac7e leveL alonc conductor l9fi is essentially c.~nstant, position 21 indil:ating the 1,~c~til~n l~n the system bus ,-ondul-tl~r ,~f data processing system unit 21 and pcsiticn ~ indicatirl~ the lo.:ati..n cn the system bus ~ ndu.:t~r of data pr~cessin~ system unit ~3. This c.~ndition is shown by the curve in Figure 4a.
When the nefit .:onse.:utiv~ state in the system is one in which transistc-r ~1~ is in a nonconducting state and transistc~r ~
is a :-~nducting state~ then, imme~iately after the new state is entered, tran~istcr ~1 is rendered nonconducting~ A5 shown in DEr-66c) the curve in Fir~ure 4b immediately after the new state is entered the low voltage level indicating the application of no logic level propagates alon~ the conductiny element lgx.
Turning now to the operaticn of the transistor -~3x the b~se of transistor ~3x has a voltage applied thereto to pla:e t~7is transistor in a _or)ductin~ state~ However because the signal resultin~ from :easing of the prior conductlon of transistor ~lx has not yet propagated to the position of transi~tor ~3~ on the system bus condul:tor tranYistor ~3x rnay not be in the conducting st~te even th~ugh the voltage level of the base i5 at a level where :ondul:tion of the transistor normally takes place. At a later time as shown in Figure 4c the effect of rend~rin~ transistor lx non:ondu~ting will have propagated to position 23~ Immediately thereafter as shown in Figure 4d transistor ~ be:omes condu~ting and a volta~e level si~nal is proFarJated al~nr~ the system bus ~~onduet-~r~ After a period of time the voltar~e level resulting from initiation of condu-tion of transistor ~x will reach position ~1 as shown in Figure 4e. Therefore it will be :lear that transient signal effe ts on the system bus can persist for a longer period than the time :al:ulated for the transients to propagate along the distan:e defined by the physi-al separation of the data processing ~ystern elernents.
It has been known in the related art to provide ~ timing :y:le for the data pro:essinl3 <3ystem that :an a comm:date the longest required time~ However the adjustment of t~e systr~m timin~ :y:le to the worst _ase :an be ineffi:ient be~-ause for sele ted types of access tc the system bus a plurality of bus DEI'~F,O
access cycles ,:an ,-~ccur from a single data pro essiny subsystem without interruption~ The excessively lontl system cycle ti~e would make su,-h a transfer of siynals unnecessarily long in addition to the overall eompromise of the system performance resulting from a lont3 system cycle time.
A need has therefore been felt for apparatus ancd method c,f operation f~r the system bus that would permit the cycle time of the data processing system to remain short while simultaneously permittil7g any transient conditions on the system bus to decayr thereby maintainin~ the inte~rity of loyic state imposed on the data pr,:":essing system bus.
SUMMA~Y OF THE INVENTION
It is an obje,:t of the present invention to proYide an improved data processin~ unit.
It is a further object of the present invention to provide a ci.~ta pro,:essin~ system that ,-an provide for variable delays in the decay of tr~nsient conditic,ns on the system bus.
It i5 a particular object c~f the present invention to provide a delay in the ac,:ess of the system bus by a newly sele,:ted data prol:essin~ subsystem that i5 determined by the data pro,essiny subsystem havin~ system bus a~,:ess duriny the pri,~r system cll~,:k cycle.
It is a more partlcular ,~bject of the present invention, in a data processiny system in whi,:h conducti,~n of a first transistor ,:oupled to a system bus can delay the cclnduction of a se,:ond transistor coupled to the system bus, to provide s ~7~
66822~~5 apparatus for eliminating the effect of the interaction of the two transistors without increasing the system clock cycle.
The aforement:Loned and other objects are accomplished, accorcling to the present lnvention, by coupllng the data processlng ~ubsystems to a control unlt and by manipulzlting output sirJnal.s from an arhitration wnit itl a manner to provlcle aclditional time prior to application of the control unit signals when predetermined conditions are present. The arbitration unlt receives signals from each subsystem as the subsystem requires access to the system bus. In the event of conflict between two subsystems, the arbitration unit resolves the conflict according to an algorithm associated with a decision network device in the control unit. Accordiny to one embodiment o~ the present invention, associated with the arbitration unit ls apparatus tha~
permits the Request siynals to be disabled ~or a perlod of time prior ko the application of the Request signal to the decision network after any prior access to the system bus. According to a second embodiment of the present invention, the application of the Enable signal to a clata processin~ subsys-tem determined by the decision networlc can be delayed ~or selected subsystems, the remalning subsystems receiviny the ~nable siynal during -the present clock cycle. ~n thLs embod:lment, apparatus can be addecl to redetermine the suhs~stem receiving the ~nable siynal after a delay in the yenerat:Lon of the s:Lynal.
The inven~ion may be summarizecl, according to one aspect, as a data processing system, comprising, a system bus for carrying transmitted logic signal yroups having a transient time 66822-~5 period equal to the time for said logi~ signal groups ~ransmitted on said system bus to stabilize; A first data processing unit and a second data processlny unit coupled to said system bus, each of said ~irst and se~orld datc, processiny units in~ludingt means for transmitkiny lOCJ:IC slynal cJroUpS on sald system bus, and means for yenerakLng hus rec~les~ signals; central arbitration means coupled to sald firs~ and second data processlng units for permitting said ~irst and second d~ta processiny unlts to successlvely gain access to sald system bus including: declc:ion means for determining which of said 1rst and second data processiny units is permitted to gain access to said system bus in succession in response to said bus request signals and for generating one o~ a first enable signal and a second enable signal corresponding to said first and second data processing units respectively, means for generating an lnhibit signal ln response to generation of one of said first and second enable signals, sald inhibit signal generation means generating said inhibit sLgnal after generation of said one of said first and second enable slgnals for a period of time at least equal to the transient time period for logic signal groups transmitted by a preceding data processing unit permitted to gain successive access to the system bus; and means for inhib:Ltlng the trelnsmi~sion of successive bus request s.tgnals to sald declsion means ln response to an inhibit signal.
AccordincJ to another aspect, the invention provldes the method of controlllng the appllcation of logic signal yroups from data processing un:Lt~ ol a data processing system havlng a central arbitration unit to a system bus compr:lsing the steps of t 6~822~8S
determininy, by said central arbitration un.it, a one of said data processing units to be granted access to said system bus in order to apply a logic signal qroup to said system bus; generating, by said central arbitration un:Lt, a signal enabling said one of said data process:Lng units to gain access to said syetem bus; and pxevent.ln~ cJeneratlon of a slynal enabllng one of the remainlng clata processinq units to ga:Ln accese to said ~ystem bus during a system alock cycle following an aacess to said system bus.
These and other features oE the presenk invention will be underskood upon recadiny of the following description alonq with the drawings.
DEC~F.O
~2~
~IEF DESI~RIPTION OF THE DRAWIN13S
FI~. 1 i5 a block diagram of the components c~f a data pro,-essing system ,:apable ~f utilizing the present invention.
FI13~ ~ is a schematic diacgram c,f the c~upling ,~f units of the ciata processinc~ system to the system bus by means of transistc,rs.
Fl~. 3 is a s,:hematic dia~ram c~f the couplincl of twc~
transist,~rs to a ~:ondu,-tor in the system bus.
FIG. 4 is a diagrammatic representation of the si~nal levels on a system bus during the transitil~n from appli,-ation of a lc~gic sic~nal clrc,up by one data processiny system unit to an appli.-ation of a logi,- signal ~roup by a se~ond data processinc~ system unit t,~ the system bus.
FIO~. 5 i5 a blol-k diagram ,~f a data pr,~,-essin~ system ha~inc~ a unit tc, determine the next data prc,cessin~ subsystem t,~ apply a l.~gic siynal group to the system bus.
FI13. 6 is a block diac~ram of the apparatus for disabling the applicati,~n ,~f the loc~ic signal c~rl~up for a timing cycle.
FI13. 7 is a bloc~: diacJram of apparatus f,~r controlling the delay of applicati,3n of logic signal ~roups to the system bus determined by the partlcular ciata processinc~ subsystem havinc7 the last access~
DETAILED DESCF.:IPTION QF THE P~EFE~:ED EM~ODIMENT
1. Detailed Ves,:ripti,~n of the Figures ~78~ DF ~
Fi~ure 1 Fi~ure 2 Fi~ure 3 and Fiyure 4 have previously been des~ribed.
~ eferring ne~t to Fic~ure 5 the data pro~ssincl system ancl the data pro:essing subsystems as sh~wn and des:ribed with reference to Fi~ure 1 ls illustrated. In addition an arbitrati~n unit 5~ is indi:ated that :an control the appli~aticn oF the c~rjups of lor~ic signals to the system bus.
Su:h an apparatus i5 a c~ntr~1 unit that :an be referred t~ as a system bus arbitration unit cne su-h apparatus is des-ribed in U. S. Patent 4 7~3 7~1; entitled ~istributed ~rbitration Cireuitry for ~ata Processinr~ Systems; assir~ned to tl7e assir~nee of the present Patent Appli:ation. In the preferrecl embo~iment utili~ing central arbitration a eentralized arbitration unit 50 operates in the following manner~ When any of the subsystems has the requirem~nt that the subsystem must pla~e a ~roup of logil~ sir~nals on the system bus a Request lo~ic siClnal i5 applied to a mechanism couplinr~ the data pr~cessin~
subsystem and the arbitrati n unit 50. In the simplest situation the d~ta pr~cessincl sLlbsystem and the arbitration unit 5l~ are couplec1 by a cl~nductor a lorJi- siclnal ~pplied thereto indieatincl not only the presen:e -f a Request for a~cess to the system bus but als~ the identity l:f the subsystem requesting the access~ ~ased on an alr~rithrn preveriting monop~ly of ~he ;ystrm bu!3 by a partil:ul~r subsystem assignin~ prioritie~ to the various data pr~ces~inr~
unit subsystems~ and takin~ a:~:ount of any other fa:t~r deemed important in the acce~s to the system bus the arbitration unit 50 (ietermines the ne~t data pro:essinc~ subsystem to have a~:eess DE ~ 6 0 ~27~
to the system bus, and an Enable lo~i- si~nal is applied to the selected subsystem by a coupliny means, typically a condu,_t,3r.
The presen,e of this Enable logic siynal ,-ommuni~ates t" the selected data pro,-essiny subsystem that the 14~ic signal ~r~up can be applied to the system bus. The sele~ted subsystem can apply a Hl~ld lo~ic signal to the arbitration unit S~. Tlle Hold logi, si~nal i5 used in those situati4ns where the sele,:ted data pro,:essin~ subsystem must apply a plurality of logil-signal groups in sequen,:e to the system bus. The H~ld si~nal prevents the Enable signal frc,m bein~ removed from the s~lected data pr~,-essin~ subsystem until the ne~essary system clol:k cyc]es have passed for the plurality of related 14gir signal greups t~ have been applied to the system bus.
~ eferrin~ ne~t to Figure 6, the apparatus for preventing the appli,:ation of the Enable loyil- siynals to the sele,ted subsystem i5 shown. The arbitration unit 50 ~an re~eive Re~uest signals and Hold signals fr,3m the data pro,:essiny subsystems requiring ac~ess to the system bus. The Hold siynals are ,:oupled direl:tly t~ the de,:ision network 61 at terminals associated witll tlle particular data processin~
subsystem issuin~ the Hold si~nal. The ~equest line fr:,m ea,-h data pr~ essin~ subsystem is ~oupled to the first input terminal of a loyi,- AhlU yate G2a throuyh 62x associated with the data pr"cessin~ subsystem~ The output terminal~ clf the loyic AND yates ~2a thr4u~h 6~x are ,:oupled directly to terminals c,f th~ decision network 61 associated with the ~equest siynal line s data pro,:e~siny system. The output terminals of the decisi~n network 61 are c~upled t~ conducting ~EU6~0 ~78~
paths that apply the Enable si~nals to the associated dat processing sub~ystem. Each Enable line is also cc~upled t,~ an input terminal of logil: "NO~" gate ~3. The output terminal of ICJ9iC llNn~l gate ~3 i5 cc.upled to an input terminal of a one cy,:le delay netw,~rk &~, while the output terminal of one .:y,-le delay network 6~ i5,oupled to a second input terminal of each ,~f the logil~ "AN~" gates 6~:a tc~ ~-'`fi.
Referring next to Fi.gure 7, a block diagram is s~lown ~f apparatus for pr~vidingt t~ a ~;elected dat~ pr~cessing subsystem, an Enable signal that ._an be delayed when one of a gr.~up ,:,f preselected subsystems received an Enable signal durin~ a pr~vious timing ,-ycle. Each .~utput terminal of the decision netw~rk 61 is coupled to an input terminal of a delay network 7~a thr~ugh 7~x and a first input terminal ~f lc~ic "AND" yates 71a through 71x respe,tively~ E~ch second input terminal of logic "AND" gates 71a through 7ix~ is ~oupled t,-, an output terminal of ll~gil- "NOR" gate 7~a through 7~x respectively~ The ~-JUtpUt terminals of the delay networks 7~'a through 7~x are coupled to input terminals ~f logic "0~" gates 71a through 71x according t.~ the foll,-lwing relationship. When the two subsystems shoulli be activated cl:,n~el:utively only after a delay t,:, av.~id settlin~ time problems, t~e ~utp~t terminals c~f the delay networks asscl,:iated with the twc, subsy~tems sh~uld be coupled to the input terminal of the lc.gi.. "0~" gate associated with the .~ther subsystem. In this manner, the s~bsystems that sh~uld have a delay between ~c~~esses t.~ the system bus ~re insured .~f an enf.~r.ed delay~
.
~E1~6 . Operation ,f the Preferred Embodiment The use of the system bus in data pr~essin~ systems provides flexibility in ~-onfiyuration of the 6ystem. Data pr,seessing subsystems ean be added sr removed from the system relatively easily. However, thQ pri,:e ,~f this flexibility is that the time rr*quired to transfer l~,gi,- si~nal groups from one data pr,s,:essing system .:omp,-.nent unit t.s a se~.lnd is nlst precisely known, but ,:an be determined ,~nly within ,~ertain lirnits. The present inventl,sn permits the data pr.slessin~
system t~ a~csmmodate a l~sng settling time f,sr transients on the system bus. The prin.-iple of delayin~ the initiati,~n of the control s~gnal permitting ac,_ess to the system bus can be used in syn.-hr,sn,sus ~r nonsyn,:hronous data proeessing systems.
In the synehr~nous data pr.~essing systems in whil-h the ,-locking ,-y.:les are syn.-hroni~ed f~sr eaeh data pro.:essin~
subsystem, the a._tivation of the system bus ae.~ess control or enable signal .-an be delayed by ~sne .-.r m.sre system .-l...:k .-yeles. The present invention can be used as part .~f an arbitration unit. The arbitrati~sn unit is employed in a data pr~eessing system to reslslve confli-ts between tle data pro.-essin~ suhsystems f.sr a~cess t-s the system bus and t.s insure that one subsystem does not msn~poli~e the system bUCi.
In additi.-.n, in data pro~essing systems in whi.:h ..-onse.:utive system bus ac~esses are provided t~ e~pedite ~ertain signal ~r.~up tran~;fers, the arbitration unit .:an be resplsn~aive t.s the Hold signals, permittin~ the subsystem to maintain a.:cecis f..r e.snse.:utive ~l.s.:k .:ycles, and delay issuanee sf a .:~sntr~sl si~nal until the .:onsecutive a~.-ess pro,:edure has been DEu660 ~:ompleted.
~ eferring ~nce a~ain to Figure ~, it will be clear that the primary operation of netw~r~ ~4 is the delay of the Enable signal for one eycle by preventing appli,:ati,-,n ,~f the ~equest siynal to the de,-ision networlc 61 in the first embodiment. In the embodiment shown, the delay i5 f~r one cycler however other delay periods can be easily a,-rommodated. Upon generati,~n of an Enable signal~ the delay network ~4 delays a lcl~ic signal f"r one cycle and then applies a negative logil signal to the input terminal of all the logic AN~ gates 6~a to 6~Y~, thereby disablin~ the ll~(~il- AND ~ates until l~ne ~y~:le after the Enable signal is reml~ved from the ~utput terminals of the de,-ision network 61. When no Enable signal is applied to the output terminals of decision network ~1~ a pcsitive lo~i~
signal is applied to the output terminal of logil: NOF ~ate 63. One cycle later, the positive logil signal is applied, via delay netwl~rk 64, to the second input terminal of the lo~ic AN~ ~a~es ~a through ~?y~ and enables the logic AND gates.
The enabled l~gi- AND gates therefore ~-an transmit the Request siclnals to the decision network for determining the neYt data processin~ system to have a,:,:ess t,~ the system bus.
The foregoiny apparatus provides a unif~rm ~one cy,:le) delay after the ~eneratic,n of ea~:h Enable signal. I-lowever, it ,:an be desirable, in order t~ inerease the bus a~tivity~ to establish that, f~r sele~.ted data proces3ing subsystems, the delay in a,-cess to the system bus is not reqùired. In c,rder to implement a arbitration unit in which a delay can ~r ~:an not be required, the implementation illustrated in Fi~ure 7 ~an be l ~7 ~7~ DE~
used. The ceupling of the delay networks 72a through 7~x to the lo~ic "0~" ~ates 73a through 73x in the manner des~ribed previously delays the Enable sir~nal from passing throu~h t~
ass~ iated logic "A~" gate when one of the terminals asso,-iated with a preselected subsystem has been activated rJùring the previous timin~ cycle. The Enable si~nal is frad ba~k via its ass4ciated line 75a tilrough 75x in order to communicate to decision network 61 that the Enable si~nal issued. With this information, network 61 may update its priority state.
The apparatus for delayin~ the application of the Enable signal t,~ mpensate f4r system bus settlin~ times ~an either be performed on the in~~ominy Request signals clr ,-,n the Enable signals themselves. When the delay is imposed on the Enable signals and when de~isi~n network ~i makes priority decisions based upon previclus bus a,,ess suc,-ess, the actual transmission ~f the Enable signal must be communicated to t~e ~ecision network~
In the interactic,n by data pro,-essing subsystems wit~ the system bus, one m,~de of operati"n result~3 in a plurality of signal groups b~?ing applied t" the system bus ,-,n conse,-utive cy,les. T~le apparatus of the present invention is intended to provide a delay only when tl-e subsystem havinr~ access tc, the bus changes. For a multiplil:ity of sir~nal groups applied by a given subsystem to the system bus ,~n ,onsecutive ~lo~k cycles, only the ~irst si~nal group is delayed.
The foregoing descriptic~n is included t" illustrate the ,~peratlon "f the preferred embl~diment and is nc,t meant t" limit ~2~ DE1~6~(~
t~e s,-ope of the invention. The scope of the invention is to be limited only by the followin~ claims~ ~rom the fore~oin~
description many variations will be apparent to those skilled in the art that would yet be ~ncompassed by the spirit and s-ope of the invention.
1`~
Claims (8)
1. A data processing system, comprising:
a system bus for carrying transmitted logic signal groups having a transient time period equal to the time for said logic signal groups transmitted on said system bus to stabilize;
a first data processing unit and a second data processing unit coupled to said system bus, each of said first and second data processing units including:
means for transmitting logic signal groups on said system bus, and means for generating bus request signals;
central arbitration means coupled to said first and second data processing units for permitting said first and second data processing units to successively gain access to said system bus including:
decision means for determining which of said first and second data processing units is permitted to gain access to said system bus in succession in response to said bus request signals and for generating one of a first enable signal and a second enable signal corresponding to said first and second data processing units respectively, means for generating an inhibit signal in response to generation of one of said first and second enable signals, said inhibit signal generation means generating said inhibit signal after generation of said one of said first and second enable signals for a period of time at least equal to the transient time period for logic signal groups transmitted by a preceding data processing unit permitted to gain successive access to the system bus; and means for inhibiting the transmission of successive bus request signals to said decision means in response to an inhibit signal.
a system bus for carrying transmitted logic signal groups having a transient time period equal to the time for said logic signal groups transmitted on said system bus to stabilize;
a first data processing unit and a second data processing unit coupled to said system bus, each of said first and second data processing units including:
means for transmitting logic signal groups on said system bus, and means for generating bus request signals;
central arbitration means coupled to said first and second data processing units for permitting said first and second data processing units to successively gain access to said system bus including:
decision means for determining which of said first and second data processing units is permitted to gain access to said system bus in succession in response to said bus request signals and for generating one of a first enable signal and a second enable signal corresponding to said first and second data processing units respectively, means for generating an inhibit signal in response to generation of one of said first and second enable signals, said inhibit signal generation means generating said inhibit signal after generation of said one of said first and second enable signals for a period of time at least equal to the transient time period for logic signal groups transmitted by a preceding data processing unit permitted to gain successive access to the system bus; and means for inhibiting the transmission of successive bus request signals to said decision means in response to an inhibit signal.
2. The data processing system for controlling the transfer of logic signal groups of claim 1 wherein the means for transmitting logic signal groups on the system bus includes a plurality of transistors coupled to the system bus, and wherein said data processing units establish the logic signal groups applied to the system bus by conduction or nonconduction of the transistors coupled to said system bus.
3. A data processing system according to claim 1 wherein said means for generating an inhibit signal includes a delay network.
4. A data processing system, comprising:
a system bus for carrying transmitted logic signal groups having a transient time period equal to the time for said logic signal groups transmitted on said system bus to stabilize;
a first data processing unit and a second data processing unit coupled to said system bus, each of said first and second data processing units including:
means for transmitting logic signal groups on said system bus, and means for generating bus request signals;
central arbitration means coupled to said first and second data processing units for permitting said first and second data processing units to successively gain access to said system bus including:
decision means for determining which of said first and second data processing units is permitted to gain access to said system bus in succession in response to said bus request signals and for generating one of a first enable signal and a second enable signal corresponding to said first and second data processing units respectively:
means for generating delayed first and second enable signals corresponding respectively to said first and second enable signals, said delayed first and second enable signals having a duration at least equal to the transient time period for logic signal groups transmitted by the preceding data processing unit permitted to gain successive access to the system bus;
and means for disabling said decision means and inhibiting successive transmission of a selected one of said first enable signal and said second enable signal in response to the presence of a selected one of said delayed first and second enable signals, respectively
a system bus for carrying transmitted logic signal groups having a transient time period equal to the time for said logic signal groups transmitted on said system bus to stabilize;
a first data processing unit and a second data processing unit coupled to said system bus, each of said first and second data processing units including:
means for transmitting logic signal groups on said system bus, and means for generating bus request signals;
central arbitration means coupled to said first and second data processing units for permitting said first and second data processing units to successively gain access to said system bus including:
decision means for determining which of said first and second data processing units is permitted to gain access to said system bus in succession in response to said bus request signals and for generating one of a first enable signal and a second enable signal corresponding to said first and second data processing units respectively:
means for generating delayed first and second enable signals corresponding respectively to said first and second enable signals, said delayed first and second enable signals having a duration at least equal to the transient time period for logic signal groups transmitted by the preceding data processing unit permitted to gain successive access to the system bus;
and means for disabling said decision means and inhibiting successive transmission of a selected one of said first enable signal and said second enable signal in response to the presence of a selected one of said delayed first and second enable signals, respectively
5. The data processing system of claim 4 wherein said data processing units are coupled to said system bus by transistors.
6. A data processing system according to claim 5 including a plurality of data processing units and a plurality of corresponding enable signals wherein selected ones of said enable signals are not inhibited by the presence of delayed enable signals.
7. The method of controlling the application of logic signal groups from data processing units of a data processing system having a central arbitration unit to a system bus comprising the steps of:
determining, by said central arbitration unit, a one of said data processing units to be granted access to said system bus in order to apply a logic signal group to said system bus;
generating, by said central arbitration unit, a signal enabling said one of said data processing units to gain access to said system bus; and preventing generation of a signal enabling one of the remaining data processing units to gain access to said system bus during a system clock cycle following an access to said system bus.
determining, by said central arbitration unit, a one of said data processing units to be granted access to said system bus in order to apply a logic signal group to said system bus;
generating, by said central arbitration unit, a signal enabling said one of said data processing units to gain access to said system bus; and preventing generation of a signal enabling one of the remaining data processing units to gain access to said system bus during a system clock cycle following an access to said system bus.
8. The method for controlling the application of logic signals to a system bus according to claim 7 further comprising the steps of coupling said data processing units to said system bus with transistors and using conductive states of a plurality of transistors to establish logic states generated by said data processing units on said system bus.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US82377486A | 1986-01-29 | 1986-01-29 | |
| US823,774 | 1986-01-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1278100C true CA1278100C (en) | 1990-12-18 |
Family
ID=25239674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000528363A Expired - Fee Related CA1278100C (en) | 1986-01-29 | 1987-01-28 | Apparatus and method for providing a settling time cycle for a system bus in a data processing system |
Country Status (7)
| Country | Link |
|---|---|
| EP (1) | EP0290472A1 (en) |
| JP (1) | JPH01501426A (en) |
| AU (1) | AU7033687A (en) |
| CA (1) | CA1278100C (en) |
| ES (1) | ES2002950A6 (en) |
| IL (1) | IL81423A (en) |
| WO (1) | WO1987004827A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2657740A1 (en) * | 1990-01-26 | 1991-08-02 | Sgs Thomson Microelectronics | METHOD AND CIRCUIT FOR CONTROLLING AN INTEGRATED CIRCUIT OUTPUT BUS. |
| US6188249B1 (en) * | 1998-06-30 | 2001-02-13 | Sun Microsystems, Inc. | Asymmetric arbiter with fast signal path |
| US7203779B2 (en) * | 2002-01-30 | 2007-04-10 | Stmicroelectronics, Inc. | Fast turn-off slow turn-on arbitrator for reducing tri-state driver power dissipation on a shared bus |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4186379A (en) * | 1977-04-28 | 1980-01-29 | Hewlett-Packard Company | High-speed data transfer apparatus |
| US4249093A (en) * | 1978-09-06 | 1981-02-03 | Lockheed Electronics Co., Inc. | Multiple request arbitration circuit |
-
1987
- 1987-01-28 CA CA000528363A patent/CA1278100C/en not_active Expired - Fee Related
- 1987-01-28 ES ES8700201A patent/ES2002950A6/en not_active Expired
- 1987-01-29 AU AU70336/87A patent/AU7033687A/en not_active Abandoned
- 1987-01-29 IL IL81423A patent/IL81423A/en not_active IP Right Cessation
- 1987-01-29 EP EP87901790A patent/EP0290472A1/en not_active Withdrawn
- 1987-01-29 JP JP62501334A patent/JPH01501426A/en active Pending
- 1987-01-29 WO PCT/US1987/000181 patent/WO1987004827A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| ES2002950A6 (en) | 1988-10-01 |
| AU7033687A (en) | 1987-08-25 |
| IL81423A (en) | 1991-06-10 |
| WO1987004827A1 (en) | 1987-08-13 |
| IL81423A0 (en) | 1987-08-31 |
| EP0290472A1 (en) | 1988-11-17 |
| JPH01501426A (en) | 1989-05-18 |
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