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BR9810100A - Circuito de comando para uma disposição de memórias-semicondutores não-voláteis - Google Patents

Circuito de comando para uma disposição de memórias-semicondutores não-voláteis

Info

Publication number
BR9810100A
BR9810100A BR9810100-5A BR9810100A BR9810100A BR 9810100 A BR9810100 A BR 9810100A BR 9810100 A BR9810100 A BR 9810100A BR 9810100 A BR9810100 A BR 9810100A
Authority
BR
Brazil
Prior art keywords
volatile semiconductor
circuit
array
control circuit
semiconductor memories
Prior art date
Application number
BR9810100-5A
Other languages
English (en)
Inventor
Thomas Zettler
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of BR9810100A publication Critical patent/BR9810100A/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits

Landscapes

  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

Patente de Invenção: <B>''CIRCUITO DE COMANDO PARA UMA DISPOSIçãO DE MEMóRIAS-SEMICONDUTORES NãO-VOLáTEIS''<D>. A invenção refere-se a um circuito de comando para uma disposição de memórias-semicondutores não-voláteis, com um circuito conversor de níveis (10), que aplica um valor de saída (D, DN) ou um valor de saída (DN) complementar a este valor de saída (D) em uma linha de bits e/ou em uma linha de palavras da disposição de memórias-semicondutores. Entre um circuito de entrada (12) e o circuito conversor de níveis (10) está situado um circuito de bloqueio (11) que interarmazena os dados a serem armazenados na disposição de memórias-semicondutores.
BR9810100-5A 1997-06-13 1998-06-08 Circuito de comando para uma disposição de memórias-semicondutores não-voláteis BR9810100A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19725181A DE19725181A1 (de) 1997-06-13 1997-06-13 Ansteuerschaltung für nichtflüchtige Halbleiter-Speicheranordnung
PCT/DE1998/001560 WO1998058384A1 (de) 1997-06-13 1998-06-08 Ansteuerschaltung für nichtflüchtige halbleiter-speicheranordnung

Publications (1)

Publication Number Publication Date
BR9810100A true BR9810100A (pt) 2000-08-08

Family

ID=7832475

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9810100-5A BR9810100A (pt) 1997-06-13 1998-06-08 Circuito de comando para uma disposição de memórias-semicondutores não-voláteis

Country Status (12)

Country Link
US (1) US6137315A (pt)
EP (1) EP0988633B1 (pt)
JP (1) JP3399547B2 (pt)
KR (1) KR20010013737A (pt)
CN (1) CN1124617C (pt)
AT (1) ATE201112T1 (pt)
BR (1) BR9810100A (pt)
DE (2) DE19725181A1 (pt)
ES (1) ES2157666T3 (pt)
RU (1) RU2221286C2 (pt)
UA (1) UA42887C2 (pt)
WO (1) WO1998058384A1 (pt)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19921868C2 (de) * 1999-05-11 2001-03-15 Siemens Ag Schaltungsanordnung zur Kontrolle von Zuständen einer Speichereinrichtung
US7440311B2 (en) * 2006-09-28 2008-10-21 Novelics, Llc Single-poly non-volatile memory cell
US7554860B1 (en) 2007-09-21 2009-06-30 Actel Corporation Nonvolatile memory integrated circuit having assembly buffer and bit-line driver, and method of operation thereof
EP2226788A4 (en) 2007-12-28 2012-07-25 Sharp Kk DISPLAY CONTROL, DISPLAY ARRANGEMENT AND DISPLAY CONTROL PROCEDURE
CN101965607B (zh) 2007-12-28 2013-08-14 夏普株式会社 辅助电容配线驱动电路和显示装置
WO2009084269A1 (ja) 2007-12-28 2009-07-09 Sharp Kabushiki Kaisha 半導体装置及び表示装置
JP4902750B2 (ja) * 2007-12-28 2012-03-21 シャープ株式会社 半導体装置及び表示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4599707A (en) * 1984-03-01 1986-07-08 Signetics Corporation Byte wide EEPROM with individual write circuits and write prevention means
US4716312A (en) * 1985-05-07 1987-12-29 California Institute Of Technology CMOS logic circuit
US4654547A (en) * 1985-06-28 1987-03-31 Itt Corporation Balanced enhancement/depletion mode gallium arsenide buffer/comparator circuit
FR2604554B1 (fr) * 1986-09-30 1988-11-10 Eurotechnique Sa Dispositif de securite pourla programmation d'une memoire non volatile programmable electriquement
JP2773786B2 (ja) * 1991-02-15 1998-07-09 日本電気アイシーマイコンシステム株式会社 書き込み電圧発生回路
JP3173247B2 (ja) * 1993-09-29 2001-06-04 ソニー株式会社 レベルシフタ
US5682345A (en) * 1995-07-28 1997-10-28 Micron Quantum Devices, Inc. Non-volatile data storage unit method of controlling same
JP3404712B2 (ja) * 1996-05-15 2003-05-12 株式会社東芝 不揮発性半導体記憶装置及びその書き込み方法

Also Published As

Publication number Publication date
US6137315A (en) 2000-10-24
DE59800692D1 (de) 2001-06-13
JP2001505350A (ja) 2001-04-17
JP3399547B2 (ja) 2003-04-21
KR20010013737A (ko) 2001-02-26
RU2221286C2 (ru) 2004-01-10
EP0988633B1 (de) 2001-05-09
CN1260901A (zh) 2000-07-19
ES2157666T3 (es) 2001-08-16
EP0988633A1 (de) 2000-03-29
UA42887C2 (uk) 2001-11-15
CN1124617C (zh) 2003-10-15
DE19725181A1 (de) 1999-02-25
ATE201112T1 (de) 2001-05-15
WO1998058384A1 (de) 1998-12-23

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 7A,8A E 9A ANUIDADES

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 1909 DE 07/08/2007.