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BR9808381A - Circuito integrado e processo para teste do circuito integrado - Google Patents

Circuito integrado e processo para teste do circuito integrado

Info

Publication number
BR9808381A
BR9808381A BR9808381-3A BR9808381A BR9808381A BR 9808381 A BR9808381 A BR 9808381A BR 9808381 A BR9808381 A BR 9808381A BR 9808381 A BR9808381 A BR 9808381A
Authority
BR
Brazil
Prior art keywords
integrated circuit
rom
test process
user
cpu
Prior art date
Application number
BR9808381-3A
Other languages
English (en)
Inventor
Juergen Nolles
Hans-Heinrich Viehmann
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of BR9808381A publication Critical patent/BR9808381A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Microcomputers (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Storage Device Security (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Patente de Invenção: <B>"CIRCUITO INTEGRADO E PROCESSO PARA TESTE DO CIRCUITO INTEGRADO"<D>. Circuito integrado com uma CPU e uma ROM de usuário caracterizado por uma ROM de teste, cujo espaço de endereço se encontra dentro do espaço de endereço da ROM de usuário, uma RAM externa à CPU bem como um dispositivo de comutação, que possibilita um acesso apenas à ROM de usuário ou à ROM de teste e é irreversivelmente deslocável para um estado, que permite apenas um acesso à ROM de usuário.
BR9808381-3A 1997-03-19 1998-03-02 Circuito integrado e processo para teste do circuito integrado BR9808381A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19711478A DE19711478A1 (de) 1997-03-19 1997-03-19 Integrierte Schaltung und Verfahren zum Testen der integrierten Schaltung
PCT/DE1998/000608 WO1998041880A2 (de) 1997-03-19 1998-03-02 Integrierte schaltung und verfahren zum testen der integrierten schaltung

Publications (1)

Publication Number Publication Date
BR9808381A true BR9808381A (pt) 2000-05-23

Family

ID=7823916

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9808381-3A BR9808381A (pt) 1997-03-19 1998-03-02 Circuito integrado e processo para teste do circuito integrado

Country Status (7)

Country Link
EP (1) EP0968436A2 (pt)
JP (1) JP2001527669A (pt)
KR (1) KR20000076351A (pt)
CN (1) CN1251183A (pt)
BR (1) BR9808381A (pt)
DE (1) DE19711478A1 (pt)
WO (1) WO1998041880A2 (pt)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3198997B2 (ja) * 1997-08-28 2001-08-13 日本電気株式会社 マイクロコンピュータ及びそのバーンインテスト方法
EP0992809A1 (de) 1998-09-28 2000-04-12 Siemens Aktiengesellschaft Schaltungsanordnung mit deaktivierbarem Scanpfad
RU2174692C1 (ru) * 2000-06-27 2001-10-10 Ульяновский государственный технический университет Устройство для измерения теплового сопротивления переход-корпус цифровых интегральных микросхем
DE10101234A1 (de) * 2001-01-11 2002-07-18 Giesecke & Devrient Gmbh Verfahren zum Text eines nichtflüchtigen Speichers und Verwendung eines solchen Verfahrens
DE602004020414D1 (de) 2003-02-24 2009-05-20 St Microelectronics Sa Verfahren und Vorrichtung zur Auswahl der Betriebsart einer Integrierten Schaltung
CN1829127B (zh) * 2006-04-20 2011-06-29 北京星河亮点通信软件有限责任公司 一种基于微内核的通信终端测试仪表控制平台的构建方法
CN102592683B (zh) * 2012-02-23 2014-12-10 苏州华芯微电子股份有限公司 一种芯片测试模式的进入方法及相关装置
CN103021471B (zh) * 2012-12-24 2016-08-03 上海新储集成电路有限公司 一种存储器及其存储方法
US10818374B2 (en) * 2018-10-29 2020-10-27 Texas Instruments Incorporated Testing read-only memory using memory built-in self-test controller

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0758502B2 (ja) * 1988-06-30 1995-06-21 三菱電機株式会社 Ｉｃカード
JP3125070B2 (ja) * 1990-12-14 2001-01-15 三菱電機株式会社 Ｉｃカード
JPH06236447A (ja) * 1993-02-09 1994-08-23 Mitsubishi Electric Corp Ｉｃカード用マイクロコンピュータ

Also Published As

Publication number Publication date
CN1251183A (zh) 2000-04-19
EP0968436A2 (de) 2000-01-05
KR20000076351A (ko) 2000-12-26
WO1998041880A2 (de) 1998-09-24
DE19711478A1 (de) 1998-10-01
JP2001527669A (ja) 2001-12-25
WO1998041880A3 (de) 1999-01-14

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 4A, 5A,6A, 7A, 8A E 9A ANUIDADES

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 NA RPI 1892 DE 10/04/2007