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BR8800754A - Processo de fabricacao de uma microplaqueta logica e estrutura logica - Google Patents

Processo de fabricacao de uma microplaqueta logica e estrutura logica

Info

Publication number
BR8800754A
BR8800754A BR8800754A BR8800754A BR8800754A BR 8800754 A BR8800754 A BR 8800754A BR 8800754 A BR8800754 A BR 8800754A BR 8800754 A BR8800754 A BR 8800754A BR 8800754 A BR8800754 A BR 8800754A
Authority
BR
Brazil
Prior art keywords
logic
manufacturing
chip
logic chip
logic structure
Prior art date
Application number
BR8800754A
Other languages
English (en)
Inventor
Elliot Lawrence Gould
Douglas Wayne Kemerer
Ronald Alan Piro
Guy Rymond Richardson
Deborah Ann Wellburn
Lance Alan Mcallister
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR8800754A publication Critical patent/BR8800754A/pt

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/909—Macrocell arrays, e.g. gate arrays with variable size or configuration of cells
BR8800754A 1987-02-24 1988-02-23 Processo de fabricacao de uma microplaqueta logica e estrutura logica BR8800754A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/018,239 US4786613A (en) 1987-02-24 1987-02-24 Method of combining gate array and standard cell circuits on a common semiconductor chip

Publications (1)

Publication Number Publication Date
BR8800754A true BR8800754A (pt) 1988-10-04

Family

ID=21786931

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8800754A BR8800754A (pt) 1987-02-24 1988-02-23 Processo de fabricacao de uma microplaqueta logica e estrutura logica

Country Status (7)

Country Link
US (1) US4786613A (pt)
EP (1) EP0283655B1 (pt)
JP (2) JPH0821701B2 (pt)
BR (1) BR8800754A (pt)
CA (1) CA1290076C (pt)
DE (1) DE3872737T2 (pt)
ES (1) ES2033346T3 (pt)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051917A (en) * 1987-02-24 1991-09-24 International Business Machines Corporation Method of combining gate array and standard cell circuits on a common semiconductor chip
US4831725A (en) * 1988-06-10 1989-05-23 International Business Machines Corporation Global wiring by removal of redundant paths
JPH02278848A (ja) * 1989-04-20 1990-11-15 Nec Corp 集積回路装置
US5015600A (en) * 1990-01-25 1991-05-14 Northern Telecom Limited Method for making integrated circuits
JP3027990B2 (ja) * 1991-03-18 2000-04-04 富士通株式会社 半導体装置の製造方法
WO1993012540A1 (en) * 1991-12-10 1993-06-24 Vlsi Technology, Inc. Integrated circuit with variable pad pitch
JPH08316331A (ja) * 1995-03-15 1996-11-29 Toshiba Corp 半導体集積回路及びその設計方法
FR2741475B1 (fr) * 1995-11-17 2000-05-12 Commissariat Energie Atomique Procede de fabrication d'un dispositif de micro-electronique comportant sur un substrat une pluralite d'elements interconnectes
TW392307B (en) * 1998-01-13 2000-06-01 Mitsubishi Electric Corp A method of the manufacture and the setup of the semiconductor apparatus
US6532581B1 (en) 1998-07-03 2003-03-11 Matsushita Electric Industrial Co., Ltd. Method for designing layout of semiconductor device, storage medium having stored thereon program for executing the layout designing method, and semiconductor device
TW519748B (en) * 2001-12-26 2003-02-01 Faraday Tech Corp Semiconductor device with substrate-triggered ESD protection
JP2004007472A (ja) * 2002-03-22 2004-01-08 Toshiba Corp 半導体集積回路、データ転送システム、及びデータ転送方法
JP2004221231A (ja) * 2003-01-14 2004-08-05 Nec Electronics Corp レイアウトパターン生成のための装置と方法、及びそれを用いた半導体装置の製造方法
US7095063B2 (en) * 2003-05-07 2006-08-22 International Business Machines Corporation Multiple supply gate array backfill structure
DE102004038063A1 (de) * 2004-07-30 2006-03-23 Infineon Technologies Ag Verfahren zur Herstellung einer Standardzellenanordnung und eine Vorrichtung zur Durchführung des Verfahrens
JP2012064854A (ja) * 2010-09-17 2012-03-29 Toshiba Corp 半導体装置
US20210200927A1 (en) * 2019-12-31 2021-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. System and Method for Transistor Placement in Standard Cell Layout
US11663391B2 (en) 2021-08-25 2023-05-30 International Business Machines Corporation Latch-up avoidance for sea-of-gates

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US814122A (en) * 1904-06-25 1906-03-06 Henry G Eckstein Apparatus for the manufacture of moisture-proof cartons.
JPS5925381B2 (ja) * 1977-12-30 1984-06-16 富士通株式会社 半導体集積回路装置
JPS5890758A (ja) * 1981-11-25 1983-05-30 Mitsubishi Electric Corp 相補形集積回路装置
FR2524206B1 (fr) * 1982-03-26 1985-12-13 Thomson Csf Mat Tel Circuit integre prediffuse, et procede d'interconnexion des cellules de ce circuit
US4513307A (en) * 1982-05-05 1985-04-23 Rockwell International Corporation CMOS/SOS transistor gate array apparatus
JPS5943548A (ja) * 1982-09-06 1984-03-10 Hitachi Ltd 半導体集積回路装置
JPS60110137A (ja) * 1983-11-18 1985-06-15 Sanyo Electric Co Ltd 半導体装置
JPS60177650A (ja) * 1984-02-23 1985-09-11 Toshiba Corp 半導体装置およびその製造方法
US4570176A (en) * 1984-04-16 1986-02-11 At&T Bell Laboratories CMOS Cell array with transistor isolation
JPS60234231A (ja) * 1984-05-04 1985-11-20 Fuji Photo Film Co Ltd 磁気記録媒体
JPS60234341A (ja) * 1984-05-07 1985-11-21 Hitachi Ltd 半導体集回路装置
JPS6124250A (ja) * 1984-07-13 1986-02-01 Nippon Gakki Seizo Kk 半導体集積回路装置
JPS61123153A (ja) * 1984-11-20 1986-06-11 Fujitsu Ltd ゲ−トアレイｌｓｉ装置
JPS61202450A (ja) * 1985-03-05 1986-09-08 Nec Corp 半導体集積回路装置
JPH0785490B2 (ja) * 1986-01-22 1995-09-13 日本電気株式会社 集積回路装置

Also Published As

Publication number Publication date
DE3872737T2 (de) 1993-03-04
ES2033346T3 (es) 1993-03-16
JPS63209144A (ja) 1988-08-30
US4786613A (en) 1988-11-22
EP0283655B1 (en) 1992-07-15
JP3213711B2 (ja) 2001-10-02
JPH08204162A (ja) 1996-08-09
CA1290076C (en) 1991-10-01
EP0283655A2 (en) 1988-09-28
DE3872737D1 (de) 1992-08-20
EP0283655A3 (en) 1989-11-29
JPH0821701B2 (ja) 1996-03-04

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Legal Events

Date Code Title Description
FF Decision: intention to grant
FG Letter patent granted
B21A Patent or certificate of addition expired [chapter 21.1 patent gazette]

Free format text: PATENTE EXTINTA EM 23/02/2003

B15K Others concerning applications: alteration of classification

Ipc: H01L 27/02 (2006.01), H01L 27/118 (2006.0