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AU2002337297A1 - Lateral semiconductor-on-insulator structure and corresponding manufacturing methods - Google Patents

Lateral semiconductor-on-insulator structure and corresponding manufacturing methods

Info

Publication number
AU2002337297A1
AU2002337297A1 AU2002337297A AU2002337297A AU2002337297A1 AU 2002337297 A1 AU2002337297 A1 AU 2002337297A1 AU 2002337297 A AU2002337297 A AU 2002337297A AU 2002337297 A AU2002337297 A AU 2002337297A AU 2002337297 A1 AU2002337297 A1 AU 2002337297A1
Authority
AU
Australia
Prior art keywords
manufacturing methods
insulator structure
corresponding manufacturing
lateral semiconductor
lateral
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002337297A
Inventor
Florin Udrea
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cambridge Semiconductor Ltd
Original Assignee
Cambridge Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cambridge Semiconductor Ltd filed Critical Cambridge Semiconductor Ltd
Publication of AU2002337297A1 publication Critical patent/AU2002337297A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65Lateral DMOS [LDMOS] FETs
    • H10D30/657Lateral DMOS [LDMOS] FETs having substrates comprising insulating layers, e.g. SOI-LDMOS transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411Insulated-gate bipolar transistors [IGBT]
    • H10D12/421Insulated-gate bipolar transistors [IGBT] on insulating layers or insulating substrates, e.g. thin-film IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/8303Diamond
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10P90/1904
    • H10P90/1914
    • H10W10/181
    • H10P14/2903
    • H10P14/2904
    • H10P14/2905
    • H10P14/3208
    • H10P14/3238
    • H10P14/3248
    • H10P14/3411
    • H10P14/3421
AU2002337297A 2001-10-23 2002-10-21 Lateral semiconductor-on-insulator structure and corresponding manufacturing methods Abandoned AU2002337297A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US33050601P 2001-10-23 2001-10-23
US60/330,506 2001-10-23
PCT/GB2002/004738 WO2003036699A2 (en) 2001-10-23 2002-10-21 Lateral semiconductor-on-insulator structure and corresponding manufacturing methods

Publications (1)

Publication Number Publication Date
AU2002337297A1 true AU2002337297A1 (en) 2003-05-06

Family

ID=23290061

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002337297A Abandoned AU2002337297A1 (en) 2001-10-23 2002-10-21 Lateral semiconductor-on-insulator structure and corresponding manufacturing methods

Country Status (2)

Country Link
AU (1) AU2002337297A1 (en)
WO (1) WO2003036699A2 (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7033912B2 (en) 2004-01-22 2006-04-25 Cree, Inc. Silicon carbide on diamond substrates and related devices and methods
US7612390B2 (en) 2004-02-05 2009-11-03 Cree, Inc. Heterojunction transistors including energy barriers
US7594075B2 (en) * 2004-10-20 2009-09-22 Seagate Technology Llc Metadata for a grid based data storage system
US7560322B2 (en) * 2004-10-27 2009-07-14 Northrop Grumman Systems Corporation Method of making a semiconductor structure for high power semiconductor devices
JP5017926B2 (en) * 2005-09-28 2012-09-05 株式会社デンソー Semiconductor device and manufacturing method thereof
US7592211B2 (en) 2006-01-17 2009-09-22 Cree, Inc. Methods of fabricating transistors including supported gate electrodes
US20130154049A1 (en) * 2011-06-22 2013-06-20 George IMTHURN Integrated Circuits on Ceramic Wafers Using Layer Transfer Technology
US10290702B2 (en) 2012-07-31 2019-05-14 Silanna Asia Pte Ltd Power device on bulk substrate
EP2880688B1 (en) * 2012-07-31 2020-07-15 Silanna Asia Pte Ltd. Power device integration on a common substrate
US9412881B2 (en) 2012-07-31 2016-08-09 Silanna Asia Pte Ltd Power device integration on a common substrate
CN104425257A (en) * 2013-08-30 2015-03-18 无锡华润上华半导体有限公司 Insulated gate bipolar transistor and manufacturing method thereof
US10083897B2 (en) 2017-02-20 2018-09-25 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact
US9923059B1 (en) 2017-02-20 2018-03-20 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors
FR3079662B1 (en) * 2018-03-30 2020-02-28 Soitec SUBSTRATE FOR RADIO FREQUENCY APPLICATIONS AND MANUFACTURING METHOD THEREOF
CN115706046B (en) * 2021-08-10 2025-11-14 苏州龙驰半导体科技有限公司 Composite structures of semiconductor wafers, semiconductor wafers and their fabrication methods and applications

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1114497A (en) * 1965-06-28 1968-05-22 Dow Corning Improvements in or relating to semiconductor devices
US5349207A (en) * 1993-02-22 1994-09-20 Texas Instruments Incorporated Silicon carbide wafer bonded to a silicon wafer
JP3324469B2 (en) * 1997-09-26 2002-09-17 信越半導体株式会社 Method for producing SOI wafer and SOI wafer produced by this method
DE19810828A1 (en) * 1998-03-12 1999-09-16 Siemens Ag Method for bonding two wafers
US6255195B1 (en) * 1999-02-22 2001-07-03 Intersil Corporation Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method
US6372600B1 (en) * 1999-08-30 2002-04-16 Agere Systems Guardian Corp. Etch stops and alignment marks for bonded wafers

Also Published As

Publication number Publication date
WO2003036699A3 (en) 2003-09-25
WO2003036699A2 (en) 2003-05-01

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase