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AU2002357591A1 - Substrate treating method - Google Patents

Substrate treating method

Info

Publication number
AU2002357591A1
AU2002357591A1 AU2002357591A AU2002357591A AU2002357591A1 AU 2002357591 A1 AU2002357591 A1 AU 2002357591A1 AU 2002357591 A AU2002357591 A AU 2002357591A AU 2002357591 A AU2002357591 A AU 2002357591A AU 2002357591 A1 AU2002357591 A1 AU 2002357591A1
Authority
AU
Australia
Prior art keywords
treating method
substrate treating
substrate
treating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002357591A
Inventor
Seiji Matsuyama
Masaru Sasaki
Takuya Sugawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of AU2002357591A1 publication Critical patent/AU2002357591A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H10D64/01344—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
AU2002357591A 2001-12-18 2002-12-16 Substrate treating method Abandoned AU2002357591A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2001385108A JP4048048B2 (en) 2001-12-18 2001-12-18 Substrate processing method
JP2001-385108 2001-12-18
PCT/JP2002/013134 WO2003052810A1 (en) 2001-12-18 2002-12-16 Substrate treating method

Publications (1)

Publication Number Publication Date
AU2002357591A1 true AU2002357591A1 (en) 2003-06-30

Family

ID=19187790

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002357591A Abandoned AU2002357591A1 (en) 2001-12-18 2002-12-16 Substrate treating method

Country Status (4)

Country Link
JP (1) JP4048048B2 (en)
AU (1) AU2002357591A1 (en)
TW (1) TW200301311A (en)
WO (1) WO2003052810A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2003231516A1 (en) 2002-05-16 2003-12-02 Tokyo Electron Limited Method of treating substrate
US20080233764A1 (en) * 2004-04-09 2008-09-25 Tsuyoshi Takahashi Formation of Gate Insulation Film
JP2006245528A (en) * 2005-02-01 2006-09-14 Tohoku Univ Dielectric film and method for forming the same
JP2007012788A (en) * 2005-06-29 2007-01-18 Elpida Memory Inc Manufacturing method of semiconductor device
JP2008192975A (en) * 2007-02-07 2008-08-21 Hitachi Kokusai Electric Inc Substrate processing method
JP6039996B2 (en) * 2011-12-09 2016-12-07 株式会社日立国際電気 Semiconductor device manufacturing method, substrate processing method, substrate processing apparatus, and program
JP6032963B2 (en) * 2012-06-20 2016-11-30 キヤノン株式会社 SOI substrate, method for manufacturing SOI substrate, and method for manufacturing semiconductor device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4001960B2 (en) * 1995-11-03 2007-10-31 フリースケール セミコンダクター インコーポレイテッド Method for manufacturing a semiconductor device having a nitrided oxide dielectric layer
JP3485403B2 (en) * 1995-11-28 2004-01-13 沖電気工業株式会社 Method for manufacturing semiconductor device
JPH1027795A (en) * 1996-07-12 1998-01-27 Toshiba Corp Method for manufacturing semiconductor device
JP3399413B2 (en) * 1999-09-13 2003-04-21 日本電気株式会社 Oxynitride film and method for forming the same
JP4731694B2 (en) * 2000-07-21 2011-07-27 東京エレクトロン株式会社 Semiconductor device manufacturing method and substrate processing apparatus
JP4713752B2 (en) * 2000-12-28 2011-06-29 財団法人国際科学振興財団 Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
TWI292441B (en) 2008-01-11
WO2003052810A1 (en) 2003-06-26
JP2003188172A (en) 2003-07-04
TW200301311A (en) 2003-07-01
JP4048048B2 (en) 2008-02-13

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase