AU2001288704A1 - Repairable dynamic programmable logic array - Google Patents
Repairable dynamic programmable logic arrayInfo
- Publication number
- AU2001288704A1 AU2001288704A1 AU2001288704A AU8870401A AU2001288704A1 AU 2001288704 A1 AU2001288704 A1 AU 2001288704A1 AU 2001288704 A AU2001288704 A AU 2001288704A AU 8870401 A AU8870401 A AU 8870401A AU 2001288704 A1 AU2001288704 A1 AU 2001288704A1
- Authority
- AU
- Australia
- Prior art keywords
- repairable
- programmable logic
- logic array
- dynamic programmable
- dynamic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17712—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays one of the matrices at least being reprogrammable
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/661,137 US6304102B1 (en) | 2000-09-13 | 2000-09-13 | Repairable dynamic programmable logic array |
| US09661137 | 2000-09-13 | ||
| PCT/US2001/027427 WO2002023724A1 (en) | 2000-09-13 | 2001-09-04 | Repairable dynamic programmable logic array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| AU2001288704A1 true AU2001288704A1 (en) | 2002-03-26 |
Family
ID=24652365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU2001288704A Abandoned AU2001288704A1 (en) | 2000-09-13 | 2001-09-04 | Repairable dynamic programmable logic array |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6304102B1 (en) |
| AU (1) | AU2001288704A1 (en) |
| TW (1) | TW518739B (en) |
| WO (1) | WO2002023724A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7207183B2 (en) | 2004-04-12 | 2007-04-24 | York International Corp. | System and method for capacity control in a multiple compressor chiller system |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1195119B (en) * | 1986-08-04 | 1988-10-12 | Cselt Centro Studi Lab Telecom | REFERENCES TO THE LOGI BOARDS THAT PROGRAMMABLE DYNAMICS WITH NOR NOR STRUCTURE MADE IN TECHNOLOGY ALREADY MOS |
| US5287017A (en) * | 1992-05-15 | 1994-02-15 | Micron Technology, Inc. | Programmable logic device macrocell with two OR array inputs |
| US6229338B1 (en) * | 2000-02-04 | 2001-05-08 | International Business Machines Corporation | Method and apparatus for reducing dynamic programmable logic array propagation delay |
-
2000
- 2000-09-13 US US09/661,137 patent/US6304102B1/en not_active Expired - Lifetime
-
2001
- 2001-09-04 AU AU2001288704A patent/AU2001288704A1/en not_active Abandoned
- 2001-09-04 WO PCT/US2001/027427 patent/WO2002023724A1/en not_active Ceased
- 2001-09-12 TW TW090122534A patent/TW518739B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| WO2002023724A1 (en) | 2002-03-21 |
| TW518739B (en) | 2003-01-21 |
| US6304102B1 (en) | 2001-10-16 |
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