AU2001281164A1 - Inter-device communication interface - Google Patents
Inter-device communication interfaceInfo
- Publication number
- AU2001281164A1 AU2001281164A1 AU2001281164A AU8116401A AU2001281164A1 AU 2001281164 A1 AU2001281164 A1 AU 2001281164A1 AU 2001281164 A AU2001281164 A AU 2001281164A AU 8116401 A AU8116401 A AU 8116401A AU 2001281164 A1 AU2001281164 A1 AU 2001281164A1
- Authority
- AU
- Australia
- Prior art keywords
- inter
- communication interface
- device communication
- interface
- communication
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/323—Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F30/343—Logical level
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Devices For Executing Special Programs (AREA)
- Communication Control (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US22347100P | 2000-08-07 | 2000-08-07 | |
| US60/223,471 | 2000-08-07 | ||
| PCT/US2001/024786 WO2002013072A2 (en) | 2000-08-07 | 2001-08-07 | Inter-device communication interface |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| AU2001281164A1 true AU2001281164A1 (en) | 2002-02-18 |
Family
ID=22836634
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU2001283549A Abandoned AU2001283549A1 (en) | 2000-08-07 | 2001-08-07 | Software-to-hardware compiler |
| AU2001281164A Abandoned AU2001281164A1 (en) | 2000-08-07 | 2001-08-07 | Inter-device communication interface |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU2001283549A Abandoned AU2001283549A1 (en) | 2000-08-07 | 2001-08-07 | Software-to-hardware compiler |
Country Status (4)
| Country | Link |
|---|---|
| US (3) | US7257780B2 (en) |
| EP (2) | EP1356401A2 (en) |
| AU (2) | AU2001283549A1 (en) |
| WO (2) | WO2002013004A2 (en) |
Families Citing this family (62)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7266725B2 (en) | 2001-09-03 | 2007-09-04 | Pact Xpp Technologies Ag | Method for debugging reconfigurable architectures |
| DE19651075A1 (en) | 1996-12-09 | 1998-06-10 | Pact Inf Tech Gmbh | Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like |
| DE19654595A1 (en) | 1996-12-20 | 1998-07-02 | Pact Inf Tech Gmbh | I0 and memory bus system for DFPs as well as building blocks with two- or multi-dimensional programmable cell structures |
| DE59710317D1 (en) | 1996-12-27 | 2003-07-24 | Pact Inf Tech Gmbh | METHOD FOR THE INDEPENDENT DYNAMIC RE-LOADING OF DATA FLOW PROCESSORS (DFPs) AND MODULES WITH TWO OR MORE-DIMENSIONAL PROGRAMMABLE CELL STRUCTURES (FPGAs, DPGAs, or the like) |
| US6542998B1 (en) | 1997-02-08 | 2003-04-01 | Pact Gmbh | Method of self-synchronization of configurable elements of a programmable module |
| US8686549B2 (en) | 2001-09-03 | 2014-04-01 | Martin Vorbach | Reconfigurable elements |
| DE19861088A1 (en) | 1997-12-22 | 2000-02-10 | Pact Inf Tech Gmbh | Repairing integrated circuits by replacing subassemblies with substitutes |
| EP1351153A3 (en) * | 1998-11-20 | 2008-11-05 | Altera Corporation | Reconfigurable programmable logic device computer system |
| AU5805300A (en) | 1999-06-10 | 2001-01-02 | Pact Informationstechnologie Gmbh | Sequence partitioning in cell structures |
| DE50115584D1 (en) | 2000-06-13 | 2010-09-16 | Krass Maren | PIPELINE CT PROTOCOLS AND COMMUNICATION |
| WO2002013004A2 (en) | 2000-08-07 | 2002-02-14 | Altera Corporation | Software-to-hardware compiler |
| US7343594B1 (en) | 2000-08-07 | 2008-03-11 | Altera Corporation | Software-to-hardware compiler with symbol set inference analysis |
| US8058899B2 (en) | 2000-10-06 | 2011-11-15 | Martin Vorbach | Logic cell array and bus system |
| US7444531B2 (en) | 2001-03-05 | 2008-10-28 | Pact Xpp Technologies Ag | Methods and devices for treating and processing data |
| WO2005045692A2 (en) | 2003-08-28 | 2005-05-19 | Pact Xpp Technologies Ag | Data processing device and method |
| US7844796B2 (en) | 2001-03-05 | 2010-11-30 | Martin Vorbach | Data processing device and method |
| US9037807B2 (en) | 2001-03-05 | 2015-05-19 | Pact Xpp Technologies Ag | Processor arrangement on a chip including data processing, memory, and interface elements |
| US7657877B2 (en) | 2001-06-20 | 2010-02-02 | Pact Xpp Technologies Ag | Method for processing data |
| US7996827B2 (en) | 2001-08-16 | 2011-08-09 | Martin Vorbach | Method for the translation of programs for reconfigurable architectures |
| US7434191B2 (en) | 2001-09-03 | 2008-10-07 | Pact Xpp Technologies Ag | Router |
| US8686475B2 (en) | 2001-09-19 | 2014-04-01 | Pact Xpp Technologies Ag | Reconfigurable elements |
| US7577822B2 (en) | 2001-12-14 | 2009-08-18 | Pact Xpp Technologies Ag | Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization |
| WO2003060747A2 (en) | 2002-01-19 | 2003-07-24 | Pact Xpp Technologies Ag | Reconfigurable processor |
| EP2043000B1 (en) | 2002-02-18 | 2011-12-21 | Richter, Thomas | Bus systems and reconfiguration method |
| US8914590B2 (en) | 2002-08-07 | 2014-12-16 | Pact Xpp Technologies Ag | Data processing method and device |
| US8190765B2 (en) * | 2002-06-25 | 2012-05-29 | Intel Corporation | Data reception management apparatus, systems, and methods |
| WO2004021176A2 (en) | 2002-08-07 | 2004-03-11 | Pact Xpp Technologies Ag | Method and device for processing data |
| US7657861B2 (en) | 2002-08-07 | 2010-02-02 | Pact Xpp Technologies Ag | Method and device for processing data |
| EP1537486A1 (en) | 2002-09-06 | 2005-06-08 | PACT XPP Technologies AG | Reconfigurable sequencer structure |
| JP2005018626A (en) * | 2003-06-27 | 2005-01-20 | Ip Flex Kk | Method for generating parallel processing system |
| WO2005073866A2 (en) * | 2004-01-21 | 2005-08-11 | Charles Stark Draper Laboratory, Inc. | Systems and methods for reconfigurable computing |
| WO2005086746A2 (en) * | 2004-03-04 | 2005-09-22 | Trustees Of Boston University | Programmable-logic acceleraton of data processing applications |
| US7493606B2 (en) * | 2004-08-03 | 2009-02-17 | Université du Québec à Chicoutimi (UQAC) | Method for compiling and executing a parallel program |
| US7519823B1 (en) | 2004-08-12 | 2009-04-14 | Xilinx, Inc. | Concealed, non-intrusive watermarks for configuration bitstreams |
| US7406673B1 (en) * | 2004-08-12 | 2008-07-29 | Xilinx, Inc. | Method and system for identifying essential configuration bits |
| EP1762933B1 (en) * | 2005-08-30 | 2010-10-27 | Sony Ericsson Mobile Communications AB | Method and software for optimising the positioning of software functions in a memory |
| US20070139074A1 (en) * | 2005-12-19 | 2007-06-21 | M2000 | Configurable circuits with microcontrollers |
| JP2009524134A (en) | 2006-01-18 | 2009-06-25 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | Hardware definition method |
| US8443351B2 (en) * | 2006-02-23 | 2013-05-14 | Microsoft Corporation | Parallel loops in a workflow |
| US8001540B2 (en) * | 2006-08-08 | 2011-08-16 | International Business Machines Corporation | System, method and program product for control of sequencing of data processing by different programs |
| US8230406B2 (en) * | 2006-09-11 | 2012-07-24 | International Business Machines Corporation | Compiler option consistency checking during incremental hardware design language compilation |
| US8429613B2 (en) * | 2006-10-31 | 2013-04-23 | Microsoft Corporation | Stepping and application state viewing between points |
| US20080222581A1 (en) | 2007-03-09 | 2008-09-11 | Mips Technologies, Inc. | Remote Interface for Managing the Design and Configuration of an Integrated Circuit Semiconductor Design |
| JP5109764B2 (en) * | 2008-03-31 | 2012-12-26 | 日本電気株式会社 | Description processing apparatus, description processing method, and program |
| US8959496B2 (en) * | 2010-04-21 | 2015-02-17 | Microsoft Corporation | Automatic parallelization in a tracing just-in-time compiler system |
| US8549504B2 (en) | 2010-09-25 | 2013-10-01 | Intel Corporation | Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic region |
| EP2718859A1 (en) * | 2011-06-08 | 2014-04-16 | Hyperion Core, Inc. | Tool-level and hardware-level code optimization and respective hardware modification |
| US8966457B2 (en) | 2011-11-15 | 2015-02-24 | Global Supercomputing Corporation | Method and system for converting a single-threaded software program into an application-specific supercomputer |
| US9489184B2 (en) * | 2011-12-30 | 2016-11-08 | Oracle International Corporation | Adaptive selection of programming language versions for compilation of software programs |
| US20130212366A1 (en) * | 2012-02-09 | 2013-08-15 | Altera Corporation | Configuring a programmable device using high-level language |
| US8959469B2 (en) | 2012-02-09 | 2015-02-17 | Altera Corporation | Configuring a programmable device using high-level language |
| CN103455313B (en) * | 2012-05-31 | 2017-03-22 | 国际商业机器公司 | Method and device for associating input information with output information of detected system |
| US9525621B2 (en) * | 2012-08-29 | 2016-12-20 | Marvell World Trade Ltd. | Semaphore soft and hard hybrid architecture |
| US9520180B1 (en) | 2014-03-11 | 2016-12-13 | Hypres, Inc. | System and method for cryogenic hybrid technology computing and memory |
| US9547738B1 (en) * | 2014-05-08 | 2017-01-17 | Altera Corporation | Invariant code optimization in high-level FPGA synthesis |
| US9940097B1 (en) * | 2014-10-29 | 2018-04-10 | Netronome Systems, Inc. | Registered FIFO |
| US10061590B2 (en) * | 2015-01-07 | 2018-08-28 | Micron Technology, Inc. | Generating and executing a control flow |
| US9984037B1 (en) | 2015-04-27 | 2018-05-29 | Synaptic Engines, Llc | Scheduler for a fine grained graph processor |
| US10628142B2 (en) | 2017-07-20 | 2020-04-21 | Texas Instruments Incorporated | Loop break |
| CN114270308A (en) * | 2019-08-22 | 2022-04-01 | 谷歌有限责任公司 | Compilation of synchronous processors |
| US11520570B1 (en) | 2021-06-10 | 2022-12-06 | Xilinx, Inc. | Application-specific hardware pipeline implemented in an integrated circuit |
| US12039381B2 (en) * | 2022-09-27 | 2024-07-16 | Amazon Technologies, Inc. | On-demand code execution data management |
Family Cites Families (48)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1444084A (en) | 1972-06-21 | 1976-07-28 | Honeywell Inf Systems | Generalized logic device |
| US4442504A (en) * | 1981-03-09 | 1984-04-10 | Allen-Bradley Company | Modular programmable controller |
| US5152000A (en) | 1983-05-31 | 1992-09-29 | Thinking Machines Corporation | Array communications arrangement for parallel processor |
| US5142625A (en) | 1985-06-12 | 1992-08-25 | Minolta Camera Kabushiki Kaisha | One-chip microcomputer including a programmable logic array for interrupt control |
| US5134884A (en) * | 1986-05-02 | 1992-08-04 | Forrest Anderson | Single pulse imaging device |
| US5068823A (en) | 1988-07-11 | 1991-11-26 | Star Semiconductor Corporation | Programmable integrated circuit using topological and parametric data to selectively connect and configure different high level functional blocks thereof |
| DE69031257T2 (en) | 1989-09-21 | 1998-02-12 | Texas Instruments Inc | Integrated circuit with an embedded digital signal processor |
| US5128871A (en) | 1990-03-07 | 1992-07-07 | Advanced Micro Devices, Inc. | Apparatus and method for allocation of resoures in programmable logic devices |
| US5541849A (en) * | 1990-04-06 | 1996-07-30 | Lsi Logic Corporation | Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of timing parameters |
| US5684980A (en) | 1992-07-29 | 1997-11-04 | Virtual Computer Corporation | FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions |
| US5442792A (en) * | 1992-08-07 | 1995-08-15 | Hughes Aircraft Company | Expert system compilation method |
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| US6871341B1 (en) * | 2000-03-24 | 2005-03-22 | Intel Corporation | Adaptive scheduling of function cells in dynamic reconfigurable logic |
| US6467075B1 (en) * | 2000-03-24 | 2002-10-15 | Nec Corporation | Resolution of dynamic memory allocation/deallocation and pointers |
| EP1742159A3 (en) | 2000-08-07 | 2007-06-20 | Altera Corporation | Software-to-Hardware compiler |
| WO2002013004A2 (en) | 2000-08-07 | 2002-02-14 | Altera Corporation | Software-to-hardware compiler |
-
2001
- 2001-08-07 WO PCT/US2001/041624 patent/WO2002013004A2/en not_active Ceased
- 2001-08-07 EP EP01962358A patent/EP1356401A2/en not_active Ceased
- 2001-08-07 AU AU2001283549A patent/AU2001283549A1/en not_active Abandoned
- 2001-08-07 WO PCT/US2001/024786 patent/WO2002013072A2/en not_active Ceased
- 2001-08-07 US US09/924,274 patent/US7257780B2/en not_active Expired - Fee Related
- 2001-08-07 US US09/924,272 patent/US7219342B2/en not_active Expired - Fee Related
- 2001-08-07 EP EP01959629A patent/EP1356400A2/en not_active Ceased
- 2001-08-07 AU AU2001281164A patent/AU2001281164A1/en not_active Abandoned
-
2006
- 2006-09-22 US US11/526,198 patent/US8473926B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| WO2002013072A2 (en) | 2002-02-14 |
| EP1356401A2 (en) | 2003-10-29 |
| US20020100032A1 (en) | 2002-07-25 |
| US8473926B2 (en) | 2013-06-25 |
| WO2002013004A2 (en) | 2002-02-14 |
| US20070169033A1 (en) | 2007-07-19 |
| WO2002013072A8 (en) | 2003-10-23 |
| US20020124238A1 (en) | 2002-09-05 |
| WO2002013072A3 (en) | 2003-08-21 |
| US7257780B2 (en) | 2007-08-14 |
| WO2002013004A3 (en) | 2003-08-21 |
| US7219342B2 (en) | 2007-05-15 |
| EP1356400A2 (en) | 2003-10-29 |
| AU2001283549A1 (en) | 2002-02-18 |
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