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AU2001268304A1 - Method and apparatus for adjusting the phase of input/output circuitry - Google Patents

Method and apparatus for adjusting the phase of input/output circuitry

Info

Publication number
AU2001268304A1
AU2001268304A1 AU2001268304A AU6830401A AU2001268304A1 AU 2001268304 A1 AU2001268304 A1 AU 2001268304A1 AU 2001268304 A AU2001268304 A AU 2001268304A AU 6830401 A AU6830401 A AU 6830401A AU 2001268304 A1 AU2001268304 A1 AU 2001268304A1
Authority
AU
Australia
Prior art keywords
circuit
clock
phase
input
phase adjustment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001268304A
Inventor
Chi-Yeu Chao
Songmin Kim
Chee Lim
Gregory Taylor
Keng Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2001268304A1 publication Critical patent/AU2001268304A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Pulse Circuits (AREA)
  • Networks Using Active Elements (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Input/output (I/O) clock phase adjustment circuitry for use with I/O buffer circuitry of an integrated circuit chip. In one embodiment, an integrated circuit chip includes a phase adjustment circuit coupled to receive a system clock. The phase adjustment circuit generates an I/O clock coupled to be received by an I/O buffer circuit of an integrated circuit chip for I/O data transfers in a system. The phase adjustment circuit includes a phase locked loop (PLL) circuit coupled to receive the system clock through a first delay circuit. The I/O clock generated by the PLL circuit is received through a second delay circuit at a feedback clock input of the PLL circuit. The first and second delay circuits are used to control the phase of the I/O clock generated by the PLL circuit relative to the system clock. In one embodiment, a third delay circuit is included in an I/O data path of the I/O buffer circuit of the integrated circuit. The third delay circuit enables input and output data transmissions from the integrated circuit to be clocked, in effect, out of phase with the I/O clock generated by phase adjustment circuit.
AU2001268304A 2000-06-26 2001-06-07 Method and apparatus for adjusting the phase of input/output circuitry Abandoned AU2001268304A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/604,049 US6748549B1 (en) 2000-06-26 2000-06-26 Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock
US09/604,049 2000-06-26
PCT/US2001/018754 WO2002001233A2 (en) 2000-06-26 2001-06-07 Method and apparatus for adjusting the phase of input/output circuitry

Publications (1)

Publication Number Publication Date
AU2001268304A1 true AU2001268304A1 (en) 2002-01-08

Family

ID=24417975

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001268304A Abandoned AU2001268304A1 (en) 2000-06-26 2001-06-07 Method and apparatus for adjusting the phase of input/output circuitry

Country Status (8)

Country Link
US (1) US6748549B1 (en)
EP (1) EP1295134B1 (en)
CN (1) CN1287527C (en)
AT (1) ATE441868T1 (en)
AU (1) AU2001268304A1 (en)
DE (1) DE60139777D1 (en)
TW (1) TW530197B (en)
WO (1) WO2002001233A2 (en)

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US7616036B1 (en) 2005-09-12 2009-11-10 Virage Logic Corporation Programmable strobe and clock generator
US7571267B1 (en) * 2006-03-27 2009-08-04 Integrated Device Technology, Inc. Core clock alignment circuits that utilize clock phase learning operations to achieve accurate clocking of data derived from serial data streams having different relative skews
CN101420510B (en) * 2007-10-26 2014-06-11 瑞昱半导体股份有限公司 Device for generating clock applied to multimedia interface and related method
IT1397376B1 (en) * 2009-12-30 2013-01-10 St Microelectronics Srl ADJUSTMENT OF A PROGRAMMABLE DELAY LINE TO PSEUDO-CLOSED RING
CN102859879B (en) * 2010-05-13 2015-03-11 华为技术有限公司 System and method for verifying output frequency in a phase locked loop
CN102281063A (en) * 2010-06-10 2011-12-14 中兴通讯股份有限公司 Method and device for adjusting frequencies
TWI482030B (en) * 2011-06-21 2015-04-21 Via Tech Inc Apparatus and method for advanced synchronous strobe transmission, optimized synchronous strobe transmission mechanism, apparatus and method for delayed synchronous data reception, optimized synchronized data reception mechanism, programmable mechanism f
US20140003564A1 (en) * 2012-06-27 2014-01-02 Broadcom Corporation Multichip synchronization system
GB2513529A (en) 2012-11-15 2014-11-05 Ibm System and method of low latency data tranfer between clock domains operated in various synchronization modes
KR102006243B1 (en) * 2012-12-24 2019-08-01 에스케이하이닉스 주식회사 Data write circuit of semiconductor apparatus
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US9286961B1 (en) * 2015-03-30 2016-03-15 Apple Inc. Memory controller half-clock delay adjustment
CN105759195A (en) * 2016-02-24 2016-07-13 复旦大学 Setup-hold time test system and setup-hold time test method based on fine phase modulation
US10324879B2 (en) 2016-09-28 2019-06-18 International Business Machines Corporation Mitigation of side effects of simultaneous switching of input/output (I/O data signals
US11153067B2 (en) 2019-05-14 2021-10-19 Space Exploration Technologies Corp. Chip to chip time synchronization
US11133806B1 (en) * 2019-05-14 2021-09-28 Space Exploration Technologies Corp. Phase lock loop (PLL) synchronization
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Also Published As

Publication number Publication date
DE60139777D1 (en) 2009-10-15
US6748549B1 (en) 2004-06-08
CN1528051A (en) 2004-09-08
EP1295134B1 (en) 2009-09-02
WO2002001233A3 (en) 2002-08-01
WO2002001233A2 (en) 2002-01-03
EP1295134A2 (en) 2003-03-26
TW530197B (en) 2003-05-01
ATE441868T1 (en) 2009-09-15
CN1287527C (en) 2006-11-29

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