JP2000347764A - Circuit block connection method and semiconductor integrated circuit connection method using PLL - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce variation in LSI output data delay variation due to LSI process variation, power supply voltage variation, ambient temperature variation, etc., which poses a problem in data transfer between LSIs operating with the same clock. To reduce. A feedback path to a PLL input section is provided by a clock distribution circuit (11) and a PLL feedback clock output buffer (21).
, A PLL feedback loop wiring 22, and a PLL feedback clock input buffer 20. On the other hand, a data output buffer 8 which synchronizes the data transmission path with the clock output from the clock distribution circuit 11 and outputs the data to the next LSI. When,
And data wiring 14 for transmitting data to the next-stage LSI.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data transfer between circuit blocks and between semiconductor integrated circuits (hereinafter referred to as "LSI") in data transmission between apparatuses and within the apparatus. LSI
It is to reduce delay variation (clock skew) of output data due to use environment such as process variation, power supply voltage variation, and ambient temperature variation. Thereby, the timing margin at the time of data transfer is increased, and high-speed transmission is possible.

[0002]

2. Description of the Related Art Conventionally used technologies include:
As shown in FIG. 9, a PLL (Phase Locked)
There is a method of reducing clock skew between LSIs using a PLL below Loop. The system clock (CKIN) distributed to each LSI is a clock distribution circuit 11a.
, And is supplied to each subsequent flip-flop.

Since the number of buffers and the number of loads constituting the clock distribution circuit 11a are different for each LSI, the output data (DTOUT) is input from the input of the system clock (CKIN).
The delays until are also different. Therefore, the PLL 12a is incorporated in each of the LSIs 1 and 2, and the clock distribution circuit 11
By taking a into the feedback loop of the PLL 12a, the phase can be adjusted and the clock skew between the LSIs can be reduced.

An example of the above configuration is disclosed in, for example,
No. 21773. Here, the PLL
A method of adjusting a phase by providing a terminal capable of monitoring a feedback clock and a variable delay circuit in a feedback loop is disclosed.

[0005]

FIG. 10 shows a PLL12.
1 shows a specific circuit configuration of an LSI 1 incorporating a. In FIG. 10, a data transmission processing path is partially omitted. A system clock (CKIN) serving as a PLL reference clock 15a is input from a clock input terminal 3a of the LSI 1. The output signal of the PLL is distributed by the clock distribution circuit 11a, and the clock of each flip-flop and P
It is supplied as the LL feedback clock 13a. PLL12
a from output to flip-flop input clock,
Assuming that the delay time from the output of L12a to the input of the PLL feedback clock 13a is the same, the PLL matches the phases of the reference clock 15a and the PLL feedback clock 13a at the PLL input terminal, so that the reference clock phase and the flip-flop input clock phase are PLL1
The delay time of 2a and the clock distribution circuit 11a becomes zero. The delay time of the system clock input buffer 6a is Tpd1, the delay time of the output data flip-flop 10a is Tpd2, the delay time of the LSI output data output buffer 8a is Tpd3, and the delay time of the data wiring 14 between the LSIs is Tpd4. Then, the system clock (CKI
N) Data up to LSI2 input 4b (DTIN)
The delay time is

[0006]

(Equation 1)

[0007]

In general, the characteristics of an LSI generally vary from 0.5 to 1.5 times the reference value due to the use environment such as LSI process variations, power supply voltage fluctuations, and ambient temperature changes. (DTIN)
Causes an uncertain time (uncertain region) due to a delay variation of 0.5 to 1.5 times ΔT1, and a delay variation as shown in FIG. 11 occurs. However, in order to transfer data accurately between LSIs, the variation in the delay variation is a serious problem. This variation reduces the timing margin and limits the data transfer rate.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the delay variation of output data by a relatively simple method and to reduce the adjustment work as much as possible.

[0010]

In order to solve the above-mentioned problems, in a method for connecting a plurality of circuit blocks provided with a clock supply circuit for inputting a system clock to a PLL and adjusting a phase by using the PLL, A feedback path from the PLL output to the PLL feedback clock input unit is provided by the PLL
A clock distribution circuit that distributes an output clock, a PLL feedback clock output buffer that buffers a PLL feedback clock output from the clock distribution circuit,
A PLL feedback loop wiring for feeding back the PLL feedback clock; and a PLL feedback clock input buffer for inputting the PLL feedback clock transmitted through the PLL feedback loop wiring to the PLL feedback input unit. A data output buffer for synchronizing the processed data with a clock output from the clock distribution circuit and outputting the processed data to a next-stage circuit block on a data transmission path for processing the captured data and outputting the processed data to the next-stage circuit block And data wiring for transmitting the data to the next circuit block.

Further, the invention is characterized in that the above-mentioned circuit block is constituted by one semiconductor integrated circuit.

Further, the present invention is characterized in that the PLL feedback loop wiring is set outside the semiconductor integrated circuit by the connection method described above.

Further, the delay time of the PLL feedback clock input buffer and the delay time of the system clock input buffer of the PLL are set to be the same by the connection method described above, and the delay time of the PLL feedback clock output buffer and the delay time of the data output buffer are set. Are set to be the same, and the delay time of the PLL feedback loop wiring and the delay time of the data wiring are set to be the same.

Further, a delay circuit is inserted in the feedback path to the feedback clock input section by the above-described connection method.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention. Two LSIs, LSI 16 and LSI 17 in the figure, operate on a system clock (CKIN). L
The main component of the SI 16 is an input flip-flop 9
c, data processing unit 36c, PLL 12c, clock input buffer 6c, PLL feedback clock input buffer 20
c, clock distribution circuit 11c, output flip-flop 1
0c, a data output buffer 8c, and a PLL feedback clock output buffer 21c. On the other hand, the main components of the LSI 17 are an input flip-flop 9 d and a data processing unit 36.
d, PLL 12d, clock input buffer 6d, PLL
Feedback clock input buffer 20d, clock distribution circuit 1
1d, an output flip-flop 10d, a data output buffer 8d, and a PLL feedback clock output buffer 21d. At this time, it goes without saying that each data processing unit operates with the clock distributed by each clock distribution circuit. The details of the LSI 16 will be described below.

FIG. 2 illustrates the LSI 16 of FIG. 1 in detail. In FIG. 2, a data transmission processing path is partially omitted. Hereinafter, the reduction of the clock skew for the LSI 16 will be described. In the figure, L
From the SI clock input terminal 3c, the system clock (C
KIN). This system clock (CKI
N) passes through the input buffer 6c and is supplied as the reference clock 15c of the PLL 12c. The PLL output signal is branched by the clock distribution circuit 11c and used as a clock for each flip-flop. After processing the data internally, the LSI passes the data (DTOUT) through the output flip-flop 10c and the output buffer 8c to the LS
Send it to I17. At the same time, the PLL output includes the clock distribution circuit 11c, output buffer 21c, output terminal 19c, LS
PLL by a feedback loop composed of a feedback loop wiring 22c, an input terminal 18c, and an input buffer 20c outside the I.
The feedback clock 13c is supplied to the PLL 12c. The LSI 17 for the system clock (CKIN) at this time
Delay time ΔT2 of data (DTIN) up to input 4d
Is Tpd1, the delay time of the output flip-flop 10c is Tpd2, the delay time of the output buffer 8c is Tpd3, the delay time of the data wiring 14 between the LSIs is Tpd4, and the delay time of the input buffer 20c is The time is Tpd5, the delay time of the output buffer 21c is Tpd6, P
Assuming that the delay time of the LL feedback loop wiring 22c is Tpd7,

[0017]

(Equation 2)

Is obtained. Here, the input buffer 6c and the input buffer 20c, the output buffer 8c and the output buffer 2
In 1c, if the same buffer in the same chip is used, the delay times are almost equal, so that Tpd1 = Tpd5, Tpd3 =
Tpd6, and data wiring 14 between LSI and PLL
If the delay of the feedback loop wiring 22c is made equal, Tpd4 = T
pd7, and the delay time ΔT3 of the data (DTIN) up to the input 4 of the receiving LSI 17 with respect to the system clock (CKIN) is

[0019]

(Equation 3)

And only the delay time term of the flip-flop. The delay time ΔT3 (= Tpd2) is the delay time ΔT1 (= Tpd1 + Tpd2 + Tpd3 +
Tpd4) is smaller than ΔT3 <ΔT1.

As a result, as shown in FIG. 3, the uncertainty area, which is the variation of the delay variation width (about 0.5 to 1.5 times the reference value) due to the use environment, can be made very small as compared with the related art. It becomes possible. That is, by taking the term that causes clock skew into the PLL feedback loop, the term becomes P
The LL phase control function can cancel the clock skew and reduce the clock skew due to the usage environment.

In order to further make the delay time of each buffer the same, each unit cell constituting the buffer on the same chip is designed to have the same size, and is arranged close to each other, and the wiring length and the wiring width are set. And the wiring state may be arranged as much as possible. Conversely, a design may be made by intentionally changing the parameters of the unit cell and changing the conditions such as the wiring length and the wiring width. Furthermore, if the layout position of each LSI on the substrate is determined, it goes without saying that the data wiring length and the feedback loop wiring length are determined depending on each other. What has been described above can be similarly applied to the following description.

FIG. 4 shows another embodiment of the above circuit configuration. In this embodiment, an internal buffer 24e having a delay characteristic equivalent to the LSI input buffer 6e, an internal buffer 25e having a delay characteristic equivalent to the LSI output buffer 8e, and a delay equivalent to the data line 14 between the LSIs are shown in FIG. The internal buffer 23e forms the PLL feedback loop. This configuration is a system in which the feedback circuit shown in the embodiment of FIG. 1 is incorporated in the LSI, and similar effects can be obtained.

As shown in FIG. 5, depending on the configuration of the device, the system clock (MCKI
N), and the output data of the LSI 16 is synchronized with the clock (CKIN) supplied from the LSI 26 to the LSI 16.
Data may be transferred between them.

FIG. 6 shows an embodiment of the apparatus configuration shown in FIG. In FIG. 6, a data transmission processing path is partially omitted. In the figure, an LSI 16 is the LSI 16 of the embodiment shown in FIG. 1, and an LSI 26 has a configuration in which a clock output terminal 29g is provided based on the configuration of the LSI 17f of the embodiment shown in FIG. In the LSI 26, the system clock (MCKIN) input from the system clock input terminal 28g passes through the input buffer 6g and is supplied as a PLL reference clock. The PLL output signal is branched by the clock distribution circuit 11g and used as a clock for each flip-flop. At the same time, the internal buffer 2 having a delay characteristic equivalent to the input buffer 6g
4g and an internal buffer 25g having a delay characteristic equivalent to that of the output buffer 21g constitute a PLL internal feedback loop and serve as a feedback clock for the PLL. The clock (CKIN) of the LSI 16 is output from the clock distribution circuit 11c via the output buffer 21c (CKOUT).
Is done. Here, assuming that the delay times of the respective elements are Tpd1 to Tpd13 as shown in FIG. 3, the input data (DT) of the LSI 26 with respect to the output clock (CKOUT) of the LSI 26
The delay time ΔT4 of IN) is the same as in the above embodiment.

[0026]

(Equation 4)

Is obtained. Here, if the same buffers are used for the input buffers 6c and 17c and the output buffers 8c and 21c of the LSI 16, Tpd1 = Tpd5 and Tpd3 = Tpd6. If the feedback loop wiring 22c and the data wiring 14 + clock wiring 27 are made equal in length, Tpd7 = Tpd4 + Tpd8
Therefore, the delay time ΔT5 becomes

[0028]

(Equation 5)

Term only. Further, the data delay time ΔT6 with respect to the clock in the input flip-flop 9g of the LSI 26 is

[0030]

(Equation 6)

Assuming that the input buffers 6g and 7g and the internal buffer 24g and the output buffer 21g and the internal buffer 25g have equivalent delay characteristics, respectively,
Tpd9 = Tpd10 = Tpd11, Tpd12 = Tpd13, and the delay time ΔT7

[0032]

(Equation 7)

Thus, the effect of reducing the clock skew is preserved up to the input of the input flip-flop 9g. As described above, by applying this circuit configuration, a data input (DTIN) having a small delay time and a small skew with respect to the output clock (CKIN) of the LSI 26 can be obtained, so that high-speed data transfer can be performed.

FIG. 7 shows an embodiment relating to the control of the output data phase by the above circuit configuration. In the figure, the delay of the output data (DTOUT) can be arbitrarily varied with respect to the system clock (CKIN) by inserting the delay circuit 30 into the PLL feedback loop. As a result, even if the wiring length between the LSIs varies, the transmission LS
The phase of the output data of I can be corrected, and data transfer between LSIs becomes possible.

The present invention can also be applied to a printed circuit board. FIG. 8 shows an embodiment on a printed circuit board. The printed circuit board 31 is the connector 3
2. It comprises a receiving interface IC 33, a transmitting interface IC 34, a clock PLL 35, and a data processing LSI. Receiving interface IC33
The transmission interface IC 34 includes the input buffers 6c and 20c and the output buffer 8 shown in FIG.
c, 21c, the clock PLL 31
By taking these into the feedback loop of the above, the effect of reducing clock skew can be obtained even in data transfer between printed circuit boards.

[0036]

According to the present invention, it is possible to cancel a delay element which causes a delay variation due to a use environment,
In particular, it is possible to reduce skew, which is a problem in high-speed data transfer. Further, the phase adjustment work conventionally performed can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an LS using a PLL outer loop according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating data transfer between I.

FIG. 2 is a configuration diagram of a clock skew reduction method using a PLL outer loop according to an embodiment of the present invention.

FIG. 3 is a timing chart for explaining a delay variation of output data in the above configuration of the present invention.

FIG. 4 is a configuration diagram of a clock skew reduction method by inserting a PLL internal loop buffer according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating another example of data transfer between LSIs using the embodiment of the present invention.

FIG. 6 is a diagram illustrating a circuit configuration for realizing the above configuration of the present invention.

FIG. 7 is a diagram for explaining a delay control method for output data using the embodiment of the present invention.

FIG. 8 is a diagram illustrating a circuit configuration for realizing an embodiment of the present invention on a printed circuit board.

FIG. 9 is a diagram illustrating a conventional data transfer between LSIs at the same clock.

FIG. 10 is a configuration diagram of a conventional clock skew reduction method using a PLL.

FIG. 11 is a timing chart illustrating delay fluctuation of output data in a conventional configuration.

[Description of Signs] 1, 2, ... conventional LSI, 3a, 3b, 3c, 3d, 3e, 3f ... clock input terminal, 4a, 4b, 4c, 4d, 4f, 4g ... data input terminal, 5a, 5b, 5c 5d, 5e, 5f ... data output terminals, 6a, 6b, 6c, 6d, 6e, 6f, 6g ... clock input buffers, 7a, 7b, 7c, 7d, 7f, 7g ... data input buffers, 8a, 8b, 8c , 8d, 8e, 8f... Data output buffers, 9a, 9b, 9c, 9d, 9f, 9g... Input flip-flops, 10a, 10b, 10c, 10d, 10e, 10f. , 11e, 11f, 1
1g: clock distribution circuit, 12a, 12b, 12c, 12d, 12e, 12f, 1
2g ... PLL, 13a, 13b, 13c, 13d, 13e, 13f ... P
LL feedback clock, 14: data wiring, 15a, 15c: PLL reference clock, 16, 16e, 17, 17f: LSI of the present invention, 18c, 18d: PLL feedback clock input terminal, 19c, 19d: PLL feedback clock output terminal, 20c, 20d: PLL feedback clock input buffer, 21c, 21d, g: PLL feedback clock output buffer, 22c, 22d: PLL feedback loop wiring, 23e, 23f: internal delay buffer for data wiring, 24e, 24f, 24g: input Internal delay buffers, 25e, 25f, 25g: internal delay buffers for output, 26: clock output type receiving LSI of the present invention, 27: clock wiring between LSIs, 28g: system clock input terminal, 29g: LSI clock output terminal, 30 ... delay circuit, 31 ... printed circuit Plate, 32, 36 ... printed circuit board connector, 33 ... receiving interface IC, 34 ... transmission interface IC, 35 ... clock PLL 36a, 36b, 36c, 36d ... data processing unit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Taro Donotsuka 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Communication Systems Division, Hitachi, Ltd. (72) Inventor Kokuni Yokota Totsuka-ku, Yokohama 216-cho, Hitachi, Ltd.Communication Systems Division of Hitachi, Ltd. (72) Inventor Katsunori Hirano 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture In-house Research Laboratory of Hitachi, Ltd. 216 Totsuka-cho, Totsuka-ku F-term in Hitachi, Ltd. Communication Systems Division (Reference) 5B079 BA20 BB10 BC03 CC14 DD08 DD13 DD20 5J106 AA04 DD05 DD11 FF07 KK13 KK14 5K047 AA06 AA08 GG03 GG09 GG11 MM36 MM46 MM47

Claims (5)

[Claims] 1. A system clock is input to a PLL, and
A method of connecting a plurality of circuit blocks each including a clock supply circuit for adjusting a phase using L, a clock distribution circuit for distributing a clock of the PLL output through a feedback path from the PLL output to the PLL feedback clock input unit. And P output from the clock distribution circuit.
A PLL feedback clock output buffer for buffering an LL feedback clock, a PLL feedback loop wiring for feeding back the PLL feedback clock, and the PLL feedback clock transmitted through the PLL feedback loop wiring are input to the PLL feedback input unit. A PLL feedback clock input buffer, a data transmission path for processing the data captured by the system clock and outputting the processed data to the next circuit block, and a clock output from the clock distribution circuit for the processed data. A circuit block connection method comprising: a data output buffer that synchronizes with the above and outputs the data to the next-stage circuit block; and a data line that transmits the data to the next-stage circuit block. 2. A method of connecting a semiconductor integrated circuit, wherein one circuit block is constituted by one semiconductor integrated circuit. 3. The method according to claim 2, wherein the PLL feedback loop wiring is set outside the semiconductor integrated circuit. 4. The delay time of the PLL feedback clock input buffer and the delay time of the system clock input buffer of the PLL are set to be the same, and the delay time of the PLL feedback clock output buffer, the delay time of the data output buffer, 4. The method according to claim 1, wherein the delay time of the PLL feedback loop wiring and the delay time of the data wiring are set to be the same. 5. The semiconductor integrated circuit connection method according to claim 1, wherein a delay circuit is inserted in a feedback path to said PLL feedback clock input section.