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NO910014L - Fremgangsmaate for aa unngaa latente feil i et logikknettverk for majoritetsselektering av binaere signaler. - Google Patents

Fremgangsmaate for aa unngaa latente feil i et logikknettverk for majoritetsselektering av binaere signaler.

Info

Publication number
NO910014L
NO910014L NO91910014A NO910014A NO910014L NO 910014 L NO910014 L NO 910014L NO 91910014 A NO91910014 A NO 91910014A NO 910014 A NO910014 A NO 910014A NO 910014 L NO910014 L NO 910014L
Authority
NO
Norway
Prior art keywords
procedure
binary signals
logic network
majority selection
latent errors
Prior art date
Application number
NO91910014A
Other languages
English (en)
Other versions
NO178557B (no
NO178557C (no
NO910014D0 (no
Inventor
Tord Lennart Haulin
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of NO910014L publication Critical patent/NO910014L/no
Publication of NO910014D0 publication Critical patent/NO910014D0/no
Publication of NO178557B publication Critical patent/NO178557B/no
Publication of NO178557C publication Critical patent/NO178557C/no

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/187—Voting techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/23—Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Quality & Reliability (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Hardware Redundancy (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Radio Transmission System (AREA)
  • Small-Scale Networks (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
NO910014A 1989-05-12 1991-01-03 Fremgangsmåte for å unngå latente feil i et logikknettverk for majoritetsselektering av binære signaler NO178557C (no)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE8901723A SE465056B (sv) 1989-05-12 1989-05-12 Foerfarande foer att undvika latenta fel i ett logiknaet foer majoritetsval av binaera signaler
PCT/SE1990/000290 WO1990013869A1 (en) 1989-05-12 1990-05-03 A method for avoiding latent errors in a logic network for majority selection of binary signals

Publications (4)

Publication Number Publication Date
NO910014L true NO910014L (no) 1991-01-03
NO910014D0 NO910014D0 (no) 1991-01-03
NO178557B NO178557B (no) 1996-01-08
NO178557C NO178557C (no) 1996-04-17

Family

ID=20375945

Family Applications (1)

Application Number Title Priority Date Filing Date
NO910014A NO178557C (no) 1989-05-12 1991-01-03 Fremgangsmåte for å unngå latente feil i et logikknettverk for majoritetsselektering av binære signaler

Country Status (15)

Country Link
US (1) US5140594A (no)
EP (1) EP0397632B1 (no)
JP (1) JP2963763B2 (no)
KR (1) KR950005528B1 (no)
AU (1) AU622029B2 (no)
BR (1) BR9006762A (no)
CA (1) CA2032519C (no)
DE (1) DE69010275T2 (no)
DK (1) DK0397632T3 (no)
ES (1) ES2055405T3 (no)
FI (1) FI98571C (no)
IE (1) IE66200B1 (no)
NO (1) NO178557C (no)
SE (1) SE465056B (no)
WO (1) WO1990013869A1 (no)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3229135B2 (ja) * 1994-09-14 2001-11-12 三菱電機株式会社 アナログ／デジタル変換装置
US5568067A (en) * 1995-06-30 1996-10-22 Cyrix Corporation Configurable XNOR/XOR element
TW325608B (en) * 1996-04-17 1998-01-21 Toshiba Co Ltd Timing signal generation circuit and a display device using such a circuit
US5982199A (en) * 1998-01-13 1999-11-09 Advanced Micro Devices, Inc. Faster NAND for microprocessors utilizing unevenly sub-nominal P-channel and N-channel CMOS transistors with reduced overlap capacitance
RU2141130C1 (ru) * 1998-04-20 1999-11-10 Акционерное общество открытого типа "Ракетно-космическая корпорация "Энергия" им.С.П.Королева" Мажоритарное устройство
RU2173876C1 (ru) * 2000-09-11 2001-09-20 Открытое акционерное общество "Ракетно-космическая корпорация "Энергия" им. С.П. Королева" Мажоритарное устройство
RU2174703C1 (ru) * 2000-09-27 2001-10-10 Открытое акционерное общество "Ракетно-космическая корпорация "Энергия" им. С.П. Королева" Мажоритарное устройство (варианты)
RU2208245C2 (ru) * 2001-08-07 2003-07-10 Открытое акционерное общество "Ракетно-космическая корпорация "Энергия" им. С.П.Королева" Устройство выбора сигнала
RU2208246C2 (ru) * 2001-08-07 2003-07-10 Открытое акционерное общество "Ракетно-космическая корпорация "Энергия" им. С.П.Королева" Устройство выбора сигналов
US7363546B2 (en) * 2002-07-31 2008-04-22 Sun Microsystems, Inc. Latent fault detector
US7333099B2 (en) * 2003-01-06 2008-02-19 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit, display device, and electronic apparatus
US7308605B2 (en) * 2004-07-20 2007-12-11 Hewlett-Packard Development Company, L.P. Latent error detection
US7236005B1 (en) * 2005-02-09 2007-06-26 Intel Corporation Majority voter circuit design
KR100728954B1 (ko) * 2005-06-03 2007-06-15 주식회사 하이닉스반도체 디지털 방식의 다수결 판정 회로
RU2342696C1 (ru) * 2007-06-01 2008-12-27 Открытое акционерное общество "Ракетно-космическая корпорация "Энергия" имени С.П. Королева" Способ управления отключением неисправных и/или переводимых в резерв объектов системы и система резервирования замещением для его реализации
RU2395161C2 (ru) * 2008-05-04 2010-07-20 Федеральное государственное унитарное предприятие научно-исследовательский институт "Субмикрон" Мажоритарное устройство
US8739010B2 (en) * 2010-11-19 2014-05-27 Altera Corporation Memory array with redundant bits and memory element voting circuits
RU2618192C1 (ru) * 2016-03-09 2017-05-02 федеральное государственное бюджетное образовательное учреждение высшего образования "Пермский национальный исследовательский политехнический университет" Мажоритарное устройство
WO2018048723A1 (en) 2016-09-09 2018-03-15 The Charles Stark Draper Laboratory, Inc. Methods and systems for achieving trusted fault tolerance of a system of untrusted subsystems

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4375683A (en) * 1980-11-12 1983-03-01 August Systems Fault tolerant computational system and voter circuit
GB2093614B (en) * 1981-02-19 1984-10-17 Plessey Co Ltd Triply redundant microprocessor system
US4355683A (en) * 1981-05-11 1982-10-26 Midland-Ross Corporation System of moisture and temperature conditioning air using a solar pond
US4555721A (en) * 1981-05-19 1985-11-26 International Business Machines Corporation Structure of stacked, complementary MOS field effect transistor circuits
US4468574A (en) * 1982-05-03 1984-08-28 General Electric Company Dual gate CMOS transistor circuits having reduced electrode capacitance
JPS5985153A (ja) * 1982-11-08 1984-05-17 Hitachi Ltd 冗長化制御装置
US4617475A (en) * 1984-03-30 1986-10-14 Trilogy Computer Development Partners, Ltd. Wired logic voting circuit

Also Published As

Publication number Publication date
SE465056B (sv) 1991-07-15
DE69010275D1 (de) 1994-08-04
JP2963763B2 (ja) 1999-10-18
FI98571B (fi) 1997-03-27
DE69010275T2 (de) 1994-10-13
NO178557B (no) 1996-01-08
SE8901723L (no) 1990-11-13
KR920700430A (ko) 1992-02-19
JPH03506089A (ja) 1991-12-26
CA2032519C (en) 2000-07-11
BR9006762A (pt) 1991-08-13
AU622029B2 (en) 1992-03-26
WO1990013869A1 (en) 1990-11-15
EP0397632B1 (en) 1994-06-29
EP0397632A1 (en) 1990-11-14
DK0397632T3 (da) 1994-10-31
NO178557C (no) 1996-04-17
FI910022A0 (fi) 1991-01-02
IE66200B1 (en) 1995-12-13
IE901680L (en) 1990-11-12
SE8901723D0 (sv) 1989-05-12
FI98571C (sv) 1997-07-10
NO910014D0 (no) 1991-01-03
US5140594A (en) 1992-08-18
CA2032519A1 (en) 1990-11-13
AU5674090A (en) 1990-11-29
ES2055405T3 (es) 1994-08-16
KR950005528B1 (ko) 1995-05-25

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