NL8401928A - FIELD EFFECT TRANSISTOR CONSTRUCTED FROM THIN LAYERS. - Google Patents

Description

. * * 4 * -1- VG 3373

Title: Thin-layered cpb-baked field effect transistar

The invention relates to a thin-layered field-effect transistar comprising a supply region, a discharge region and a gate region with conductor attached thereto.

According to the invention, a new type of thin layer field-5 effect transistor is provided, characterized in that the supply area and the discharge area are arranged one above the other and arranged vertically with respect to a substrate, in that an area of deposited semi-gel side material extends between and in contact with the supply region and the discharge region and because the gate region is enclosed to apply an electric field to the semiconductor material region between the supply region and the discharge region, so that electrical conduction is caused therebetween. The field effect transistor according to the invention can be deposited on a substrate consisting of an insulator, a semiconductor material, an insulated metal or an insulated semiconductor material. Thanks to the possibility of sculpting on different substrate types and thanks to the small leakage and operating current, it is possible to form a number of transistors according to the invention, that is to say stacking one above the other.

In a suitable embodiment of the field effect transistor 20 according to the invention, at least a part of the suitable semiconductor materials consists of an amorphous alloy, which contains fluorine, silicon and hydrogen. The following can be noted by way of explanation of this embodiment.

8401928 -2- i * *% t

Silicon is the foundation for the massive crystalline semiconductor industry, and is the material used in virtually all commercial integrated chains currently produced.

When the crystalline semiconductor technology reached a commercial state, it became the foundation of today's huge semiconductor device manufacturing industry.

This was due to the ability of the natural scientist to grow substantially error-free germanium, and in particular silicon crystals, and then change it into additional materials 10 having regions therein having a p and n conductivity. It was accomplished by diffusing parts per million of giving Cn] or receiving (p) stimulation materials into such crystalline material, which were introduced as substitute impurities into the substantially pure crystalline materials to enhance their electrical conductivity and for controlling the p or n conductivity thereof.

The semiconductor manufacturing methods for making p-n junction crystals comprise extremely complicated, time consuming and expensive operations, as well as high processing temperatures.

2Q Such crystalline materials used in transistors and other current controllers are thus produced under very precisely controlled conditions by growing individual single silicon or germanium crystals, and when pn junctions are required by stimulating such and such. -3-

Kellijkiga Crystals with extremely Small and Critical amounts of stimulants. Similar crystal growth methods attractively produce Klein's crystal disks, on which the integrated chains are formed.

In the scale integration of such disks, the small area of the crystal disk limits the overall size of the integrated circuits that can be formed thereon. In applications that require large-scale areas, such as in display technology, the crystal disks cannot be manufactured with the required or desired large areas.

Ge organs are formed at least in part by diffusing p or n stimulants into the substrate. Furthermore, each member is formed between insulating channels, which are diffused into the bottom layer. The packing density The number of members per unit 15 of the surface of the disc surface] is also limited on the silicon discs due to the leakage current in each member and the energy required to operate the members, both of which generate heat, which is undesirable. The silicon discs do not spread heat easily. Also, the leakage current adversely affects the 2C life of the battery or the energy cell in portable applications.

In an MDS circuit, the switching speed is directly related to the gate length, with the shortest length having the highest speed. Diffusion methods, photolithography and other crystalline manufacturing methods limit the shortness at which the gate length can be executed.

Furthermore, the packing density is extremely important since the cell size is exponentially related to the cost of each organ.

A reduction in die size with e.g. a factor of 2, 3G results in a cost reduction on the order of a factor δ.

In summary, crystal silicon transistor and integrated circuit parameters, which are not changeable as desired, require large amounts of material, high processing temperatures, and can only be produced on discs with a relatively small surface area and are expensive and time-consuming in production. Organs based on amorphous silicon can overcome these drawbacks of crystal silicon. Amorphous silicon can be made faster, more easily, at lower temperatures and in larger areas than crystal silicon.

Accordingly, considerable effort has been put into developing methods for easily depositing amorphous semiconductor alloys or foils, each of which may comprise relatively large areas, if desired, limited only by the size of the deposition equipment, and which may be stimulated. for forming p and n materials to form pn junction transistors and members that are better in cost and / or performance than those produced by their crystalline counterparts. For many years this work was essentially unproductive. Films of amorphous silicon or germanium (Group IV] are usually quadruple coordinated and have been found to have micro-cavities, as well as meandering bonds and other errors, which produce a high density of localized states in their energy gap. The presence of a high density of localized states. in the energy gap of semiconductor foils of amorphous silicon, such films could not be successfully stimulated or otherwise modified to shift the fermin level close to the conduction or valence bands, making them unsuitable for making pn junctions for transistors and other current control applications.

In an effort to minimize the aforementioned difficulties related to amorphous silicon and germanium, WESpear and PGLe Comber of the "Carnegie Laboratory of Physics, 30 University of Dundee", in Dundee, Scotland, conducted research on "Substitutional Doping of Amorphous Silicon ”, reported in a paper published in" Solid State Communications ", Vol. 17, pp. 1193 - 1196, 1975, with a view to reducing the localized states in the energy gap in amorphous 35 silicon or germanium so as to approximate it more intrinsically crystalline 8401928 'si -5- silicon af germanium ts, and substitutionally stimulate the amorphous materials with appropriate conventional stimulants, such as Dij, to stimulate crystalline materials to make them extrinsic and p or n gel sideability.

The reduction in localized states was accomplished by a glow discharge deposition of amorphous silicon fibers through which a gas-ignited silane (SiH4) was passed through a reaction tube, in which the gas was decomposed by a high-fre-13 quant glow discharge and deposited on a substrate at an substrate temperature of about 500-600 ° K. C227 - 327 ° C3. The material thus deposited on the substrate was an intrinsically amorphous material consisting of silicon and hydrogen. To produce amorphous material, a gas of hydrogen phosphorus (PH 3 for an n-conductivity or a gas of diborane [02 ^ 3 for a p-conductivity, was pre-mixed with the silane gas and passed through the glow discharge reaction tube under the same operating conditions.

The gaseous concentration of the stimulants used was ”6” 2 * between about 5 x 10 and 10 parts by volume. Thus, the deposited material contained allegedly substituent phosphorus or boron stimulant and was found to be eccentric and of the n-cf p-gel eligibility.

Although not known to these investigators, it has now become known through the work of others that the hydrogen in the silane combines at an optimum temperature with many of the wobbling bond of the silicon during the glow deposition to provide substantial reduce the density of the localized states in the cutting gap in order to make the electronic properties of the amorphous material more similar to the crystalline material.

D.I. Jones, W.E. Spear, P.G. LeComber, S.Li, and R. Martins also worked on preparing a Ge: H from GeH, using similar deposition techniques. The resulting material showed a high density of localized states in its 8401928 * 6 energy gap. Although the material could be stimulated, its effectiveness was significantly reduced from that available with an Si: H. In this work, reported in '' Philosophical Magazine 3. "5 Vol. 39, p. 147 (19793, the authors conclude that due to the high density of slit states, the material obtained "..." is a less attractive material than a-Si for stimulation studies and potential applications. "

The inclusion of hydrogen in the previous silane process 10 t not only has limitations due to the fixed hydrogen to silicon ratio in silane, but different Si: H bonding shapes, which is very important, entail new anti-bonding states, which adversely affect can have consequences in these materials. Therefore, there are basic limitations to reducing the density of localized states in these materials, which states are particularly harmful in terms of effective p-, as well as n-stimulating. The resulting density of states of the silane deposited materials leads to a narrow discharge width, which in turn limits the effectiveness of members whose operation depends on the flow of free carriers. The method of making these materials using only silicon and hydrogen also results in a high density due to surface conditions affecting all of the previous parameters.

After the development of the glow discharge deposition of silicon from silane gas, research was conducted on sputter deposition of amorphous silicon foils in the atmosphere of the argon mixture (necessary for sputter deposition 3 and molecular hydrogen in order to avoid the consequences). to determine such molecular hydrogen on the properties of the deposited amorphous silicon foil. This study indicated that the hydrogen acted as an equalizing agent, bonding to such an extent that the localized states in the energy gap were reduced. states in the energy gap were reduced in cathode sputtering, fibrous was less than achieved by the aforementioned deposition of sianan. The p and n stimulation materials described above were also used in the cathode sputtering processes. to produce p and n stimulated extent rials.

These materials had a lower stimulation efficiency than the materials produced in the glow discharge method. Neither method efficiently produced p-stimulated materials with sufficiently high receiving electrode concentrations to produce commercial p-n junction organs. The n-stimulatis-13 efficiency was below desirable and acceptable commercial levels, and the p-stimulation was particularly undesirable as it increased the number of localized states in the band gap.

Different methods for manufacturing and constructing transistors and members in the form of a thin layer of thin layers 15 have been proposed, the different ones of the transistor being made of different materials with different electrical properties. These thin layered transistors are e.g. proposed using nickel oxide layers of silicon layers, layers of amorphous silicon and layers of amorphous silicon 20 eci of hydrogen formed from Siian, as mentioned above. Various geometric shapes have also been proposed, such as a flat IOS construction.

The known deposition of amorphous silicon, which has been changed by hydrogen from the silane gas, in an attempt to make it more resemble crystalline silicon, and which has been stimulated in the manner of stimulating crystalline silicon, has properties which all important aspects are less than that of stimulated crystalline silicon. As reported by LeComber and Spear et al., As mentioned above, in the transistor members on the 60-second transistor members, the leakage current cannot be more than 10 A, -6 the saturation current appears to be about 5 x 10 A, the 4 switching frequency of the organ is about 10 'Hz and the stability is poor because the material deteriorates with time.

It has been proposed to make a solar cell which is in principle an 8401928 -8 photosensitive rectifier using an amorphous alloy containing silicon and fluorine, as disclosed in the aforementioned U.S. Pat. Nos. 4,217,374 and 4,276,898.

In accordance with a suitable embodiment of the invention, a field-effect transistor, or built of thin layers, is provided, comprising a source region, a drain region, a gate insulator and a thin-layered amorphous alloy containing at least silicon and fluorine and coupled with the source region, the drain region and the gate insulator, and a gate electrode in contact with the gate-10 insulator.

The amorphous alloy preferably also contains hydrogen, such as an amorphous alloy Si: F.: H, wherein a is between 80 and 98 atomic% & & abc, b is between 1 and 10 atomic% and c is between 1 and 10 atomic% %.

The thin layer field effect transistor may have various desirable properties depending on the particular thickness selected of the thin layers of the selected amorphous silicon / fluorine material, such as e.g. a saturation DC current of not more than 10 A to -4 to or more than 10 A, an upper cutoff frequency of at least more than 10 MHz, a high ratio of about 10 ^ from the resistor in the off state to the resistor in the on state, - 11 and a very low leakage current of about 10 A or less. Furthermore, the alloy does not deteriorate over time.

8401928 .1 * -s- • The invention is further elucidated on the basis of the drawing, in which:

Fig. 1 is a vertical sectional view of an embodiment having metal source and drain regions, similar to a planar ilOS transistor;

Fig. 2 is a circuit diagram of the transistor shown in Fig. 1;

Fig. 3 is a vertical sectional view of a second embodiment having half slider source and drain regions; FIG. 4 is a circuit diagram of the transistor shown in FIG. 3;

Fig. 5 is a vertical sectional view of another embodiment, having metal source and drain regions similar to a V-MCS transistor; Fig. S is a circuit diagram of the transistor shown in Fig. 5,

Fig. 7 is a vertical sectional view of an embodiment similar to the transistor shown in FIG. 5, having semiconductor source and drain regions; FIG. 3 is a circuit diagram of the transistor shown in FIG. 7; and

Fig. 9 is a vertical sectional view of one shown in FIG.

1-3 shown in transistors are similar transistors, however, with an 8401928-10- other geometric construction.

Referring now in more detail to the drawing, FIG. 1 shows a field film transistor 10 in the form of a thin film. As shown, transistor 10 is formed on a bottom layer 12 of insulating material, which may consist of a silicon material, a layer of polymer material, or an insulator on top of a metal. According to the present teachings, a thin alloy layer 14 is deposited on the bottom layer 12, which contains silicon and fluorine, and which can also contain hydrogen, which layer can be stimulated to form an IM or P alloy. On top of this blank ring layer 14 is a layer or tape 16 of insulating material, such as a field oxide, and spaced therebetween is another layer or tape 18 of insulating material, such as a field oxide.

A channel or aperture 20 is biv, formed between the two bands 16 and 18 by conventional photo-15 lithographic techniques.

A source metal conductor 22 is deposited over the belt 16, a portion of which is in contact with the alloy layer 14 to form a scrap resistance contact at the interface between the source metal 22 and the amorphous alloy layer 14.

In a similar manner, a drain metal conductor or layer 24 is deposited over the insulating tape 18, a portion of which is in contact with the alloy layer 14 spaced from the source metal 22. The interface between the drain metal 24 and the amorphous layer 14 provides another scrap metal contact. A gate-25 insulator layer 26 of insulating material, such as a gate oxide or gate nitride 26, is deposited over the source metal 22 and the drain metal 24 and contacts the amorphous alloy layer 14 between the source and drain metal. A gate conductor 28, which may be made of any suitable metal, such as aluminum or molybdenum, is deposited on this layer 26 of gate insulating material. A further layer 30 of insulating material is deposited on the gate conductor to render the member passive, which material is referred to as a field oxide.

The insulating layers 16 and 30 are connected prior to the next adjacent transistor, the source 22 being connected to an external conductor by 8401928 5% -11. The insulating layer IS forms the insulator for the next member, similar to the insulator 18 of the illustrated transistor 10.

The gate insulator layer 25 and the tapes 15 and IS of insulating material, referred to as a field oxide, may be made of a metal oxide, silicon dioxide, or other insulator, such as silicon nitride. The source metal 22 and drain metal 24 may be formed of any suitable conductive metal, such as aluminum, molybdenum or a high activity metal, such as gold, pal-10 ladium, platinum or chromium. The gate insulator can be a nitride, silicon dioxide or silicon nitride material.

According to the present teachings, an alloy containing silicon and fluorine, which may also contain hydrogen, is used to form the amorphous alloy layer 14. This alloy provides the aforementioned desirable properties, which can be used for many different chains . The alloy layer 14 is preferably made of a-Si: F.: H, wherein a is between 80 and abc 98 atom%, b between 1 and 10 atom% and c between 1 and 10 atom%.

The alloy can be stimulated with a stimulant from Group V or Group III of the Periodic System in an amount of between 10 and 1000 parts per million Cdpml.

CE stimulation materials and the degree of stimulation can be different.

The thickness of the alloy layer 14 of amorphous material can be between 100 and 500 nm, the thickness used being about 100 nm. The source metal 22 and the drain metal 24 may also have thicknesses between 50 and 2000 nm, with an applied thickness being about 200 nm. Although, according to the description, the port-30 conductor 23 is made of metal, it can be made, if desired, of a stimulated semiconductor material.

Depending on the geometry of the different layers and the thicknesses of the different layers, a transistor multi-field operation can be constructed in the manner described above, where the leakage current is about 10 ^ A to provide 8401928 4 w -12 - of a high resistance when switched off and a saturation DC current of about 10 A.

When constructing the thin film field-effect transistor 10 shown in FIG. 1, the material layers, and in particular the alloy layer 14, are deposited by various deposition techniques, preferably by glow discharge.

A typical gate CG3, source CS) and drain CD) circuit diagram of the field-effect transistor 10 is shown in Figure 2.

Referring now to FIG. 3, a planar constructed thin film field transistor 40 is shown, which like transistor 10 is formed on an insulated bottom layer 42. On top of the bottom layer material 42, e.g. An alloy layer 44, which contains silicon and fluorine and preferably also hydrogen, is deposited by glow discharge and may be of the N or P type. Two layers of insulating material 48 and 48 are made on this alloy layer 44, which are made of a field oxide and according to Fig. 3 with an opening 50 between them. Above the insulating layers 46 and 48, resp. a source alloy layer 52 and a drain alloy layer 54, which also contain: silicon and fluorine and preferably also hydrogen. The source 52 and the drain ring 54 are amorphous N or P alloys. An N-P or P-N junction is then formed at the interface where layers 52 and 54 contact alloy layer 44.

After depositing layers 52 and 54, a gate insulator layer 56, referred to as a gate oxide 56, is deposited over the source region 52, the exposed portion of the amorphous layer 44 and the drain region 54. Then, a gate conductor 58 is deposited over the gate insulator 46, and a passivating insulating layer 6G is deposited on top of the gate conductor 58, which layer consists of a field oxide.

A typical gate (G), source (S) and drain CD) circuit diagram of transistor 40 is shown in Figure 4.

The difference between transistor 40 and transistor 10 is that the drain and source regions or conductors 52 and 54 of transistor 40 are made of a semiconductor material and preferably 8401928 -13- of a ~ 3i: F: H alloy.

Fig. 5 shows a new V-MOS construct depicted as a field film transistor 70 in the form of thin films manufactured in accordance with the present teaching. On a backsheet 72, a layer or band of drain metal 74 is first deposited where a center portion is cut or etched. On top of the drain metal 74, a thin layer of amorphous alloy tape 76 is deposited, in which a center portion is cut or etched in line with the cut portion of the layer 74. Similarly, a layer of source metal 78 is deposited on the layer 76 and a corresponding center portion thereof is cut away. Also, all layers can be etched in one step following the deposition of those layers.

Also, a part insulator 30, referred to as a gate oxide, is deposited over the source metal 73 and in the resulting center space 82 in the form of a V-cut and on the beveled edges of the layer portions 74, 76 and 73 and over the exposed underlayer 72. Next, a gate conductor 84 is deposited on the gate insulator 82, and a layer 86 of insulating material, referred to as a field oxide, is deposited over the gate metal conductor 84 as a passivating layer.

This particular V-MQS construction with the open space 80 has the advantage that a very short distance L is established between the source metal 74 and the drain metal 79 through the alloy layer 76. The layer thickness or distance L has a resulting in a high operating frequency and a higher saturation current than the transistor-shape of FIGS. 1 and 3. The leakage current may increase with respect to the form of FIGS. 1 and 3.

A typical gate CG), source CS1, and drain (0) circuit diagram of transistor 70 is shown in Figure 5.

In FIG. 7, another V-flQS transistor 90 having a thin film field action, divided on a bottom layer 92, the alloy layers 94, 96 and 98 with silicon and fluorine (N or P type) ] are coated on the bottom layer 92. The respective layers 94, 96 and 98 have a cut-away or etched center portion 100. Then, a gate insulator 102, referred to as a gate oxide, is deposited over the edge of the layer 98 and in contact with the exposed edges of the layers 94, 96 and 9S, as well as the exposed portion of the bottom layer 92, as shown, a gate conductor 104 is deposited over the insulating layer 102, finally forming a layer 106 of insulating material, such as a field oxide, is deposited over gate conductor 104. Transistor 90 operates using oppositely biased PN junctions formed between layers 94 and 96 and between 96 and 93.

Transistor 90 is similar to transistor 70, as shown in Figure 5, except that the source region 93 and drain 10 region 94 are made of a semiconductor alloy, such as α-Si: F: H.

The V-MOS construction of transistors 70 and 90 is advantageously used with any semiconductor deposited material, such as e.g. but not exclusively a silicon alloy containing at least silane-deposited hydrogen.

A typical circuit diagram of transistor 90 is shown in Figure 8.

Referring now to Figure 9, another field-effect transistor 110 is made in accordance with the present teaching.

The transistor 110 is formed on a metal substrate 111 on which a thin layer of insulating material 112 is deposited, which separates the active components of the transistor 110 from the metal substrate 111 and yet is sufficiently thin that the heat generated in the transistor 110 is the metal substrate can flow, which forms a heat accumulator for this.

The thin film field operation transistor 110 is formed by depositing a source conductor layer 114 made of metal or an N or P semiconductor alloy. A drain conductor 118 is deposited on the insulating layer 112 and is also made of a metal or a PN semiconductor alloy. On top of the conductors 114 and 116, an intrinsic or slightly stimulated alloy layer 118 is deposited, such as the a-Si: F already described. : H alloy.

On top of the alloy layer 118 is deposited a gate insulator 120, which may consist of a silicon oxide or a silicon nitride.

A gate conductor layer 122 is deposited on top of the gate insulator 120, which may consist of a metal or semiconductor material. A passivating layer 124 is deposited over the gate conductor 122.

The different transistors 10, 40, 70, 30 and 110 may be formed in a matrix, so that the source region or drain region extends as a Y axis conductor across the deposited under layer 112. Then, the drain or source region deposited to mix a separate drain or source area, which is then connected to an X axis guide. The gate electrode is set so that it extends parallel to the Y axis to form a Y axis conductor. In this manner, the transistors 10, 50, 70, 30, and 110 can be field-operated in conjunction with PROM members to form the isolator in a memory circuit therefor, which circuit includes a memory region and the isolator.

The present field film transistor in the form of thin films and the various embodiments thereof, as described, provide a transistor which is very small and yet has very good operating properties, as mentioned above. The top insulating layer of the transistors, such as 124 in Fig. 9, can be used to form the insulating layer for another transistor to be formed thereon to provide a stacked transistor shape, and thus further increase the packing density of the members. This is possible because the layers have been deposited and due to the low operating and leakage current of the organs.

It is clear from the foregoing description that a thin film field-effect transistor comprising a leg ring layer of a-Si: F: H according to the present teachings has a number of lead parts,

The planar structures of FIGS. 1, 3, and 9 may also be warped in reverse order from that shown with the gate at the bottom. Ce scraps can also be a MIS (metal insulator semiconductor) contact. The gate conductor in an organ may also consist of metal, polysilicon or stimulated semiconductor material with a different metal or semiconductor drain material, instead of both being made of the same metal or semiconductor material.

8401928

Claims (14)

Thin-layered field-effect transistor, comprising a supply region, a discharge region and a gate region with conductor attached thereto, characterized in that the supply region (78, 98) and the discharge region (74, 94) are arranged one above the other and vertically arranged with respect to a substrate (72, 92) jb) that a region (76, 96) of deposited semiconductor material extends between and in contact with the supply region (78, 98) and the discharge region (74, 94), and ) the gate region (80, 84, 102, 104) is arranged to apply an electric field to the semiconductor material region (76, 96) between the supply region (78, 98) and the discharge region (74, 94) so that electrical conduction is caused between them. Thin layer field effect transistor according to Claim 1, characterized in that the deposited semiconductor material (76, 96) is an n-type semiconductor material. Thin layer field effect transistor according to Claims 1-2, characterized in that the deposited semiconductor material (76, 96) is an amorphous fegation. Thin layer field effect transistor according to Claim 3, characterized in that the alloy is an amorphous semiconductor material having at least one of the density-reducing element in the form of fluorine. Thin layer field-effect transistor according to Claims 3-4, characterized in that the alloy contains silicon and hydrogen. Thin layer field effect transistor according to Claims 3-5, characterized in that the alloy contains silicon, fluorine and hydrogen and can be represented by the empirical formula Si ^:: H, wherein a 80 to 98 atom%, b 1 to 10 atom% and c represents 1 to 10 atom%. Thin layer field effect transistor according to Claims 1-6, characterized in that the drain region (94) is a p-type semiconductor. Thin layer field effect transistor according to Claims 1-6, characterized in that the drain region (74,94) consists of a material 8401928 -17- selected from metals and / or amorphous Isgeringsn. Thin layer field effect transistor according to Claims 1-3, characterized in that the supply region C333 is a p-type semiconductor Thin layer field effect transistor according to claims 1-9, characterized in that the supply region (73, 98) consists of a material selected from metal an / or amorphous alloys. Thin layer field effect transistor according to Claims 1 to 10, characterized in that the deposited semi-layer material C7S, 38) has a thickness O of 100 to 5000 Augstrom. Thin layer field effect transistor according to Claims 1-11, characterized in that the drain region C74, 94) has a thickness of O 500 - 2Q.C00 Augstrom. Thin layer field effect transistor according to Claims 1-12, characterized in that the supply region (78, 98) has a thickness of 0 500 - 20,000 Augstrom. Thin layer field effect transistor according to Claims 1 to 13, characterized in that the device is provided with a gate insulating layer C80-, 102), which consists of oxide. 8401928