Kawa et al., 2006 - Google Patents
EDA challenges in nano-scale technologyKawa et al., 2006
- Document ID
- 2705545650381672905
- Author
- Kawa J
- Chiang C
- Camposano R
- Publication year
- Publication venue
- IEEE Custom Integrated Circuits Conference 2006
External Links
Snippet
Since the onset of the 90 nm node the challenges associated with further transistor scaling while maintaining a consistently functional, reliable, and yielding design have increased substantially. While those challenges carry across the spectrum of the manufacturing, the …
- 238000005516 engineering process 0 title description 15
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5072—Floorplanning, e.g. partitioning, placement
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Exposure apparatus for microlithography
- G03F7/70483—Information management, control, testing, and wafer monitoring, e.g. pattern monitoring
- G03F7/70491—Information management and control, including software
- G03F7/705—Modelling and simulation from physical phenomena up to complete wafer process or whole workflow in wafer fabrication
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/14—Originals characterised by structural details, e.g. supports, cover layers, pellicle rings
- G03F1/144—Auxiliary patterns; Corrected patterns, e.g. proximity correction, grey level masks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/12—Design for manufacturability
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Exposure apparatus for microlithography
- G03F7/70425—Imaging strategies, e.g. for increasing throughput, printing product fields larger than the image field, compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching, double patterning
- G03F7/70433—Layout for increasing efficiency, for compensating imaging errors, e.g. layout of exposure fields,; Use of mask features for increasing efficiency, for compensating imaging errors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Chiang et al. | Design for manufacturability and yield for nano-scale CMOS | |
| Jhaveri et al. | Co-optimization of circuits, layout and lithography for predictive technology scaling beyond gratings | |
| Wang et al. | Standard cell layout with regular contact placement | |
| Cao | Design for manufacturing (DFM) in submicron VLSI design | |
| US8161421B2 (en) | Calibration and verification structures for use in optical proximity correction | |
| US20080162103A1 (en) | Method, system, and computer program product for concurrent model aided electronic design automation | |
| KR102442273B1 (en) | Tie off device | |
| Dutton et al. | Perspectives on technology and technology-driven CAD | |
| US8024675B1 (en) | Method and system for wafer topography-aware integrated circuit design analysis and optimization | |
| Choi et al. | Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing | |
| Kawa et al. | EDA challenges in nano-scale technology | |
| Pan et al. | Design for manufacturing meets advanced process control: A survey | |
| Gupta et al. | Wafer topography-aware optical proximity correction | |
| US20100162188A1 (en) | Method and system performing block-level rc extraction | |
| Shauly | Design Rules in a Semiconductor Foundry | |
| Gupta et al. | Timing yield-aware color reassignment and detailed placement perturbation for bimodal CD distribution in double patterning lithography | |
| Kahng | Key directions and a roadmap for electrical design for manufacturability | |
| Jeong et al. | Assessing chip-level impact of double patterning lithography | |
| Pan et al. | Manufacturability aware routing in nanometer VLSI | |
| Sole | Layout regularity for design and manufacturability | |
| Chiang et al. | Three DFM challenges: Random defects, thickness variation, and printability variation | |
| Orshansky | Increasing circuit performance through statistical design techniques | |
| Cheng | A glance of technology efforts for design-for-manufacturing in nano-scale CMOS processes | |
| Poppe et al. | Platform for collaborative DFM | |
| You et al. | Impacts of optical proximity correction settings on electrical performances |