Jamal et al., 2015 - Google Patents
Analysis of test sequence generators for built-in self-test implementationJamal et al., 2015
- Document ID
- 18263902191379655791
- Author
- Jamal K
- Srihari P
- Publication year
- Publication venue
- 2015 International Conference on Advanced Computing and Communication Systems
External Links
Snippet
The technique of Test Sequence Generation (TSG) plays a key role in Built-In Self-Test (BIST) architecture implementation. Major problem with any test sequence generator is to produce long, unpredictable key sequences which can be applied to Circuit Under Test …
- 238000004458 analytical method 0 title abstract description 10
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
- G01R31/318385—Random or pseudo-random test pattern
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/582—Pseudo-random number generators
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20190012146A1 (en) | Self-timed random number generator | |
Jamal et al. | Analysis of test sequence generators for built-in self-test implementation | |
Jamal et al. | Test pattern generation using thermometer code counter in TPC technique for BIST implementation | |
Cerda et al. | An efficient FPGA random number generator using LFSRs and cellular automata | |
JP5165755B2 (en) | Cryptographic random number generator using finite field operations | |
Hussain et al. | BIST-PUF: Online, hardware-based evaluation of physically unclonable circuit identifiers | |
Babu et al. | Modified dynamic current mode logic based LFSR for low power applications | |
kumar Singh et al. | Design of LFSR circuit based on high performance XOR gate | |
Teo et al. | Hardware implementation of multi-lfsr pseudo random number generator | |
Devrari et al. | Reconfigurable linear feedback shift register for wireless communication and coding | |
Kumar et al. | Low power LFSR for BIST applications | |
Kirthi et al. | Design of BIST with low power test pattern generator | |
Mohan et al. | Low transition dual LFSR for low power testing | |
Sony et al. | Design and analysis of multi-bit linear feedback shift register based prng with fpga implementation using different primitive polynomials | |
Thirunavukkarasu et al. | Performance of low power BIST architecture for UART | |
Rajski et al. | A nonlinear stream cipher for encryption of test patterns in streaming scan networks | |
Voyiatzis et al. | On the generation of SIC pairs in optimal time | |
Madghuri | Hybrid Cellular Automata-Based Pseudo Random Sequence Generator for BIST Implementation | |
Dogaru et al. | Algebraic normal form for rapid prototyping of elementary hybrid cellular automata in FPGA | |
Sekhar et al. | An Efficient Pseudo Random Number Generator for Cryptographic Applications | |
Alawey | A Mixture between Rule 90 and Rule 150 Cellular Automata as a Test Pattern Generator | |
Nivita et al. | A BIST Circuit for Fault Detection Using Recursive Pseudo-Exhaustive Two Pattern Generator | |
Yoo et al. | A robust and practical random number generator | |
Naghwal et al. | A PN Sequence Generator using LFSR with Dual Edge Trigger Technique | |
Jagtap et al. | Techniques for minimizing area and power in test pattern generation |