Trummer et al., 2009 - Google Patents
Simulation-based verification of power aware System-on-Chip designs using UPF IEEE 1801Trummer et al., 2009
- Document ID
- 11973450964545807402
- Author
- Trummer C
- Kirchsteiger C
- Steger C
- Weiß R
- Dalton D
- Pistauer M
- Publication year
- Publication venue
- 2009 NORCHIP
External Links
Snippet
For System-on-Chips (SoCs) the most critical design constraint is power dissipation. Therefore, power aware design should be introduced at early stages of SoC design where it has the highest benefits for power reduction. This also lowers the design complexity and …
- 238000004088 simulation 0 title abstract description 17
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/504—Formal methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/86—Hardware-Software co-design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/68—Processors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. varying supply voltage
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7958475B2 (en) | Synthesis of assertions from statements of power intent | |
TWI528199B (en) | System and method for automatic extraction of power intent from custom analog/custom digital/mixed signal schematic designs | |
US8732636B2 (en) | Method, system, and computer program product for implementing multi-power domain digital / mixed-signal verification and low power simulation | |
US9703921B1 (en) | Naturally connecting mixed-signal power networks in mixed-signal simulations | |
USRE44479E1 (en) | Method and mechanism for implementing electronic designs having power information specifications background | |
US7596769B2 (en) | Simulation of power domain isolation | |
CN102314525B (en) | Low-power-consumption circuit design optimization method | |
US8234617B2 (en) | Method and system for re-using digital assertions in a mixed signal design | |
US9058440B1 (en) | Method and mechanism for verifying and simulating power aware mixed-signal electronic designs | |
Hazra et al. | Formal verification of architectural power intent | |
US8255859B2 (en) | Method and system for verification of multi-voltage circuit design | |
Trummer et al. | Simulation-based verification of power aware System-on-Chip designs using UPF IEEE 1801 | |
Macko et al. | Simplifying low-power SoC top-down design using the system-level abstraction and the increased automation | |
US10162917B1 (en) | Method and system for implementing selective transformation for low power verification | |
Gagarski et al. | Power specification, simulation and verification of SystemC designs | |
Macko et al. | Power-management high-level synthesis | |
Peterson et al. | Fully-automated Synthesis of Power Management controllers from UPF | |
Chickermane et al. | A power-aware test methodology for multi-supply multi-voltage designs | |
Carver et al. | Low-power design using the Si2 common power format | |
Hsu et al. | Speeding up power verification by merging equivalent power domains in RTL design with UPF | |
Harinarayan et al. | Automated Full Chip SPICE simulations with self-checking assertions for last mile verification & first pass Silicon of mixed signal SoCs | |
Sinha et al. | Advancetechnique to accompolish power aware cdc verification | |
Bhargava et al. | Low-power verification methodology using upf query functions and bind checkers | |
Mischkalla et al. | Efficient power intent validation using loosely-timed simulation models | |
Vyagrheswarudu et al. | PowerAdviser: An RTL power platform for interactive sequential optimizations |