RISC-V: instruction cache returns references
- closes RV-219
What
Return Option<&InstrCacheable> from the instruction cache, instead of Option<InstrCacheable>.
Why
This avoids copying the instruction bytes unnecessarily, resulting in a performance gain.
How
RISC-V: split instruction-cache from runnable m... (!15005 - merged) separated the instruction cache out from the rest of the 'runnable state' (ie parts of the state required to run cacheable instructions).
As a result, we can now safely return references from the instruction cache without rustc complaining.
Manually Testing
make -C src/riscv all
Benchmarking
master |
This MR | Improvement | |
|---|---|---|---|
| AMD Ryzen 7 7840U | 0.370 TPS (1/810 native) | 0.440 TPS (1/682 native) | +18.9% |
| Benchmark Machine | 0.189 TPS (1/799 native) | 0.221 TPS (1/683 native) | +16.9% |
Tasks for the Author
-
Link all Linear issues related to this MR using magic words (e.g. part of, relates to, closes). -
Eliminate dead code and other spurious artefacts introduced in your changes. -
Document new public functions, methods and types. -
Make sure the documentation for updated functions, methods, and types is correct. -
Add tests for bugs that have been fixed. -
Put in reasonable effort to ensure that CI will pass. -
Benchmark performance and populate the table above if needed. -
Write commit messages to reflect the changes they're about. -
Self-review your changes to ensure they are high-quality. -
Complete all of the above before assigning this MR to reviewers.
/assign @ole.kruger
/assign @victor-dumitrescu
/assign @felix.puscasu1
/assign @anastasia.courtney
/assign @emturner
/assign_reviewer @ole.kruger
/assign_reviewer @victor-dumitrescu
/assign_reviewer @felix.puscasu1
/assign_reviewer @anastasia.courtney
/assign_reviewer @emturner
/unassign me
/unassign_reviewer me
/ready
Edited by Emma Turner