RISC-V: split instruction-cache from runnable machine state

• closes RV-178
• part of RV-219

What

Split instruction cache apart from the state required to run 'cacheable' instructions. (ie. instructions that do not invalidate the instruction cache when run).

Why

This will allow us to return references from the instruction cache (see RISC-V: instruction cache returns references (!15008 - merged)), which gives a large performance gain.

Manually Testing

make -C src/riscv all

Benchmarking

This MR was measured on the benchmark machine; no change to performance was observed.

Tasks for the Author

• Link all Linear issues related to this MR using magic words (e.g. part of, relates to, closes).
• Eliminate dead code and other spurious artefacts introduced in your changes.
• Document new public functions, methods and types.
• Make sure the documentation for updated functions, methods, and types is correct.
• Add tests for bugs that have been fixed.
• Put in reasonable effort to ensure that CI will pass.
• Benchmark performance and populate the table above if needed.
• Write commit messages to reflect the changes they're about.
• Self-review your changes to ensure they are high-quality.
• Complete all of the above before assigning this MR to reviewers.

/assign @ole.kruger
/assign @victor-dumitrescu
/assign @felix.puscasu1
/assign @anastasia.courtney
/assign @emturner

/assign_reviewer @ole.kruger
/assign_reviewer @victor-dumitrescu
/assign_reviewer @felix.puscasu1
/assign_reviewer @anastasia.courtney
/assign_reviewer @emturner

/unassign me
/unassign_reviewer me

/ready