Branches

• feature_add_div

  76d91a1d · simulation shows divide instruction working; need to convert make_0 to make(); · Jun 20, 2020
• feat_clkgen

  07ab6ae0 · CLKGEN created; simulation running with generated clocks · Jun 21, 2020
• 2020-0621-clock_consolidation

  fccbbb66 · main FSM running off clk_cpu now; still some stuff warned as inferred latches; · Jun 21, 2020
• 2020-0621-regfile

  9c09bd9a · regfile works; many but not all instructions tested; fails timing; need to fix poor FSM model; · Jun 23, 2020
• 2020-0627-multdiv

  caf9a41e · got mul and div working; added many other instructions; runs great in simulation now · Jul 03, 2020
• 200710-timing-2

  ddf03d53 · meets timing at 48 MHz · Jul 11, 2020
• 200711-fixio

  f982c3ba · fixed the io/strobe issue; changed to 64Mhz and timing passes; added some basic IO constraints · Jul 12, 2020
• 200712-rs232

  4de7d68c · working TX UART at 115200 bps · Jul 19, 2020
• 200930-threadui

  25f31e61 · didn't get threaded to work, but other UI and instructions coded. LIFE works.... · Oct 23, 2020
• master default protected

  746d92ef · started RX code in VM · Oct 26, 2020