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feature_add_div
76d91a1d
·
simulation shows divide instruction working; need to convert make_0 to make();
·
Jun 20, 2020
feat_clkgen
07ab6ae0
·
CLKGEN created; simulation running with generated clocks
·
Jun 21, 2020
2020-0621-clock_consolidation
fccbbb66
·
main FSM running off clk_cpu now; still some stuff warned as inferred latches;
·
Jun 21, 2020
2020-0621-regfile
9c09bd9a
·
regfile works; many but not all instructions tested; fails timing; need to fix poor FSM model;
·
Jun 23, 2020
2020-0627-multdiv
caf9a41e
·
got mul and div working; added many other instructions; runs great in simulation now
·
Jul 03, 2020
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