Activity for marcel hendrix
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marcel hendrix posted a comment on discussion Open Discussion
This would mean that the delay control input should be inhibited until T = T_present + T_delay(new) ? That should be easy to do (but complex to predict what its effect will be).
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The IPC additions make debugging really difficult with all these alternative code paths. I didn't use it when I needed something like this because it was unclear what IPC/ATESSE does exactly and how it should be used. The proper thing to do to appease dusty deck users might be to conditionally compile the code and announce that it will be removed in future releases. IIRC, removing the code is not really simple as it hooks into details of the time stepper.
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OK. It looks to me that hybrids are supposed to do something with g_mif_info.breakpoint.current as soon as they know that the analog timestep is final. That could be difficult. The hybrid codes can't simply wait until EVTcall_hybrids() happens, because what they want to do next might depend on what other hybrids are going to do with breakpoint.current and there would be a deadlock. If the closest breakpoint simply wins, it could be that the state of the all the loosing hybrids must be recomputed....
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... as hybrid (analog+digital) device instances already get a look at the solution just before it is committed ... Please expand a bit on this?
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Who do you want to embrace this standard? I am sure end-users will love it, but they won't engage in defining and standardizing the interface(s). For simulator dev teams it is easy to give input (e.g for NGSPICE it's exactly the XSPICE interface) but getting all these interfaces aligned will be an unappetizing political, not a technical, battle. However, I know from personal experience that it would be very beneficial for non-SPICE tools to integrate/define a SPICE component. For instance, microcontroller...
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Who do you want to embrace this standard? I am sure end-users will love it, but they won't engage in defining and standardizing the interface(s). For simulator dev teams it is easy to give input (e.g for NGSPICE it's exactly the XSPICE interface) but getting all these interfaces aligned will be a unappetizing political, not a technical battle. However, I know from personal experience that it would be very beneficial for non-SPICE tools to integrate/define a SPICE component. For instance, microcontroller...
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Coupling factor (wrongly) required to be positive
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Here you have two (intended to be behavioral) current sources Vx2 and Vx3 (better call them Bi1 and Bi2), with the same node label X1. Do you really want to put them in parallel? Also, I wouldn't give a node the name of a possible device. Again, please supply a netlist.
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controlled delay If a signal is delayed by 0s, but at t=1s it is ordered to be delayed by 100ms, there is a gap of 100ms between 1s and 1.1s where the signal is 0. What happens then if at t=1.05s the delay is changed to 10ms? How is 'controlled delay' mathematically defined?
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Check the manual '13.5.38 Gnuplot: Graphics output via gnuplot'. If you are on Windows (looks like it) you will have to properly install Gnuplot. Maybe '13.5.39 Hardcopy: Save a plot to a file for printing' is easier.
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The vcvs and ccvs are very efficient (i.e. fast) basic devices that can be solved in a single timestep. Adding limits to them removes their best features. Why not add limits to a behavioral source, or use a table source?
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PEEC is nice if better models are needed. As a stepup to it I can recommend https://westy31.nl/Electric.html . I did not yet have time to actually try out any of those ideas. With respect to speed: Fettweis' Digital Wave Filter framework is very interesting, as it allows to get rid of NR and works with a constant stepsize. However, when accurate device models are needed iteration creeps in again. Maybe it could be combined with piecewise linear modeling (quite heavy mathematics again). A disadvantage...
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I am not sure where the speed up comes from ... I don't think this is (only) caused by ngspice being faster (although it is). My experience with LTspice says that it becomes unexplicably slow when one starts using more than a few B-sources, and/or when the netlist becomes larger than a typical circuit. For instance, the largest files in the MCNC benchmark (smult20, chip2, voter, etc.) are very, very, slow or don't even finish (ram2k).
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I find it odd that there is trouble with .spiceinit as I believe it is what has been used for many years, True. and I never had a problem with it when using Windows. (But that is rare.) I have had many problems with it on Windows. The way it works is very unixy, and I found it difficult to figure out from the source / build /install process where the .rc and .init files will be / should be, and which one of them is used when there are multiple copies in different locations (multiple copies are needed...
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manual 13.5.57 Pre_: execute commands prior to parsing the circuit Try pre_set ngbehavior=ltps
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All calculated points are within the tolerance checks. The result doesn't look nice, but that might be acceptable depending on what you want to do with the results. For instance, if you know that the result is a sine-wave, two points per cycle tell you everything. The interpolate() function (Chapter 13, page 368) helps to fill in the blanks. On the other hand, if you don't know how the result is supposed to look, reduce TSTEPMAX.
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I did check the manual, but I now see it is ngspice-43plus, not ngspice-44, sorry. It says (p359): add .functions limit, pwr, pwrs, stp, if, int I did not see if there because it is impractical to search for. Marcel is 98% human, I know some people who think that quite generous. I scanned #780 The user did a lot of work to document his problem and outline a possible solution that would work for him. It appears to me he simply does not know ngspice has a ? b : c. Definitely not one of these new-fangled...
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There are several ways to look at this. If IF() were available by default, confusion can arise with the 'If' parameter of built-in models (when writing IF (a,b,c) instead of IF(a,b,c)). Concretely, the user appears not to consider this a bug and would be happy with an answer to his second question: If so, is there a way to enable if() support in other modes? Or are there any recommended alternatives to achieve similar functionality? When I started using Intusoft SPICE around 1985, I found its C-like...
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That is exactly what I meant. I have it at the top of all my libraries.
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There are several ways to look at this. If IF() were available by default, confusion can arise with the 'If' parameter of built-in models. Concretely, the user appears not to consider this a bug and would be happy with an answer to his second question: If so, is there a way to enable if() support in other modes? Or are there any recommended alternatives to achieve similar functionality? When I started using Intusoft SPICE around 1985, I found its C-like "... ? ... : ... " syntax confusing and cryptic...
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According to a respectable on-line detector, your post is 100% AI-generated.
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What is your definition of non-determinism?
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How exactly do you define 'non-deterministic'? My definition: "Repeatedly running (on the same hardware) a program binary with a given input does not produce exactly the same binary results." Comparing the output of different versions of a deterministic program with a defined input can have many reasons. The netlist used in a test to show non-determinism is not very helpful.
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Hi Giles - where do we find the spider codemodel?
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Manual: "auto_bridge When set to zero, automatic insertion of bridging devices (8.6) is disabled." Maybe the d_source model is helpful, or just use a properly adjusted explicit adc_bridge / dac_bridge.
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Why not use the limit or climit codemodels? Chapt. 8.2.5 and 8.2.6, page 188 in the ngspice 44 manual. Alternatively, use the tanh function inside a behavioral source.
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That means that regular ngspice users will see different results from their dusty decks (unless the defaults are switched according to compatibility setting). In my opinion the occasional discrepancy between ngspice and LTspice is much more insightful than similar results would be.
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My previous interpretation is wrong. The circuit works in resonant mode and doesn't obey the CCM formulas. A sawtooth inductor current is expected. As shown below, with an inductor of 10uH a voltage of 3.3kV is possible, using the VDMOS model. (I don't have an explanation why the parallel diode doesn't break down at this point.)
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The circuit works in resonant mode and doesn't obey the formulas for continuous mode. With an inductor of 10uH a voltage of 3.3kV is possible, using the VDMOS model. (I don't have an explanation why the parallel diode doesn't break down at this point.)
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Unfortunately, these parameters don't solve the problem, see the plot. (Using ngspice-44.) Using .model IM VDMOS Kp=1 Vto=5 Rd=10m Rs=10m + is=1e-399 cjo=0.01f bv=200000 ibv=1e-399 rb=100e6 also did not work -- the plot stays almost the same. As making BV = 200 also does not make any difference, it appears that the .model line is not parsed correctly and/or the VDMOS load routine is not working as it should.
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You should at least get some output when modifying the source line to: vsig 1 0 dc 0.01 pulse(0.0 {ampl} 0.0 {tr} {tr} {pw} 1.0) The parameters of the transmission line appear to be such that ngspice must use an extremely small step. It runs fine, but of course very slowly. Using SPARSE 1.3 as Direct Linear Solver Note: vsig: dc value used for op instead of transient time=0 value. Initial Transient Solution -------------------------- Node Voltage ---- ------- 2 0 3 0 4 0 1 0 5 0 vsig#branch 0 Reference...
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I have to run it (on Window 11) with an explicit path: * Waveform generation by Verilog delays adut null [ d4 d3 d2 d1 d0 ] ring .model ring d_cosim simulation="ivlng" sim_args=["D:/ngspice-ngspice/examples/xspice/verilator/delay"] .control tran 20u 100u 0 20u * see option digitop plot d4 d3 d2 d1 d0 .endc .end
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When plotting @m2[id], @m2[ig] and @m2[is], it appears the VDMOS device is breaking down. Given Fig.7.4 on page 168 of the manual, it could be that DBODY has been given default parameters that do not anticipate a high Vds. I don't see a way to set DBODY's parameters. Also note the 1us wide and 1.2 A high gate current spikes. That definitely happens in real circuits, but I am not sure the VDMOS model is supposed to predict it (the MOS1 model clearly does not).
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I always found the SPICE syntax for the .MEAS command, presented as a Backus-Naur diagram, very hard to follow. When taking a fresh look at it, it became easier to understand when viewed as the mechanical interface of an old oscilloscope. One of the ideas that came out of that is measuring AC frequency response using the TRIG and TARG keywords to set triggers on the frequency trace of the output file: .measure ac fdiff1 TRIG v(1) VAL=0.7 FALL=1 TARG v(1) VAL=0.5 FALL=1 This would not work as I expected...
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The .log file is fine, I see no issues. (Source stepping succeeded in finding the OP). The .rawfile looks like it is from LTspice, not from ngspice. I think you should close the ticket.
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I see nothing unusual here. I assume your line 1 actually reads launch NGspice 44 from Windows. Please add an new line between 3 and 4: Run the command "listing", there might be an obvious mistake. If not, it is time to start experimenting with .OPTIONS .
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I see nothing unusual here. I assume your line 1 actually reads launch NGspice 44 from Windows Please run an newline between 3 and 4: Run the command "listing", there might be an obvious mistake. If not, it is time to start experimenting with .OPTIONS .
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If found this suspicious: Note: Compatibility modes selected: ps lt Circuit: set ngbehavior=ltps.title kicad schematic It looks like the setcommand is on the same line as the .TITLE command. It could be that a linefeed is missing somewhere, or your spice.rc OS command is concatenated with the netlist. Why don't you use the pre_command to set options?
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Seven Gigabytes ... What does task manager say about memory and swap file usage when your programs run? Python is single-threaded, I am not sure what happens if it tries to coordinate separate instances of other programs.
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Seven Gigabytes ... What does task manager say about memory usage when your programs run? Python is single-threaded, I am not sure what happens if it tries to coordinate separate instances of other programs.
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I have to say that at least under Windows, I think it is quite unclear how to install ngspice for normal use and even more so for development. It took me about two weeks to get all the latest features to work (upgrading from vsn 32 to 44). Re-engineering what I did to fix it for me, and documenting the problems with configuration, tuning custom scripts, and seemingly wrong examples would certainly be a few more weeks work. (I am not complaining!)
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I have to say that at least under Windows, I think it is quite unclear how to install ngspice for normal use and even more so for development. It took me about two weeks to get all the latest features to work (upgrading from vsn 32 to 44). Re-engineering what I did to fix it for me, and documenting the problems with configuration, tuning custom scripts, and seemingly wrong examples would certainly be a few more weeks work.
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How much memory (in total) are you using (Python + all ngspice processes + additional tools or environments).
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The log looks like stdout only. Do you redirect stderr ?
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Note: All necessary files are included in the attachment. Except for the console output of ngspice with the startup and error messages.
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"ngspice-ngspice\examples\various\transformers1.cir" in the downloaded distribution. Or: https://forum.kicad.info/t/assigning-spice-code-to-a-transformer/52203 Or: https://sourceforge.net/p/ngspice/discussion/120973/thread/8b01a832/#d002 Modeling a transformer with capacitors and a gyrator is pretty advanced stuff and not something that is an advertized feature of ngspice. Good papers exist.
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The debugger can not assume that all the source files are available, and anyway, it doesn't know the project's root directory (absolute path). In my experience it sometimes asks the user for the location of a (source) file, or it hints to download development kits (e.g. when you trace into the Windows runtime and don't want assembly language). I'm curious, why do you want to know this?
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Maybe this helps: type the command showmod in the console after a simulation runs. It does not work for OSDI models. Manual 13.5.83, p414.
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The solver might recognise that, reduce the dimension and continue, .. I don't think that would work, and setting gmin surely would be an easier solution. A capacitor+voltage loop is much more difficult to fix...
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AFAIK, only inductor + current-source cut-sets matter. Capacitor+voltage source loops are the other topological problem (where two capacitors in parallel are not a formal topological loop).
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Two capacitors in parallel is OK, they will be stamped to a single one (there might be bugs getting the data out, will check that). No ground node violates a basic assumption and the MNA matrix is simply invalid. [edit] '(there might be bugs getting the data out, will check that)' No bugs (charge can't be asked for).
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Two capacitors in parallel is OK, they will be stamped to a single one (there might be bugs getting the data out, will check that). No ground node violates a basic assumption and the MNA matrix is simply invalid.
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Yes, first open the ngspice project debug solution, then attach, then set breakpoints. [edit] Note that the running ngspice and the VS project should match, i.e., both should be the debug version of ngspice. Trying to debug a release version of ngspice can be very frustrating as many source lines have been optimized away or altered.
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Yes, first open the ngspice project debug solution, then attach, then set breakpoints.
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The VS 'Debug' tab has an 'Attach' option. I allows to graphically select from a list of running programs. VS 'remembers' previous attachings so you can Reattach quickly after edits. Setting a conditional breakpoint in the running program is no different from setting it from VS itself: click in the left margin of the source line.
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I don't think using an Administrator account is a good idea. A normal user probably doesn't have (default) read or write access to this type of file. If you named it yourself I'd avoid this particular extension *.tmp : https://jetico.com/blog/what-are-tmp-files-how-should-i-delete-them/ . Ngspice is indeed generating *.tmp files (You can do a global search (alt-cntrl-f) in VS :-) but I'm not sure they are relevant for you in this stage.
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You did not install win_bison and win_flex, or they are not installed in the correct directory: RTFM :-) XSPICE uses *.mod and *.ifs files that have to be pre-processed to *.c with a dedicated preprocessor, CMPP.exe, that is also build by ngspice. The preprocessor is called by the compiler make files. It takes some mental gymnastics to understand this process at first.
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Manual: "28.2. NGSPICE COMPILATION UNDER WINDOWS OS", page 715. The problem is not with NGSPICE, it will be in finding your way in Visual Studio. (You don't want to let it install every possible support package.) There is an advantage to running the environment on Windows 11.
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I use Visual Studio under Windows 11. I'm sure it can be done with gdb too.
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Actually, I set a conditional breakpoint in the debugger "if iterno>7" and waited for the first break. (This simulation has deliberate changes of the operating point for t > 10ms. It makes sense that a smaller timestep results in less iterations, but the step size if very difficult to control. The total iterations is therefore difficult to interpret.)
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Thanks, that was fast.
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You match my understanding of P-C methods. The variant used in ngspice certainly does not preserve charge automatically (e.g. see ngspice manual for MOS level 1, p157, "The use of Meyer’s model for the C-V part makes it non charge conserving.") This seems to imply that a simulator based on a Gauss method still can be spoiled by a bad device model. In SPICE it is custom to define circuits where (almost) ideal capacitors are shorted by (almost) ideal switches at any arbitrary moment, and users expect...
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I use it but can't detect any positive (or negative) effect. Because it is in the solver its effect (speedup) should only become noticeable for very large circuits. [ edit ] Experiments with the ISCAS '85 benchmarks show that PREDICTOR slows them down by a few percent, lesser and lesser the bigger they are.
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...they are implicit ... I may be confused by terminology - in my understanding implicit methods need to guess the function value at the end of the next timestep, explicit methods only need access to the points we already have? The advantage of an implicit method is that it can be A-stable, while an explicit one never is (AFAIK). Interesting that a fixed step method is energy-preserving, that would explain what I observe for Digital Wave Filter type of approaches. There is a discussion in Chua &...
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...they are implicit ... I may be confused by terminology - in my understanding implicit methods need to guess the function value at the end of the next timestep, explicit methods only need access to the points we already have? The advantage of an implicit method is that it can be A-stable, while an explicit one never is (AFAIK). Interesting that a fixed step method can be A-stable, that would explain what I observe for Digital Wave Filter type of approaches. There is a discussion in Chua & Lin about...
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Yes, we can easily write a vector to a file with write <vector> <filename> and read it back with load <name>. For fourier, which is formatted as a table, one normally uses redirection to a text file fourier 25kHz V(out) > fourier.txt . Adding an arbitrary vector to a plot is more difficult because its scale may be different from the vectors already there. That is the problem at the root of this thread.
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Good to know! Meanwhile I added the experimental option '-s' to fourier in order to prevent creating any vectors.
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I use it but can't detect any positive (or negative) effect. Because it is in the solver its effect (speedup) should only become noticeable for very large circuits.
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Hi Carmelo, That is certainly a new and interesting idea. I thought (I'm not a mathematician) Gauss-Legendre was a method where the function needs to be known for a number of points in the interval over which to integrate. For circuit simulation we don't know that, it is a two-point boundary problem where the past is known for a (large) number of non-homogeneous steps, but where we have to guess a (single) next point. That is probably why you found the predictor - corrector references. Further problems...
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There is no change. .csparam does not define parameters. It just sends parameters into a .control section. Thanks, I have always struggled with understanding (or better, remembering) this. Reading it again, this is also what the manual says and has always said. When I have time, I'll dig around to see if I can find out what the fundamental reason is that only one of the following lines works fourier $&fs v(in) $ yes *fourier {fs} v(in) $ no *fourier fs v(in) $ no while the following three are all...
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The fourier <freq> <trace> command generates a very convenient table of results but also adds a vector to the current plot. Because (e.g.) fourier11 almost certainly does not have the same length as the other vectors in the current plot, saving the plot with ( e.g.) write f:/prinverter.raw results in a raw file that is unreadable. (This is because traces are checked for their maximum length and truncated when needed, but there is no check for their minimum size and subsequent padding.) Is it possible...
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.CSPARAM behavior changed?
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On 2020-04-11 20:24, p.h. wrote: Is there a way to iteratively change models based on some list given? I know there is altermod nch file = BSIM3_nmos.mod command, which makes it feasible to change model for the other, which must be loaded with .include or .model prior to use. I am struggling with doing this iteratively. I have tried like this: > * netlist of a circuit to be simulated > Q4 V2s_p V2s_p N002 0 BC560C_CA > Q2 V2s_p V1s_p N009 0 BC550C_CA > * netlist of a circuit to be simulated > > .include...
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As you said: /* * NIiter(ckt,maxIter) * * This subroutine performs the actual numerical iteration. * It uses the sparse matrix stored in the circuit struct * along with the matrix loading program, the load data, the * convergence test function, and the convergence parameters */ NR for a matrix / vector function... I doubt that CUDA for NR will do much, but don't let that hold you back. -marcel
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[ edited: fixed wrong paste -mhx ] Or do the following (note parallel resistor and extended frequency scale). The minimum is 12dB which is about 5 Ohms :-) -marcel * test I1 in 0 AC 1 Rp in 0 100MEG R1 in out 5 C1 out t1 10p L1 t1 0 10n .AC DEC 100000 1e8 1e10 .controlc run write imp.raw quit .endc .end
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In the first 10ms of the rather nasty examples/vdmos/dcdc.sp circuit ( ~38s runtime), iterno never gets above 7 and hovers around 2.
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For those that wonder what fell on the chopping block ... ITL1=x resets the dc iteration limit. The default is 100. ITL2=x resets the dc transfer curve iteration limit. The default is 50. ITL3=x resets the lower transient analysis iteration limit. the default value is 4. ITL4=x resets the transient analysis timepoint iteration limit. the default is 10. ITL5=x resets the transient analysis total iteration limit. the default is 5000. Set ITL5=0 to omit this test. ITL6=x resets the dc iteration limit...
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As a side question, is it important to have a defined title? Or should i still be fine with an empty line as a title? An empty line is fine, but invites (human) mistakes. If a .TITLE xxx yy line is provided, it is used to label program output with xxx yy.
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Tip: post the console output when asking such a question. If you indeed left out the title line, you saw: PS D:\spice\mhx\bug_snapLED> spice64w .\nick.cir ****** ** ngspice-44 : Circuit level simulation program ** Compiled with KLU Direct Linear Solver ** The U. C. Berkeley CAD Group ** Copyright 1985-1994, Regents of the University of California. ** Copyright 2001-2024, The ngspice team. ** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html ** Please file your bug-reports...
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This also suggests to me that timestap control algorithm could be helped out by keeping "last-1" timestep as well... This is already the case. The basic problem is, as you mention also, that NR estimates error assuming differentiable functions (additionally assuming not being off too far from the 'correct' point) and this condition is fragile. When events are present, even the smoothest curve can become discontinuous / non-differentiable. The simulator can go back to the previous event, hoping that...
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This also suggests to me that timestap control algorithm could be helped out by keeping "last-1" timestep as well... This is already the case. The basic problem is, as you mention also, that NR estimates error assuming differentiable functions (additionally assuming not being off too far off from the 'correct' point) and this condition is fragile. When events are present, even the smoothest function can become discontinuous / non-differentiable. The simulator can go back to the previous event, hoping...
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This also suggests to me that timestap control algorithm could be helped out by keeping "last-1" timestep as well... This is already the case. The basic problem is, as you mention also, that NR estimates error assuming differentiable functions (additionally assuming not being off too far off from the 'correct' point) and this condition is fragile. When events are present, even the smoothest function can become discontinuous / non-differentiable. The simulator can go back to the previous event, hoping...
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Capacitor voltages and inductor currents are the unknowns (to SPICE) to solve for, the former with KVL, the latter with KCL. The circuit under consideration has (at least) two loops of capacitors: C1, C2x, C3x, C4, and C4, C5x, C6x, C7. Furthermore L3a, L4, L5a is one cutset of inductors, L4 with L3b and L5b is another (maybe there are more, the definition of a cutset is not really intuitive). Picking individual voltages or currents and trying to prove that they can not be the operating point is...
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Capacitor voltages and inductor currents are the unknowns (to SPICE) to solve for, the former with KVL, the latter with KCL. The circuit under consideration has (at least) two loops of capacitors: C1, C2x, C3x, C4, and C4, C5x, C6x, C7. Furthermore L3a, L4, L5a is one cutset of inductors, L4 with L3b and L5b is another (maybe there are more, the definition of a cutset is not really intuitive). Picking individual voltages or currents and trying to prove that they can not be the operating point is...
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Capacitor voltages and inductor currents are the unknowns (to SPICE) to solve for, the former with KVL, the latter with KCL. The circuit under consideration has (at least) two loops of capacitors: C1, C2x, C3x, C4, and C4, C5x, C6x, C7. Furthermore L3a, L4, L5a is one cutset of inductors, L4 with L3b and L5b is another (maybe there are more, the definition of a cutset is not really intuitive). Picking individual voltages or currents and trying to prove that they can not be the operating point is...
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The OSDI models are really good, with very smooth derivatives on switching signals. There seems to be at least one feature missing: the showmod command does not work for these models (more precise: for bsimbulk107.osdi). It looks like a OSDIinfo->DEVmodAsk pointer is missing / not implemented. PS D:\examples\osdi\bsimbulk> spice64w .\bsimbulk_ro.sp ****** ** ngspice-44 : Circuit level simulation program ** Compiled with KLU Direct Linear Solver ** The U. C. Berkeley CAD Group ** Copyright 1985-1994,...
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The OSDI models are really good, with very smooth derivatives on switching signals. There seems to be at least one feature missing: the SHOWMOD command does not work for these models (more precise: for bsimbulk107.osdi): PS D:\examples\osdi\bsimbulk> spice64w .\bsimbulk_ro.sp ****** ** ngspice-44 : Circuit level simulation program ** Compiled with KLU Direct Linear Solver ** The U. C. Berkeley CAD Group ** Copyright 1985-1994, Regents of the University of California. ** Copyright 2001-2024, The ngspice...
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The OSDI models are really good, with very smooth derivatives on switching signals. There seems to be at least one feature missing: the SHOWMOD command does not work for these models (more precise: for bsimbulk107.osdi): PS D:\examples\osdi\bsimbulk> spice64w .\bsimbulk_ro.sp ****** ** ngspice-44 : Circuit level simulation program ** Compiled with KLU Direct Linear Solver ** The U. C. Berkeley CAD Group ** Copyright 1985-1994, Regents of the University of California. ** Copyright 2001-2024, The ngspice...
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The OSDI models are really good, with very smooth derivatives on switching signals. There seems to be at least one feature missing: the SHOWMOD command does not work for these models (more precise: for bsimbulk107.osdi): PS D:\examples\osdi\bsimbulk> spice64w .\bsimbulk_ro.sp ****** ** ngspice-44 : Circuit level simulation program ** Compiled with KLU Direct Linear Solver ** The U. C. Berkeley CAD Group ** Copyright 1985-1994, Regents of the University of California. ** Copyright 2001-2024, The ngspice...
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From my fresh ngspice-44 download and after doing the instructions involving openvaf-compile-va.bat I still get these two warnings: D:\>spice64w Error opening osdi lib "../lib/ngspice/BSIMBULK107.osdi": No such file or directory! Error: Library ../lib/ngspice/BSIMBULK107.osdi couldn't be loaded! Error opening osdi lib "../lib/ngspice/HICUMl0-2.0.osdi": No such file or directory! Error: Library ../lib/ngspice/HICUMl0-2.0.osdi couldn't be loaded! I think there is one missing and one probably wrong...
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The bsimbulk_ro.sp ring oscillator is a chain of inverters with the last one shorted by the input pulse source. Simply comment V1 out. Because V1 was dominating the timestep selection, set TSTEPMAX to 1 ps for a visually more convincing result. * BSIMBULK model vers. 107 * simple 5-stage ring oscillator .param Vcc = 1.2 .csparam vcc='Vcc' * Path to the models .include Modelcards/model.l * the voltage sources: Vdd vdd gnd DC 'Vcc' *V1 in gnd pulse(0 'Vcc' 0p 200p 100p 1n 2n) Vmeas vss 0 0 Xnot1 in...
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Capacitor voltages and inductor currents are the unknowns (to SPICE) to solve for, the former with KVL, the latter with KCL. The circuit under consideration has (at least) two loops of capacitors: C1, C2x, C3x, C4, and C4, C5x, C6x, C7. Furthermore L3a, L4, L5a is one cutset of inductors, L4 with L3b and L5b is another (maybe there are more, the definition of a cutset is not really intuitive). Picking individual voltages or currents and trying to prove that they can not be the operating point is...
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Capacitor voltages and inductor currents are the unknowns (for SPICE) to solve for, the former with KVL, the latter with KCL. The circuit under consideration has (at least) two loops of capacitors: C1, C2x, C3x, C4, and C4, C5x, C6x, C7. Furthermore L3a, L4, L5a is one cutset of inductors, L4 with L3b and L5b is another (maybe there are more, the definition of a cutset is not really intuitive). Picking individual voltages or currents and trying to prove that they can not be the operating point is...
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[It would be nice to upload a schematic and also state exactly what annoys you.] With vsn. 44 I see that ngspice needs the Transient op to find the DC operating point which is indeed rather unexpected, unless there are loops of V,C elements or cutsets of inductors (that's where the schematic comes in).
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In the mean time, maybe replace '\\' by ' ' ? Ngspice can handle very long lines (at least 40k characters long).
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In the mean time, maybe replace '\' by ' ' ? Ngspice can handle very long lines (at least 40k characters long).
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With the exception of the first step, it doesn't matter if you see it before or after factorization. NR factorizes the factorized matrix, not the original one. And even if it didn't do that, the MNA is the numerical linear approximation in the operating point (if you only use resistors and dc sources it still can be somewhat instructive).
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