Activity for George
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George modified a comment on discussion ngspice-users
Hello! I am writing extension for control of ngspice in form of shared library. My question is - what is the safe sequence for unloading shared library without memory corruption? My sequence is: 1. Tries to gracefully shut down background thread by bg_halt command, wait for the BGThreadRunning callback with some timeout (there is also checks that wait issuing bg_halt until thread is launched, if call to unload arrive at that transition time) 2. Send quit command to ngspice 3. Wait for ControlledExit...
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Hello! I am writing extension for control of ngspice in form of shared library. My question is - what is the safe sequence for unloading shared library without memory corruption? My sequence is: 1. Tries to gracefully shut down background thread by bg_halt command, wait for the BGThreadRunning callback with some timeout (there is also checks that wait issuing bg_halt until thread is launched, if call to unload arrive at that transition time) 2. Send quit command to ngspice 3. Wait for ControlledExit...
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Hello! I am writing extension for control of ngspice in form of shared library. My question is - what is the safe sequence for unloading shared library without memory corruption? My sequence is: 1. Tries to gracefully shut down background thread by bg_halt command, wait for the BGThreadRunning callback with some timeout (there is also checks that wait issuing bg_halt until thread is launched, if call to unload arrive at that transition time) 2. Send quit command to ngspice 3. Wait for ControlledExit...
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Hello! I am writing extension for control of ngspice in form of shared library. My question is - what is the safe sequence for unloading shared library without memory corruption? My sequence is: 1. Tries to gracefully shut down background thread by bg_halt command, wait for the BGThreadRunning callback with some timeout (there is also checks that wait issuing bg_halt until thread is launched, if call to unload arrive at that transition time) 2. Send "quit" command to ngspice 3. Wait for ControlledExit...
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Right after posting, I realized that I can just put quit command right after the write command...
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Hello! It may sounds strange, but my question is: Is it possible to override raw file that is specified with command line option -r in batch mode? For example, I want to save raw file inside .control section with write command under the same name as file specified with -r option, but with different vectors. If I just add write command, the file later is being overwritten by standard raw file. I know that I can just not specify -r option, but in my specific application, it is difficult to know if...
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As far as I know, there is no such feature now. In theory, it could be handled with compiling Ngspice as a shared library and control it precisely from external script that detects convergence issues, change tolerances and resume simulation, but still need confirmation from more experienced users
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As far as I know, there is no such feature now. In theory, it could be handled with compiling Ngspice and shared library and control it precisely from external script that detects convergence issues, change tolerances and continue running, but still need confirmation from more experienced users
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Hello, thank you for proposal, yes I can prepare that and check them with vampyre.
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I think it is not matter of output data precision, but the matter of solving some convergence issues, especially in power curcuits where difference between largest and lowest values could be much higher than in the case of IC circuits
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Simetrix has solver with quadprecision, also QSPICE has the 80 bit
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Hello! Thank you, these models already build for OSDI and Ngspice, and results on screenshots are from the ngspice simulation. Non-local model differs from local in the sense of how history is modelled. In local model we see the magnet as one large element with hysteresis, when in non-local the model consist of large number of individual relay hysterons, and each hysteron influence the total hysteresis curve and taking into account the full history. The advantage of non-local model is the ability...
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Hello! Thank you, these models already build for OSDI and Ngspice, and results on screenshots are from the ngspice simulation. Non-local model differs from local in the sense of how history is modelled. In local model we see the magnet as one large element with hysteresis, when in non-local the model consist of large number of individual relay hysterons, and each hysteron influence the total hysteresis curve and taking into account the full history. The advantage of non-local model is the ability...
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Hello! Thank you, these models already build for OSDI and Ngspice, and results on screenshots are from the ngspice simulation. Non-local model differs from local in the sense of how history is modelled. In local model we see the magnet as one large element with hysteresis, when in non-local the model consist of large number of individual relay hysterons, and each hysteron influence the total hysteresis curve and taking into account the full history. The advantage of non-local model is the ability...
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Hello! Thank you, these models already build for OSDI and Ngspice, and results on screenshots are from the ngspice simulation. Non-local model differs from local in the sense of how history is modelled. In local model we see the magnet as one large element with hysteresis, when in non-local the model consist of large number of individual relay hysterons, and each hysteron influence the total hysteresis curve and taking into account the full history: The advantage of non-local model is the ability...
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Hello! Thank you, these models already build for OSDI and Ngspice, and results on screenshots are from the ngspice simulation. Non-local model differs from local in the sense of how history is modelled. In local model we see the magnet as one large element with hysteresis, when in non-local the model consist of large number of individual relay hysterons, and each hysteron influence the total hysteresis curve and taking into account the full history: The advantage of non-local model is the ability...
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Hello! Thank you, these models already build for OSDI and Ngspice, and results on screenshots are from the ngspice simulation. Non-local model differs from local in the sense of how history is modelled. In local model we see the magnet as one large element with hysteresis, when in non-local the model consist of large number of individual relay hysterons, and each hysteron influence the total hysteresis curve and taking into account the full history: The advantage of non-local model is the ability...
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I have alternative Verilog-a models for the magnetic cores (see screenshot). They are easier for parameters extraction., there is a version that could be defined by the table data. They are written by myself for not public yet open-source project, write to georgtree@gmail.com if you want to get them. But keep in mind that models are local because creating non-local models like Presiah one with OSDI are not possible at the moment.
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I have alternative Verilog-a models for the magnetic cores (see screenshot). They are easier for parameters extraction. They are written by myself for not public yet open-source project, write to georgtree@gmail.com if you want to get them. But keep in mind that models are local because creating non-local models like Presiah one with OSDI are not possible at the moment.
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I have alternative Verilog-a models for the magnetic cores (see screenshot). They are easier for parameters extraction. They are written by myself for not public yet project, write to georgtree@gmail.com if you want to get them. But keep in mind that models are local because creating non-local models like Presiah one with OSDI are not possible at the moment.
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I have alternative Verilog-a models for the magnetic cores (see screenshot). They are easier for parameters extraction. They are written by myself for not public yet project, write to georgtree@gmail.com if you want to get them.
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I have alternative Verilog-a models for the magnetic cores (see screenshot). They are written by myself for not public yet project, write to georgtree@gmail.com if you want to get them.
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I have alternative Verilog-a models for the magnetic cores (see screenshot). They are written by myself for not public yet project, write to georgtree@gmail.com if you want to get them.
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hello! I am active user of xschem, but I see my tool as pure text way of working with simulator, but at higher level than basic netlists, because it create simulator independent interface to different engines, especially in control structures that differs a lot. all that now is responsibility of tcl. so it is rather an alternative to xschem and to it's gui schematic building approach.
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hello! I am active user of xschem, but I see my tool as pure text way of working with simulator, but at more higher level than basic netlists, because it create simulator independent interface to different engines, especially in control structures that differs a lot. all that now is responsibility of tcl. so it is rather an alternative to xschem and to it's gui schematic building approach.
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Hello! I hope I'm not violating any rules regarding self-promotion, but I’d like to share a project that could be helpful for Ngspice users working with scripting and automating simulations. I recently released a project called SpiceGenTcl. It provides a scripting interface for Ngspice (and Xyce) using an object-oriented approach to building circuits. With it, you can perform repeated simulations, modify circuit parameters and models, and even adjust the circuit's topology. The project includes detailed...
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Hello! I don't worry about the variable order but the formatting of the format itself, I see it as an inconsistency
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Two files side by side
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I found that on windows there is a difference between saving file explicitly with write command in .control section, and -r flag at command line...attached both files to this post
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I found that on windows there is a difference between saving file explicitly with write command in .control section, and -r flag at command line...will investigate it further
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I found that on windows there is a difference between saving file explicitly with write command in .control section, and -r flag at command line...will investigate it further
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I found that on windows there is a difference between saving file explicitly with write command in .control section, and -r flag at command line...will investigate it further
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The issue here if I read line by line, I need to have different cycles on different platforms...
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Also, does ascii format differs on linux and windows? I found that there are additional blank line...I suspect it is somehow connected with different line terminal symbols? Left - linux, right - windows
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Ok, I see, thank you!
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Hello! I use the same command that I use on Linux for running ngspice (except name of executable) in batch mode: ngspice_con -b -r output.raw circuit.cir and by default ngspice saves in ascii raw file format, to switch to binary I need to add set filetype=binary explicitly. it is a desirable behaviour? ngspice-43 Thank you in advance.
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I found an issue - there was a wrong configuration of file stream, it assumes that there are newline characters, after correction all works right: fconfigure $file -translation binary
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Also I tried this file, and script works until it breaks 2.959221488976008 2.9598796175063433 7.026947218616172e-192 -2.81709947717119e+160 -5.332451798449676e-110 I attached source raw file data.raw and test.csv with resulted data for v(osc_out). Don't quite understand why it works until particular line, there are simple for loops that must works the same for the whole data... P.S. and the same as above for time vector: ``` 8.408035545962357e-10 7.56745598000374e-10 7.597128615522043e-10 -1.6284671440047134e-18...
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Also I tried this file, and script works until it breaks 2.959221488976008 2.9598796175063433 7.026947218616172e-192 -2.81709947717119e+160 -5.332451798449676e-110 I attached source raw file data.raw and test.csv with resulted data for v(osc_out). Don't quite understand why it works until particular line, there are simple for loops that must works the same for the whole data... P.S. and the same as above for time vector: ``` 8.408035545962357e-10 7.56745598000374e-10 7.597128615522043e-10 -1.6284671440047134e-18...
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Also I tried this file, and script works until it breaks 2.959221488976008 2.9598796175063433 7.026947218616172e-192 -2.81709947717119e+160 -5.332451798449676e-110 I attached source raw file data.raw and test.csv with resulted data for v(osc_out). Don't quite understand why it works until particular line, there are simple for loops that must works the same for the whole data... P.S. and the same as above for time vector: ``` 8.408035545962357e-10 7.56745598000374e-10 7.597128615522043e-10 -1.6284671440047134e-18...
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Also I tried this file, and script works until it breaks 2.959221488976008 2.9598796175063433 7.026947218616172e-192 -2.81709947717119e+160 -5.332451798449676e-110 I attached source raw file data.raw and test.csv with resulted data for v(osc_out). Don't quite understand why it works until particular line, there are simple for loops that must works the same for the whole data... P.S. and the same as above for time vector: ``` 8.408035545962357e-10 7.56745598000374e-10 7.597128615522043e-10 -1.6284671440047134e-18...
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Also I tried this file, and script works until it breaks 2.959221488976008 2.9598796175063433 7.026947218616172e-192 -2.81709947717119e+160 -5.332451798449676e-110 I attached source raw file data.raw and test.csv with resulted data for v(osc_out). Don't quite understand why it works until particular line, there are simple for loops that must works the same for the whole data... P.S. and the same as above for time vector: ``` 8.408035545962357e-10 7.56745598000374e-10 7.597128615522043e-10 -1.6284671440047134e-18...
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Also I tried this file, and script works until it breaks 2.959221488976008 2.9598796175063433 7.026947218616172e-192 -2.81709947717119e+160 -5.332451798449676e-110 I attached source raw file data.raw and test.csv with resulted data for v(osc_out). Don't quite understand why it works until particular line, there are simple for loops that must works the same for the whole data... P.S. and the same as above for time vector: 8.408035545962357e-10 7.56745598000374e-10 7.597128615522043e-10 -1.6284671440047134e-18...
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Also I tried this file, and script works until it breaks 2.959221488976008 2.9598796175063433 7.026947218616172e-192 -2.81709947717119e+160 -5.332451798449676e-110 I attached source raw file data.raw and test.csv with resulted data for v(osc_out). Don't quite understand why it works until particular line, there are simple for loops that must works the same for the whole data...
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Also I tried this file, and script works until it breaks 2.959221488976008 2.9598796175063433 7.026947218616172e-192 -2.81709947717119e+160 -5.332451798449676e-110 I attached source raw file data.raw and test.csv with resulted data for v(osc_out)
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Also I tried this file, and script works until it breaks 2.959221488976008 2.9598796175063433 7.026947218616172e-192 -2.81709947717119e+160 -5.332451798449676e-110 I attached source raw file data.raw and test.csv with resulted data for v(osc_out)
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Here it is
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Hello, data was generated from ngspice, and there is a text near to binary representation, or do you mean something different?
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I see that all data saved as double, but when I read file with hex viewer with Little Endian double pattern and get garbage (on screenshot), when pattern is float, it at least generate some meaningful values...
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Hello! Is there a comprehensive explanation of raw binary format? I thought that I understand it right, but I got some strange random errors when reading it with my script (see screenshot attached). Don't understand how it can read right at some points, and not right at others. If I miss the byte size of block, then all consecutive values also should be wrong... I assume that we have <time><trace1><trace2>...<tracen> in binary double for all traces. Size of block was calculated right, don't understand...
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Hello! Is there a comprehensive explanation of raw binary format? I thought that I understand it right, but I got some strange random errors when reading it with my script (see screenshot attached). Don't understand how it can read right at some points, and not right at others. If I miss the byte size of block, then all consecutive values also should be wrong... I assume that we have <time><trace1><trace2>...<tracen> in binary double for all traces. Size of block was calculated right, don't understand...
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Hello! Is there a comprehensive explanation of raw binary format? I thought that I understand it right, but I got some strange random errors when reading it with my script (see screenshot attached). Don't understand how it can read right at some points, and not right at others. If I miss the byte size of block, then all consecutive values also should be wrong... I assume that we have <time><trace1><trace2>...<tracen> in binary double for all traces. Size of block was calculated right, don't understand...
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Hello! Is there a comprehensive explanation of raw binary format? I thought that I understand it right, but I got some strange random errors when reading it with my script (see screenshot attached). Don't understand how it can read right at some points, and not right at others. If I miss the byte size of block, then all consecutive values also should be wrong... I assume that we have <time><trace1><trace2>...<tracen> in binary double for all traces. Size of block was calculated right, don't understand...
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Hello! Is there a comprehensive explanation of raw binary format? I thought that I understand it right, but I got some strange random errors when reading it with my script (see screenshot attached). Don't understand how it can read right at some points, and not right at others. If I miss the byte size of block, then all consecutive values also should be wrong... I assume that we have <time><trace1><trace2>...<tracen> in binary double for all traces. Size of block was calculated right, don't understand...
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Hello! Is there a comprehensive explanation of raw binary format? I thought that I understand it right, but I got some strange random errors when reading it with my script (see screenshot attached). Don't understand how it can read right at some points, and not right at others. If I miss the byte size of block, then all consecutive values also should be wrong... I assume that we have <time><trace1><trace2>...<tracen> in binary double for all traces. Size of block was calculated right, don't understand...
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Hello! Is there a comprehensive explanation of raw binary format? I thought that I understand it right, but I got some strange random errors when reading it with my script (see screenshot attached). Don't understand how it can read right at some points, and not right at others. If I miss the byte size of block, then all consecutive values also should be wrong... I assume that we have <time><trace1><trace2>...<tracen> in binary double for all traces. Size of block was calculated right, don't understand...
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Hello! Is there a comprehensive explanation of raw binary format? I thought that I understand it right, but I got some strange random errors when reading it with my script (see screenshot attached). Don't understand how it can read right at one points, and not right at others. I if miss the byte size of block, then all consecutive values also should be wrong... I assume that we have <time><trace1><trace2>...<tracen> in binary double for all traces. Size of block was calculated right, don't understand...
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Hello! Is there a comprehensive explanation of raw binary format? I thought that I understand it right, but I got some strange random errors when reading it with my script (see screenshot attached). Don't understand how it can read right at one points, and not right at others. I if miss the byte size of block, then all consecutive values also should be wrong... I assume that we have <trace1><trace2>...<tracen> in binary double for all traces. Size of block was calculated right, don't understand what's...
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Hello! I finally found the issue, thank you!
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Hello! I use this command to generate swig wrapper: swig -tcl -DUSE_TCL_STUBS -DUSE_TK_STUBS filter.i And then Make file like this: all: filter.so CC=gcc BUILD=build filter.so: $(BUILD)/filter.o $(BUILD)/filter_wrap.o mkdir -p $(BUILD) $(CC) -shared $(BUILD)/filter.o $(BUILD)/filter_wrap.o -L/usr/lib/x86_64-linux-gnu/libtclstub8.6.a -L/usr/lib/x86_64-linux-gnu/libtkstub8.6.a -o $(BUILD)/filter.so $(BUILD)/filter.o: filter.h filter.c mkdir -p $(BUILD) $(CC) -c filter.c -fPIC -Wall -O3 -g -march=native...
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Hello! I use this command to generate swig wrapper: swig -tcl -DUSE_TCL_STUBS -DUSE_TK_STUBS filter.i And then Make file like this: all: filter.so CC=gcc BUILD=build CFLAGS = -DUSE_TCL_STUBS -DUSE_TK_STUBS filter.so: $(BUILD)/filter.o $(BUILD)/filter_wrap.o mkdir -p $(BUILD) $(CC) -shared $(BUILD)/filter.o $(BUILD)/filter_wrap.o -L/usr/lib/x86_64-linux-gnu/libtclstub8.3.a -o $(BUILD)/filter.so $(BUILD)/filter.o: filter.h filter.c mkdir -p $(BUILD) $(CC) -c filter.c -fPIC -Wall -O3 -g -march=native...
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Hello! I use this command to generate swig wrapper: swig -tcl -DUSE_TCL_STUBS -DUSE_TK_STUBS filter.i And then Make file like this: all: filter.so CC=gcc BUILD=build filter.so: $(BUILD)/filter.o $(BUILD)/filter_wrap.o mkdir -p $(BUILD) $(CC) -shared $(BUILD)/filter.o $(BUILD)/filter_wrap.o -o $(BUILD)/filter.so $(BUILD)/filter.o: filter.h filter.c mkdir -p $(BUILD) $(CC) -c filter.c -fPIC -Wall -O3 -g -march=native -o $(BUILD)/filter.o $(BUILD)/filter_wrap.o: filter_wrap.c filter.h mkdir -p $(BUILD)...
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I tried to provide static /usr/lib/x86_64-linux-gnu/libtcl8.6.a file during .so compilations, and it works as usual with tclsh, but after wraping it throw a Seg fault
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I find that Tcl_AppendResult is provided by libtcl8.6.so library, and tried to add it to wrap, but still no effect.
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Hello! In my tool I have compiled C shared library .so, and I load it into mail application through load. When I wrap my application and run it, I got this: Undefined symbol: Tcl_AppendResult I suspect that some binaries are not there in FreeWrap, is it possible to add them into it, or what else could be the issue? System is Ubuntu. Thank you in advance.
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Got it, thank you!
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Thank you, it is a very valuable information ! :) The only question is reltol - 1e-4 looks too small, no?
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Thank you, it is a very valuable information ! :)
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For now I prefer to use averaged models of power converters, but it is not always possible...
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Hello! I have a general question - what is the best way to improve convergence of circuits with switching converters. I tried: increased abstol and vntol to 1e-3 (voltages and currents in circuit in range of hundreds of amperes/volts), increase chgtol to 1e-12, add lseries in range of 1e-4 ... 1e-3, make all components less ideal, including power sources, inductors, etc. Also I tried to decrease maximum time steps. But unfortunately, I still experienced random time-step too small. What could be done...
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Got it, thank you. Do you have any tips to improve convergence in switching power circuit? I increased abstol, vntol, add lseries, reduces time step, what else could be done? Thank you in advance.
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Got it, thank you. Do you have any tips to improve convergence in switching power circuit? I increased abstol, vntol, add lseries, reduces time step, what else could be done? Thank you in advance.
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do you mean by discrete control the digital circuit with PWM ?
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okay, thank you for detailed explanation, so what could be the modification of circuit elements to avoid it? add bandwidth limiters to elements? i have similar issues with more complex direct field control circuit, it refuses to converge
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Yeah but how to define the order of non-ideality that leads to convergence? Set and try? Also, what is the issue with the algebraic loop for SPICE simulator? it anyway works on solution of the whole system of equations, it doesn't calculate from input to output sequentially from one block to another...
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Don't know why this post in devel forum, please moev it to help, thank you.
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Hello! I have circuit that implements volt-herz control of induction control with compensation. Circuit is on the screenshot, I can't put online all modules unfortunately. The results are on the second screenshot, that are right. But, if I remove delay from compensation feedback loop, the circuit stops convergence at the first time step, the error is: doAnalyses: TRAN: Timestep too small; initial timepoint: cause unrecorded. The default run option is UIC, but if I do DC-solution before transient...
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Hello! I have circuit that implements volt-herz control of induction control with compensation. Circuit is on the screenshot, I can't put online all modules unfortunately. The results are on the second screenshot, that are right. But, if I remove delay from compensation feedback loop, the circuit stops convergence at the first time step, the error is: doAnalyses: TRAN: Timestep too small; initial timepoint: cause unrecorded. The default run option is UIC, but if I do DC-solution before transient...
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Hello! I have circuit that implements volt-herz control of induction control with compensation. Circuit is on the screenshot, I can't put online all modules unfortunately. The results are on the second screenshot, that are right. But, if I remove delay from compensation feedback loop, the circuit stops convergence at the first time step, the error is: doAnalyses: TRAN: Timestep too small; initial timepoint: cause unrecorded. The default run option is UIC, but if I do DC-solution before transient...
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and such mechanism exists in commercial SPICEs, for example, in ADS simulator https://people.ece.ubc.ca/robertor/Links_files/Files/ICCAP-2008-doc/icref/icref0713.html
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and such mechanism exist in commercial SPICEs, for example, in ADS simulator https://people.ece.ubc.ca/robertor/Links_files/Files/ICCAP-2008-doc/icref/icref0713.html
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hello, yeah I understand that, just hoped that is not a big issue because of already existing mechanism of aliasing (presence of gnd alias). I need it for my open source project that brings together different physical domains: electrical, magnetic, mechanical, thermal, etc. I want to clearly distinguish for user different domains, do erc check, and each domain has its own reference. For ngspice there is no difference, but for user and highlighting mechanism of domain specific nets it's important....
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Add ability to add custom aliases for global 0 node
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You can see the issue on this screenshot, comparison of ngspice versus openmodelica. Ngspice circuit fires the pulse with value of it's width at start point, openmodelica gives value of width where saw-tooth signal cross the threshold, the true value. This difference affects the result because it accumulates.
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You can see the issue on this screenshot, comparison of ngspice versus openmodelica. Ngspice circuit fires the pulse with value of it's width at start point, openmodelica gives value of width where saw-tooth signal cross the threshold, the true value. This difference affects the result because it accumulates.
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You can see the issue on this screenshot, comparison of ngspice versus openmodelica. Ngspice circuit fires the pulse with value of it's width at start point, openmodelica gives value of width where saw-tooth signal cross the threshold, the true value. This difference affects the result because it accumulates.
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You can see the issue on this screenshot, comparison of ngspice versus openmodelica.
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But the same circuit works correctly in OpenModelica...
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But the same circuit works correct in OpenModelica...
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But the same circuit is work correct in OpenModelica...
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Th circuit is on the screenshot, I can't easily share the netlist because it depends on custom verilog-a components. This is open-loop DC-AC inverter with synchronization. PLL block is expanded on second screenshot, and H-bridge is on the third screenshot.
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Th circuit is on the screenshot, I can't easily share the netlist because it depends on custom verilog-a components. This is open-loop DC-AC convertor with synchronization. PLL block is expanded on second screenshot, and H-bridge is on the third screenshot.
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Hello, I did it below, thank you
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Th circuit is on the screenshot, I can't easily share the netlist because it depends on custom verilog-a components. PLL block is expanded on second screenshot, and H-bridge is on the third screenshot.
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Th circuit is on the screenshot, I can't easily share the netlist because it depends on custom verilog-a components. PLL block is expanded on second screenshot.
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Th circuit is on the screenshot, I can't easily share the netlist because it depends on custom verilog-a components.
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First screenshot is from saw-tooth PWM with 1us max time step, the second with max time step 100us. As you can see, the difference is actually matter.
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This is an example of error that accumulates, white - correct PWM, blue - result from sub-circuit in first post. I consider this as a large error.
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First screenshot is from saw-tooth PWM with 1us max time step, the second with max time step 100us
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