PathWave RFIC Design

Ansys Exalto is a post-LVS RLCk extraction software solution that enables IC designers to accurately capture unknown crosstalk among different blocks in the design hierarchy by extracting lumped-element parasitics and generating an accurate model for electrical, magnetic and substrate coupling. Exalto interfaces with most LVS tools and can complement the RC extraction tool of your choice. Ansys Exalto post-LVS RLCk extraction lets IC designers accurately predict electromagnetic and substrate coupling effects for signoff on circuits that were previously "too big to analyze.” The extracted models are back-annotated to the schematic or netlist, and support all circuit simulators. The proliferation of RF and high-speed circuits in modern silicon systems has raised electromagnetic coupling to a first order effect that must be accurately modeled to reliably achieve silicon success.

Go beyond traditional RF simulation to design, analyze, and verify radio frequency integrated circuits (RFICs). Achieve confidence with steady-state and nonlinear solvers for design and verification. Wireless standard libraries accelerate the validation of complex RFICs. Model components on silicon chips accurately. Optimize designs with sweeps and load-pull analysis. Simulate RF designs in the Cadence Virtuoso and Synopsys Custom Compiler environments. Increase performance using Monte Carlo and yield analysis. Assess error vector magnitude (EVM) for the latest communication standards early in the design phase. Use the latest foundry technology immediately. Monitoring system IC specifications such as EVM via RF simulation early in the RFIC design phase is a must. Simulations include effects of layout parasitics, complex modulated signals, and digital control circuitry. With Keysight RFPro Circuit, you can simulate in both the frequency and time domain.