Search Results for "fsm"
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Showing 50 open source projects for "fsm"
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FSM for Go
Finite State Machine for Go
FSM is a finite state machine for Go. It is heavily based on two FSM implementations. Javascript Finite State Machine, and Fysom for Python. Visualize outputs a visualization of a FSM in Graphviz format. VisualizeForMermaidWithGraphType outputs a visualization of a FSM in Mermaid format as specified by the graphType. VisualizeWithType outputs a visualization of a FSM in the desired format. -
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Django friendly finite state machine
Django friendly finite state machine support
...These methods could contain side effects of the state change. You may also take a look at the Django-fsm-admin project containing a mixin and template tags to integrate Django-fsm state transitions into the Django admin. FSM really helps to structure the code, especially when a new developer comes to the project. FSM is most effective when you use it for some sequential steps. Transition logging support could be achieved with help of django-fsm-log package. -
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Active Object real-time OS
AO RTOS is small real time OS based on Active Object concurrency model
AO-RTOS is a pure object-oriented small footprint real-time operating system for embedded devices. The project is using Active Object (or Actor) concurrency model and finite state machine (FSM) design template as implementation base. -
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StateS
Draw and Simulate Finite States Machines (FSM)
Simple tool for drawing Finite State Machines (FSMs). StateS has moved to GitHub and will no longer be updated on SourceForge. New link: https://github.com/ClementFoucher/StateS -
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The FSKC is a CASE tool that allows developers to specify all valid and invalid state-event combinations of a finite state machine (FSM) through a simple to use GUI. Functions called from the FSK can be coded and linked to form a complete FSM.
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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glint
A tool for finite state machine analysis and synthesis.
...You just tell glint how you would like your control entity to operate and glint returns to you the synthesised magic black box which implements the desired logic. Also glint can tell you in regexp style which event sequences your FSM can handle and which are forbidden for it. -
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FSM: Font System Manager
FSM is a tool designed to bridge the gap between ImageMagick & paperjs
...This makes it difficult to reproduce accurately effects, for example, in video projects where the placement of text, sub-images, etc needs to be tested before production. While paperjs will render a scene in a browser context, it cannot be used in production, where ImageMagick is necessary. FSM allows for the classification of usable fonts for both these interfaces, accurate measurement of font dimensions such as descender, bearing, and extended bearing, and the means for translating between the differing font description systems used. This script which requires: *PHP >= 7.0 *MySQL >= 5.6 *ImageMagick >= 6.9, Imagick for PHP Paperjs and jquery are bound in via CDN. ... -
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Java FSM Library : DynamicEasyFSM
Dynamic FSM Library
This library can be dynamically changed as per developers whims. It just needs a XML Configuration file and User defined Action functions which can be implemented as FSM Listeners. Git Page: http://ankzz.github.io/easyfsm -
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FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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Korat2015
Enhanced Korat supports GUI, FSM, JUNG and JSON.
Korat is a tool for constraint-based generation of structurally complex test inputs for Java programs. Please see http://korat.sourceforge.net/index.html for more information on the Korat application. Korat 2015 includes the below enhancements to Korat: - Graphical User Interface using Java Swing - Graph Output Format using JUNG (Java Universal Network/Graph Framework) - Finite State Machine Domain - Graph Archival using JSON (JavaScript Object Notation) The Wiki page has... -
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AnotherFSM
State machines for Java, FSM.
AnotherFSM is yet another implementation of state machines, a library for Java programming language. -
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OOPSGen
Object Oriented Parser Generator
...Long term goals include a robust grammar file syntax, output suitable for multiple programming languages, and tools for better integrating compiler functionality, parse tree manipulation, and FSM based scanner generation. -
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PoSecCo ModelMaintainer
The ModelMaintainer contains 4 tools needed to create the PoSecCo FSM.
... - The CMDBTransformer extracts information about the service provider’s landscape from the CMDB and creates instances of the Infrastructure layer of the PoSecCo FSM. - The CrossLayerLink tool supports the maintenance of the cross-layer links between the instances of the three layers of the PoSecCo FSM. - The ServiceProviderTemplate tool can be used to create landscape models for the suppliers, in the case they are not using the PoSecCo tools. - The StatusSetter Tool displays the completion status of the PoSecCo FSM and its layers and allows to modify it. ... -
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PHP web-application framework including MVC, GUI, ORM, FSM, ACL, Ajax and many more. Very useful toolset to build php web-applications from the simpliest to more complex systems. See www.mywebframe.com for more details!
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Bavieca (www.bavieca.org)
Bavieca is an open-source speech recognition tookit.
Bavieca (www.bavieca.org) is an open-source speech recognition toolkit intended for speech research and as a platform for rapid development of speech-enabled solutions by non speech experts. It comprises the most common acoustic modeling and adaptation techniques including discriminative training, and efficient dynamic and FSM-based decoders that can operate in batch and live recognition modes. Bavieca is entirely written in C++ and distributed under the Apache 2.0 license. Bavieca was developed at Boulder Language Technologies (BLT) during the last three years in response to the needs of the research projects conducted within the company. Research at BLT includes the development of conversational dialog systems and assessment tools that are deployed in formal educational settings and other real-life scenarios. -
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compactfsm
a compact FSM library in C for embedded systems
This is a compact C library for deeply embedded systems. It uses state table approach and extends it with conditional variables and context information so that multiple state machines of same type can be executed in parallel. -
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EasyFsm
EasyFSM is a tool for generate finite state machine code quickly
EasyFSM is aimed to automatically generate code for finite state machine, especially for the NPC behavior programming in games. Using this tool, you just need to edit a .fsm file to describe the state machince concisely. It will generate the Java code for you according the .fsm file. Also, a .gv file for GraphiZ can be created for visualizing the finte state machine. -
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The BetaSDK project has been started to bridge the gap between SDK and game development suite using the XNA 4.0 Game Studio SDK.
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A Java library containing utility classes used by my other public projects. A few classes depend on the dk.brics.automaton FSM library.
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The embedded Finite State Machine (FSM) Facility that can be used to model and control a reactive or stateful system. The system can be represented by any number of states. State transitions are driven by a number of events. eFSM is written in C.
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Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format. This project is ported to github and can be found at: https://github.com/chiphackers/covered
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StateCore is a generic finite state machine (FSM), based on the state pattern and written in C++. - Project: ceStateCore.sourceforge.net - CorEngine Blog: CorEngine.wordpress.com
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A simple and intiutive Finite State Machine written purely in Java for everyday developers with low learning curve and a complete runnable example that comes in the zip for easy understanding. Pls Checkout the Project Homepage for detailed documentation