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YU235482A - Method of amplifying i/o transmissions in a system of processing said data - Google Patents

Method of amplifying i/o transmissions in a system of processing said data

Info

Publication number
YU235482A
YU235482A YU02354/82A YU235482A YU235482A YU 235482 A YU235482 A YU 235482A YU 02354/82 A YU02354/82 A YU 02354/82A YU 235482 A YU235482 A YU 235482A YU 235482 A YU235482 A YU 235482A
Authority
YU
Yugoslavia
Prior art keywords
transmissions
amplifying
data
processing
Prior art date
Application number
YU02354/82A
Other languages
English (en)
Inventor
K L York
P R Annal
J E Legory
Original Assignee
Burroughs Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Burroughs Corp filed Critical Burroughs Corp
Publication of YU235482A publication Critical patent/YU235482A/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Storage Device Security (AREA)
YU02354/82A 1979-02-02 1982-10-19 Method of amplifying i/o transmissions in a system of processing said data YU235482A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/009,250 US4244049A (en) 1979-02-02 1979-02-02 Method and apparatus for enhancing I/O transfers in a named data processing system

Publications (1)

Publication Number Publication Date
YU235482A true YU235482A (en) 1983-12-31

Family

ID=21736515

Family Applications (2)

Application Number Title Priority Date Filing Date
YU00093/80A YU9380A (en) 1979-02-02 1980-01-15 Arrangement for i/o (input/outpu) transmission amplification in a system for processing said data
YU02354/82A YU235482A (en) 1979-02-02 1982-10-19 Method of amplifying i/o transmissions in a system of processing said data

Family Applications Before (1)

Application Number Title Priority Date Filing Date
YU00093/80A YU9380A (en) 1979-02-02 1980-01-15 Arrangement for i/o (input/outpu) transmission amplification in a system for processing said data

Country Status (7)

Country Link
US (1) US4244049A (xx)
JP (1) JPS55103661A (xx)
BR (1) BR8000346A (xx)
DE (1) DE3002048A1 (xx)
FR (1) FR2448191B1 (xx)
GB (1) GB2040521B (xx)
YU (2) YU9380A (xx)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU530568B2 (en) * 1980-10-31 1983-07-21 Canon Kabushiki Kaisha Serial printing apparatus with memory and display
US4596014A (en) * 1984-02-21 1986-06-17 Foster Wheeler Energy Corporation I/O rack addressing error detection for process control
JPS6115230A (ja) * 1984-06-29 1986-01-23 Nec Corp 入力デ−タ識別装置
US4903229A (en) * 1987-03-13 1990-02-20 Pitney Bowes Inc. Forms generating and information retrieval system
AU3594189A (en) * 1988-06-21 1990-01-04 Amdahl Corporation Controlling the initiation of logical systems in a data processing system with logical processor facility
US5126728A (en) * 1989-06-07 1992-06-30 Hall Donald R ADP security device for labeled data
US5347579A (en) * 1989-07-05 1994-09-13 Blandford Robert R Personal computer diary
EP0858074B1 (en) * 1989-07-13 2001-10-17 Canon Kabushiki Kaisha Encoding device and decoding device suitable for dubbing
JP3561002B2 (ja) * 1994-05-18 2004-09-02 富士通株式会社 ディスク装置
KR102331926B1 (ko) * 2017-11-17 2021-11-29 삼성전자주식회사 저장 장치를 포함하는 호스트 시스템의 동작 방법 및 저장 장치 제어기의 동작 방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3825903A (en) * 1973-04-30 1974-07-23 Ibm Automatic switching of storage protect keys
US3825893A (en) * 1973-05-29 1974-07-23 Ibm Modular distributed error detection and correction apparatus and method
US3920976A (en) * 1974-08-19 1975-11-18 Sperry Rand Corp Information storage security system
JPS5130444A (xx) * 1974-09-09 1976-03-15 Hitachi Ltd
JPS5245837A (en) * 1975-10-08 1977-04-11 Hitachi Ltd Error detection equipment
US4020459A (en) * 1975-10-28 1977-04-26 Bell Telephone Laboratories, Incorporated Parity generation and bus matching arrangement for synchronized duplicated data processing units
DE2721599C2 (de) * 1976-05-17 1983-05-05 Sperry Corp., 10019 New York, N.Y. Schaltungsanordnung zur Verhinderung der Ausgabe von Datenworten aus einer EDV-Anlage ohne Sicherheitsverifizierung
JPS6034182B2 (ja) * 1976-08-17 1985-08-07 松下電器産業株式会社 信号誤り検出訂正方式
JPS53106110A (en) * 1977-02-28 1978-09-14 Nec Corp Magnetic memory controller
US4166211A (en) * 1978-04-03 1979-08-28 Burroughs Corporation Error control system for named data

Also Published As

Publication number Publication date
FR2448191B1 (fr) 1985-10-25
FR2448191A1 (fr) 1980-08-29
YU9380A (en) 1983-04-30
DE3002048C2 (xx) 1989-08-03
DE3002048A1 (de) 1980-08-14
US4244049A (en) 1981-01-06
BR8000346A (pt) 1980-10-07
JPS55103661A (en) 1980-08-08
GB2040521A (en) 1980-08-28
GB2040521B (en) 1983-03-02

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