WO2026005780A1 - Automatic data timing adjustment - Google Patents

Abstract

Methods, systems, and apparatus, for determining an appropriate data alignment for proper reading and processing of the data. In an aspect, a stability detection stage receives, as input, input data at a frequency of a data clock signal and processes the input data at a rate greater than the data clock signal and generates stability range data that is indicative of stability within the input data. A delay selection stage receives, as input, the stability range data and generates, based on the stability range data, selection data that corresponds to a particular time delay that corresponds to a time at which the input data is stable. An output selection stage that receives, as input, the selection data and, in response, generates, as output a delayed version of the input data or reference clock that is delayed by the particular time delay.

Description

AUTOMATIC DATA TIMING ADJUSTMENT

BACKGROUND

[0001] When reading the input from a data source, such as digital microphone, or writing to an amplifier with digital input, ensuring data integrity at higher clock speeds can be challenging. Data integrity can be degraded, for example, when a system clock is not aligned with the data due to clock drift. There are many causes for such drift. One such cause is adhering to EMI compliance requirements, where various kinds of filtering components (beads, capacitors, resistors) are used to ensure regulations and signal integrity is met. Another cause is system propagation delay through wires or PCB traces and various active and passive circuits. These delays may affect timing so that it is difficult to guarantee a valid '‘eye-opening” when reading the data.

[0002] One technique to reduce this error is to slightly delay the data relative to the clock to obtain timing closure. For example, fixed delays can be built in for a particular design. However, due to process variations, such delays may not be optimal across multiple chips. Moreover, due to operational variations caused by, for example, age and temperature, the fixed delays may not account for cases of extreme timing drift during operation. Finally, while some systems do adjust to accommodate an eye opening, they do not do so by merely processing data received from the transmitter.

SUMMARY

[0003] This disclosure describes devices and techniques to facilitate optimal sample adjustment for input data, which results in a more accurate eye-opening when reading the data relative to other systems that cannot realize such automatic adjustments based on the received data alone. The systems and methods described below independently seek and adjust for an optimal time delay so as to improve timing margins from data received from another device. The timing adjustment is based on the received data alone, resulting in a robust design.

[0004] In general, one innovative aspect of the subject matter described in this specification can be embodied in an apparatus that includes a stability' detection stage that receives, as input, input data at a frequency of a data clock signal and processes the input data at a different frequency rate than the data clock signal and generates stability range data that is indicative of stability within the input data; a delay selection stage that receives, as input, the stability range data and generates, based on the stability range data, selection data that corresponds to a particular time delay that corresponds to a time at which the input data is stable: and an output selection stage that receives, as input, the selection data and, in response, generates, as output, one of a delayed version of the input data or data clock signal that is delayed by the particular time delay. Other embodiments of this aspect include corresponding methods, apparatus, and computer programs, configured to perform the actions of the methods, encoded on computer storage devices. [0005] These and other embodiments can each optionally include one or more of the following features. In the aspect above, the stability detection stage may comprise a correlation stage that receives, as input, the input data at the frequency of the data clock signal and correlates the input data with a delayed instance of the input data to generate correlation output data and generates, as output, a plurality of delayed instances of correlation output data, each delayed instance of the correlation output data being correlation output data delayed by a respective time delay; and the delay selection stage receives, as input the plurality of delayed instances of the correlation output data and generates, based on the delayed instances of the correlation output data, the selection data that corresponds to the particular time delay.

[0006] In the aspects above, the correlation stage may comprise a correlation circuit that receives, as input, the input data at the frequency of the data clock signal and correlates the input data with the delayed instance of the input data to generate the correlation output data; and a first delay stage that receives, as input, the correlation output data and generates, as output, the plurality of delayed instances of the correlation output data.

[0007] In the aspects above, the delay selection stage may comprise a storage circuit that stores data based on the correlation output data and the delayed instances of the correlation output data; and a selection processor that generates, based on the correlation output data and the delayed instances of the correlation output data, the selection data that corresponds to the particular time delay.

[0008] In the aspects above, the selection processor may generate the selection data based on a plurality of delayed instances of the correlation output data being a same value, and wherein the selection data specifies a respective time delay of one of the respective time delays of the plurality of delayed instances of the correlation output data that are of the same value. [0009] In the aspects above, the storage circuit may comprise a plurality of set/reset flip flops, wherein each set/reset flip flop corresponds to a respective time delay.

[0010] In the aspects above, the selection processor may generate the selection data based on the output of the set/reset flip-flops indicating a stable data value, and wherein the selection data specifies a respective time delay of one of the respective time delays of the plurality of set/reset flip-flops.

[0011] In the aspects above, the output selection stage may comprise a multiplexor that receives, as input, the input data and a plurality of delayed instances of the input data, each delayed instance of the input data being the input data delayed by a respective time delay, and, based on the selection data received from the delay selection stage, selects one the input data or one of the plurality of delayed instances of the input data as output. [0012] In the aspects above, the output selection stage may further comprise a second delay stage that receives, as input, the input data at the frequency of the data clock signal and generates, as output, the plurality of delayed instances of the input data.

[0013] In the aspects above, the correlation stage may comprise a dual-mode correlation and delay stage, comprising: a correlation circuit that receives, as input, the input data at the frequency of the data clock signal and correlates the input data with a delayed instance of the input data to generate correlation output data; a dual-mode delay stage that operates in a first mode and a second mode, wherein: in the first mode, the dual mode delay stage receives, as input, the correlation output data and generates, as output, the plurality of delayed instances of the correlation output data; and in the second mode, the dual mode delay stage receives, as input, the input data at the frequency of the data clock signal and generates, as output, a plurality of delayed instances of the input data, each delayed instance of the input data being the input data delayed by a respective time delay.

[0014] In the aspects above, the delay selection stage may comprise a storage circuit that stores data based on the correlation output data and the delayed instances of the correlation output data; and a selection processor that generates, based on the correlation output data and the delayed instances of the correlation output data, the selection data that corresponds to the particular time delay.

[0015] In the aspects above, the selection processor may generate the selection data based on a plurality of delayed instances of the correlation output indicating data being of the same value, and wherein the selection data is specified by one of the respective time delays of the plurality of delayed instances of the correlation output data that are of the same value.

[0016] In the aspects above, the selection processor may generate the selection data based on a plurality of respectively accumulated delayed instances of the correlation output data, and wherein the selection data specifies a respective time delay of one of the respective time delays of one of the respectively accumulated delayed instances of the correlation output data.

[0017] In the aspects above, the selection processor may generate the selection data based on a respectively accumulated delayed instances of the correlation output data that has a highest accumulated value relative to the other respectively accumulated delayed instances of the correlation output data, where a high correlation indicates sample values that are the same or close in value.

[0018] In the aspects above, the output selection stage may comprise a multiplexor that receives, as input, the input data and a plurality of delayed instances of the input data, each delayed instance of the input data being a delayed by a respective time delay, and, based on the selection data received from the delay selection stage, selects one the input data or one of the plurality of delayed instances of the input data as output.

[0019] In the aspects above, the correlation stage may comprise: a first delay stage that receives, as input, the input data at the frequency of the data clock signal and generates, as output, a plurality of delayed instances of the input data, each delayed instance of the input data being a delayed instance of the input data delayed by a respective time delay; and a correlation circuit that receives, as input, the delayed instances of the input and generates, as output the plurality of delayed instances of the correlation output data.

[0020] In the aspects above, the first delay stage may comprise a plurality of analog delay stages.

[0021] In the aspects above, the first delay stage may be a plurality of digital delays, and each digital delay is driven by a respectively phase output of a delay locked loop multi-phase clock generator that is driven by a source clock signal.

[0022] In general, another innovative aspect of the subject matter described in this specification can be embodied in methods that include the actions of generating, based on input data received at a frequency of a data clock signal, stability detection stage that receives, as input, input data at the frequency of the data clock signal and processes the input data at a rate greater than the data clock signal to generate stability range data that is indicative of stability within the input data; selecting, based on the stability range data, a particular time delay, the particular time delay being a time delay that corresponds to a time at which the input data is stable; and generating, as output, one of a delayed version of the input data or data clock signal that is delayed by the particular time delay. Other embodiments of this aspect include corresponding systems, apparatus, and computer programs, configured to perform the actions of the methods, encoded on computer storage devices.

[0023] These and other embodiments can each optionally include one or more of the following features. In the aspect above, the stability range data may comprise correlation output data and a plurality of delayed instances of the correlation output data, wherein each correlation output data is a correlation of the input data with a delayed instance of the input data delayed by a respective time delay; and selecting, based on the stability data, the particular time delay comprises selecting a time delay that corresponds to a plurality of positive instances detected within the correlation output data and the plurality of delayed instances of the correlation output data.

[0024] In the aspects above, selecting a particular time delay may comprise generating a plurality of respectively accumulated delayed instances of the correlation output data, generating the selection data based on a respectively accumulated delayed instances of the correlation output data that has a highest accumulated value relative to the other respectively accumulated values.

[0025] In the aspects above, selecting a particular time delay may comprise determining consecutive portions of the plurality' of delayed instances of the correlation output data of indicating a stable data value; and selecting a respective time delay of one of the respective time delays of the plurality of delayed instances of the correlation output data that are indicating a stable data value.

[0026] These and other embodiments can each optionally realize one or more of the following advantages. The systems and methods described below realize delay adjustments based on the received data alone, and thus the adjustments are robust with respect to process, voltage and temperature (PVT) variations. Moreover, the delays may be determined at any time, or according to an event, e.g., during startup, and thus the system and methods do not suffer from the drawbacks of fixed-delay solutions. The systems and methods described below enable the finding of points at which the received data signal is fully stable. Accordingly, the systems and methods enable finding an optimal sampling point for "eye-patterns" without non-data interactions from the transmitter. By processing and making the selection based on the received data, the systems and methods realize devices that are more robust to clock system delays induced by external factors such as processing delay, capacitance and inductive delays, etc. Furthermore, the system will not need external devices to be part of the calibration procedure or include requirements for special external hardware to perform the calibration. This means the calibration can be performed transparently regardless of the externally connected devices. Furthermore, this may enable an increase in the maximum frequency of operation by accurately finding the optimal sampling point.

[0027] The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below.

Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Fig. 1 is a block diagram of a system that uses a delay selector to realize automatic data sample adjustment.

[0029] Fig. 2A is a timing diagram illustrating the impact of clock delay when reading data.

[0030] Fig. 2B is a timing diagram illustrating a proper adjustment for reading data.

[0031] Fig. 3A is a block diagram of a delay selector that determines a delay from processing input data.

[0032] Fig. 3B is a timing diagram illustrating correlation data for determining a timing delay.

[0033] Fig. 3C is a flow diagram of an example process for determining a timing delay.

[0034] Fig. 4 is an example implementation of a delay selector that determines a delay from processing input data.

[0035] Fig. 5A is another example implementation of a delay selector that determines a delay from processing input data.

[0036] Fig. 5B is another example implementation of a delay selection stage that can be used with the example implementation of Fig. 5A. [0037] Fig. 6A is another example implementation of a delay selector that determines a delay from processing input data.

[0038] Fig. 6B is an example timing diagram of phase signals for the example implementation of Fig. 6A.

[0039] Fig. 7 is another example implementation of a delay selector that determines a delay from processing input data.

[0040] Fig. 8 is a flow diagram of another example process for determining a timing delay.

[0041] Fig. 9A is a block diagram of a time division multiplexing system that uses a delay selector to realize automatic data adjustment.

[0042] Fig. 9B is a TDM timing diagram.

[0043] Fig. 10 is a timing diagram for a multi-bit pulse density modulation (PDM) system.

[0044] Fig. 11 is a timing diagram for a stereo pulse width modulation (PWM) system.

[0045] Fig. 12 is a timing diagram for a mono PWM system.

[0046] Fig. 13 is an example implementation of a delay selector that determines a delay to phase shift a clock relative to the input data.

[0047] Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION

[0048] This disclosure describes devices and techniques to facilitate optimal sample adjustment for input data in a manner that results in a more accurate "eye-opening" when reading the data compared to other systems that cannot realize such automatic adjustments based on the received data alone.

[0049] In operation, a delay selector receives input data at a frequency of a data clock signal. The data clock signal is usually at a lower frequency than a processing clock, e.g., a system clock. For example, the data clock signal frequency can be 1/N the system clock frequency, where N = 8, 12, 16, etc.

[0050] The delay selector then processes the input data at a frequency greater than the data clock signal to generate stability- range data that is indicative of stability within the input data. In some implementations, stability is determined by a correlation operation that generates correlation output data and a plurality of delayed instances of the correlation output data. Each correlation output data is a correlation of the input data with an instance of the input data delayed by a respective time delay. The stability data is, for example, generated at a frequency rate that is greater than the data clock signal. For example, the stability data can be generated at the frequency of the system clock, where the data clock signal frequency is 1/N the system clock frequency.

[0051] Based on the stability range data, the delay selector then selects a particular time delay that corresponds to a time at which the input data is stable. In the case of correlation output data, the particular time delay that is selected corresponds to a plurality of positive instances detected within the correlation output data and the plurality of delayed instances of the correlation output data.

[0052] As used in this specification, “stability within the input data’ refers to a change between the value of the input data and a prior delayed instance of the input data being below a threshold. For example, if the two consecutive samples of the input data both indicate a logic 0 value, then the data is stable. Likewise, if the two consecutive samples of the input data both indicate a logic 1 value, then the data is also stable. However, if the first sample and the second sample of the input data are different by more than a threshold value, e.g., such as two consecutive samples taken during either a rising signal edge or falling signal edge, then the data is unstable.

[0053] Also as used in this specification, a “positive instance” of correlation data refers to correlation data that indicates two (or more) samples of data are highly correlated, e.g., equal. Depending on the processing and circuity used, a “positive instance” of correlation data can be a binary value, e.g., a “1” when an exclusive NOR gate is used as a correlation operation, or a “0” when an exclusive OR gate is used to realize a correlation operation for two data values. Likewise, a “positive instance” of correlation data can be a count value, where the higher the count value, the higher the measure of correlation of the data. Additionally, when using a count value, a “positive instance” of correlation data may be low value, where the lower the count value, the higher the measure of correlation of the data. Thus, a “positive instance” can be any number, be it binary number, a count number, or even a real number, that is used to measure correlation, and the magnitude of the measurement may be proportional (or inversely proportional) to the measure of correlation, depending on the convention used. [0054] The delay selector also generates, based on the input data received at a frequency of a data clock signal, a plurality of delayed instances of the input data. Each delayed instance of the input data is delayed by a respective time delay. For example, each delay instance may be delayed by a time delay proportional to the frequency of the system clock, which may be N times greater than the frequency of the data clock used to clock the input data.

[0055] The delay selector then selects, as an output, one of the input data or one of the plurality of delayed instances of the input data, based on selected particular time delay. By doing so, the delay selector selects an eye opening for the data that is near an optimal position.

[0056] These features and additional features are described in more detail in the remainder of this written description. While many different example implementations are described below, other implementations that realize the features described below can also be used.

[0057] Fig. 1 is a block diagram of a system 10 that uses a delay selector 100 to realize automatic data sample adjustment. A data processor 20 includes a clock 22 and buffer 24 to generate a system clock, also referred to as source clock signal. The data processor 20 receives data from devices 40 and 50, e.g., microphone devices (or some other data source that provides data). The microphones 42 and 52 transduce acoustic signals into electrical signals, which are then converted to digital data by sensors systems 44 and 54. The data are then provided via a bus to a buffer 28 and received by a data receiver 30. The data receiver 30 then provides the data to a digital signal processor 32. [0058] Due to various system components, e.g., bus capacitances Cl and C2, buffer processing delays of buffers 46, 48, 56, 58 and 28, EMI protection components, etc., the data received from the devices 40 and 50 may not be synchronized with a data clock. This is illustrated in Fig. 2A, which is a timing diagram 60 illustrating the impact of clock delay when reading data.

[0059] As depicted in Fig. 2A. clock signals 62 and 64 have been delayed with respect to each other. This can be problematic, especially with a multi-channel input receiver. For example, when the data input is switching from channel 1 (device 40) to channel 2 (device 50), and vice versa, or when the data 66 are changing values, reading the data 66 at such points in time will result in invalid data reads. This is illustrated by read periods 68 during channel transitions, where the transmitter clock 62 is being used to read the data at a time coincident with channel changes.

[0060] Fig. 2B is a timing diagram 70 illustrating a proper adjustment for reading data. As depicted in Fig. 2B, the internal clock 72 and the received data 74 are aligned such that the read periods 78 occur when the signal levels are steady, resulting in valid data reads. The alignment of the clock 72 and data 74 can be realized by the systems and methods described below. This can be done by either adjusting the clock with respect to the data, or adjusting the data with respect to the clock.

[0061] Fig. 3 A is a block diagram of a delay selector 100 that determines a delay from processing input data. Example data generated and processed by the delay selector is illustrated in Fig. 3B, and an example process utilized by the delay selector is illustrated in Fig. 3C.

[0062] In operation, the delay selector 100 receives input data 102 and determines from the input data a respective delay of the input data relative to a clock. The delay selector 100 includes a clock stage 104 that generates a data clock signal based on a source clock signal. The data clock signal has a frequency that is normally lower than a frequency of the source clock signal. For example, the data clock signal frequency can be 1/N the system clock frequency, where N = 8, 12, 16, etc.

[0063] Both clocks and the input data 102 are provided to a stability detection stage 106. The stability detection stage 106 processes the input data at a frequency greater than the data clock signal to generate stability range data that is indicative of stability within the input data. In some implementations, stability is determined by a correlation operation that generates, based on input data received at the frequency of a data clock signal, correlation output data and a plurality of delayed instances of the correlation output data (Fig. 3C, 302). In particular, the stability detection stage 106 receives, as input, input data at the frequency of the data clock signal and correlates the input data with a delayed instance of the input data to generate correlation output data. In some implementations, the correlations are done at the source clock speed, e.g., at a rate of N times the data clock speed. Other rates of correlation can also be used, so long as there are multiple correlations done for each data clock cycle.

[0064] In the case of a correlation operation, the stability detection stage 106 then generates, as output, multiple delayed instances of correlation output data. Each delayed instance of the correlation output data is correlation output data delayed by a respective time delay. For example, each respective time delay may be a period of the source clock signal (or half period, or some other period that is less than the period of the data clock period, depending on the implementation).

[0065] For example, assume that the stability detection stage 106 operations an N times the frequency of the data clock signal. The stability⁷ detection stage 106 may generate up to N correlations of the input data for each data clock period, where each correlation is of the input data and a previously delayed instance of the input data. The stability detection stage may then store each of the N instances of correlations output data, where each delayed instance corresponds to a particular time delay At.

[0066] The delay selection stage 108 receives, as input, the delayed instances of the correlation output data and selects, based on the delayed instances of the correlation output data, selection data that corresponds to a particular time delay (Fig. 3C, 304). The selection data, for example, may be based on a number of positive instances detected within the correlation output data and the plurality of delayed instances of the correlation output data, as will be described in more detail below.

[0067] The output selection stage 110 receives, as input, the selection data from the delay selection stage 108. In response, the output selection stage 110 generates, as output, a delayed instance of the input data that is delayed by the particular time delay (Fig. 3C, 306). For example, if the selection data indicates a time delay of 4At, then the output data is the input data delayed by 4At.

[0068] The delayed instance can be generated in a variety of different ways. In one example implementation, the output selection stage 110 may generate (or receive, depending on the implementation), a plurality of delayed instances of the input data, where each delayed instance of the input data is delayed by a respective time delay, e.g., At (Fig. 3C, 308). The input data and the delayed instances may be provided to a multiplexor. Then, based on the selected particular time delay, the output selection stage 110 selects, as an output of the multiplexor, one of the input data or one of the plurality of delayed instances of the input data (Fig. 3C, 310).

[0069] In other implementations, the delay selector 100 may generate only one delayed instance of the input data, e g., by using a variable time delay circuit that is adjusted based on the selection data and either adjusts the sampling clock or the received data.

Moreover, while Fig. 3A depicts the output data output from the output selection stage 110, as described above, in another implementation, the clock can be adjusted by phase shifting, and the clock is output by the selection stage 110.

[0070] Fig. 3B is a timing diagram 200 illustrating correlation data for determining a timing delay. Given a clock 202, the input data 204 need to be delayed relative to the clock 202 for proper reading, or alternatively, the clock needs to be adjusted for unchanging data. The correlation data for each of channel 1 and 2 is shown as correlation data 206 and 208, respectively. The input data are sampled at a rate faster than the clock 202, e.g., each sample with a spacing of At, and correlated with an immediate previous input data sample. As shown, the correlation output data 206 and 208 have a subset of positive instances indicated by the open data circles. These positive instances are detected within the correlation output data by the delay selection stage 108 and used to select a time delay to delay the input data 204 relative to the clock 202, or alternatively, adjust the position of the phase of the sampling clock relative to the input data. As illustrated in Fig. 3A, the optimum sampling position can be a delay that is close to a center of the positive instances, e.g., approximately 4At. as indicated by the register data 210. The resulting selection data is then used by the output selection stage to generate the delayed version of the input data that is delayed by the particular time delay, i.e., 4At.

[0071] While the above example implementation describes a correlation operation for use in stability detection, other operations can also be used. For example, instead of a correlation operation, a difference amplifier can be used to determine a difference between two consecutive instances of the input signal. If the difference exceeds a threshold reference value, then a first value, e.g., a logic 0 value, indicating unstable data is generated. Conversely, if the difference does not exceed the threshold reference value, then a second value, e.g., a logic 1 value, indicating stable data is generated. Other circuits and processes that are appropriate for determining stability between a sample of input data and a prior delay instance of the input data can also be used. For the remainder of this specification, how ever, a correlation operation is described for determining stability'.

[0072] Figs. 4 - 7 below are example implementations of delay selectors. When appropriate, the description of similarly numbered elements in subsequent figures, e.g., MUX 432 in Fig. 4, MUX 532 in Fig. 5A, etc., may be omitted or abbreviated when the operations are as originally described or very' similar to the operations originally described. [0073] Fig. 4 is an example implementation of a delay selector 400 that determines a delay from processing input data. The clock stage 104 includes a divide by N processor to reduce a source clock signal 402 frequency by N to generate a data clock signal that is at a lower frequency than the source clock. A data clock delay block 406, which in this example is realized by two sequential D-type flip-flops that are driven at the source clock signal frequency, can be used to delay the data clock signal. This delay block 406 is optional, and can be used for “negative shifting’⁷ of the data signal should such capability be desired or required. However, the delay selector 100 need not have a data clock delay block 406 to operate.

[0074] The stability detection stage 106 receives, as input, input data at the frequency of the data clock signal. The stability detection stage 106 then correlates the input data with a delayed instance of the input data to generate correlation output data. This correlation operation is repeated at a higher frequency than the data clock rate, e.g., it is repeated at the source clock 402 frequency. The correlation output data are provided to delays to generate multiple delayed instances of correlation output data. Each delayed instance of the correlation output data is correlation output data delayed by a respective time delay.

[0075] In an example implementation, the stability' detection stage 106 includes a correlation circuit 410 and a delay stage 412. The correlation circuit 410 is. in this example, an exclusive OR gate that receives, as input, the input data and a delayed instance of the input data. A D-type flip flop is used to create the delayed instance of the input data. Here, the correlation output data is the output of the exclusive OR gate. The delay stage 430 is a series of cascaded D-type flip flops, with each output connected as in input to a subsequent D-type flip flop. The delay stage 412 is driven at the source clock signal 412 frequency.

[0076] After each correlation, the correlation output data, which is, in this example, either a 1 or a 0, is provided to the delay stage 412. After a series of correlations, e.g., N, the correlation output data are sequentially captured in the delay stage, with the right most D-type flip flop storing the most delayed correlation output data, and the left most D-type flip flop storing the most recent correlation output data. More succinctly, the delay stage 412 receives the correlation output data and generates, as output, the plurality of delayed instances of the correlation output data. [0077] The delay selection stage 108 receives, as input, the plurality of delayed instances of the correlation output data (and, in this example, a most recent correlation output that is not delayed by a D-type flip flop) from the stability detection stage 106. The delay selection stage 108 receives the delayed instances of the correlation output data according to the data clock, which is operating at 1/N the frequency of the system clock. Based on this data, the delay selection stage 108 generates selection data that corresponds to a particular time delay.

[0078] In an example implementation, the delay selection stage 108 includes a storage circuit that stores data based on the correlation output data and the delayed instances of the correlation output data. For example, the storage circuit includes a N bit register 420 and a series of set/reset flip flops 422, where each set/reset flip flop corresponds to a respective time delay. The register 420 is driven at the data clock frequency, and provides its output to the series of set/reset flip flops 422. In some implementations, the register 420 provides an output for each N correlations.

[0079] At the start of a calibration process, the selection processor 424 is reset and the set/reset flip flops 422 are set. Thereafter, the multiple delayed instances of correlation output data are generated, and the values are captured at the same time in the register 420. The set/reset flip flops 422 provide a capture history’. When two different values are compared by the XOR gate inside 410, the result is a logic high output value that will reset the set/reset flip flop inside 422. Thus, the output from any individual set/reset flip flop will then be 0 to indicate a negative correlation value, i.e., the correlation output data for that particular time delay indicates unreliable data.

[0080] The selection processor 424 reads the values of the set/reset flip flops 422, and, based on the correlation output data and the delayed instances of the correlation output data, generate selection data that corresponds to the particular time delay for which the input data can be read reliably. In Fig. 4, the selection is of a delayed version of the input data so it better aligns with the sampling clock. An alternative is a phase-adjusted version of the sampling clock to account for the optimal sampling point for the data, which will be described later in Fig. 13. The selection processor 424 can be any device that can be programmed or configured to perform the selection operation as described above. It can be a discrete digital circuit, or a processor programmed to read the values output by the set/reset flip flops 422 to determine the selection data. Multiple clock cycles, e.g., a few hundred, for example, may be required for reliable detection of the optimal sampling point.

[0081] In some implementations, the selection processor 424 can process a single register of data to generate the selection data. In other implementations, the selection processor 424 can read multiple instances of register data, e.g., M instances. In still other implementations, the selection processor 424 can read multiple instances of register data and generate the selection data after a stability condition is met. e.g., where, for each register of data, a same time delay is selected, or a set of time delays within a stable condition (e.g., with two or three time delay values) are selected.

[0082] In some implementations, the selection processor 424 can generate the selection data based on a plurality of delayed instances of the correlation output data being a same value that indicate positive instances of output correlation data. The selection data specifies a respective time delay of one of the respective time delays of the delayed instances of the correlation output data that indicate the positive instances. For example, with reference to Fig. 3B, the selection data will indicate a time delay corresponding to one of the four positive instances of correlation data indicated by the open data circles.

[0083] The output selection stage 110 receives, as input, the selection data from the delay selection stage 108, and in response, generates, as output, a delayed instance of the input data that is delayed by the particular time delay. For example, if the selection data indicates an optimal time delay of 4At, then the output data is the input data delayed by 4At, which corresponds to a selected channel in the multiplexor 432.

[0084] In some implementations, the output stage 110 includes a second delay stage 430 that receives, as input, the input data at the frequency of the data clock signal and generates, as output, multiple delayed instances of the input data. The delay stage 430 can be a series of cascaded D-type flip flops, with each output connected as in input to a subsequent D-type flip flop. The delay stage 430 is driven at the source clock signal 402 frequency.

[0085] The selection data is used as a multiplexor channel selection, and the channel that is selected is the channel with the input data delayed by the respective time delay specified by the selection data. An optional output register 434 can also be used for final synchronization before outputting the output data, where the register is driven at the system clock frequency. [0086] As indicated by the “start calibration” signal, the selection processor 424 initializes the flip-flops 422 by setting them to a logical 1 and performs the calibration operation to select the appropriate time delay. After the calibration, the selection processor 424 provides the selection data to the output selection stage 110, which, in turn, continues to output the selected delayed instance of the input data until another calibration operation is run.

[0087] The delay selector of Fig. 4 can perform measurements and calibration at the same time. In another implementation, the delay selector can either perform measurements or calibration, but not both at the same time. It may also use both clock edges for higher temporal precision. Fig. 5A is another example implementation of a delay selector 500 that determines a delay from processing input data, and performs the aforementioned operations. This has the advantage of a higher temporal resolution and only using a single delay line 512.

[0088] As illustrated in Fig. 4, D-type flip-flops 411 and 431 output the same data Q. Accordingly, the flip-flop 431 can be omitted, and the output Q of the flip flop 411 can be provided to the multiplexor 432 in place of the output of the omitted flip-flop 431. Flip flop 431 has been maintained in the figure for easier readability.

[0089] In Fig. 5A, the stability detection stage 106 and the output stage 110 differ from those in the example implementation of Fig. 4. In particular, in Fig. 5A, the stability detection stage 106 is a dual-mode correlation and delay stage that includes a correlation circuit 510 and a dual-mode delay stage 512. The correlation circuit 510 receives, as input, the input data at the frequency of the data clock signal. In a first mode, the correlation circuit 510 passes the input data to the dual-mode delay-stage 512 by means of the switch 514. This mode, referred to as the data mode, is used when a time delay has been selected for the input data.

[0090] The dual -mode delay stage 512 has a series of D-type flip flops, half of which are clocked on a falling edge of the system clock, and the other half of which are clocked on the rising edge of the system clock. This allows for greater precision compared to only clocking data on just the rising edge of a clock. When a time delay has been selected in response to previously operating in the calibration mode, the multiplexor 532 outputs the selected instance of the input data that is input on the channel corresponding to the selected time delay. The multiplexor 532 continues to output the selected delayed instance of the input data until another calibration operation is performed. [0091] Before calibration, set/reset flip-flops 522 are initialized to zero. During calibration, the switch 514 is switched to the calibration position by the ‘"start calibration" signal, which also starts the calibration process by the selection processor 524. In response, the correlation circuit 510 provides correlation output data that are correlations of the input data to the dual-mode delay stage 512. As indicated by the D-type flip flops outputs that provide input to the exclusive OR gate, a correlation of the input data and a delayed instance of the input data occurs at each rising edge and falling edge of the system clock depending on the position of switch 514. In other words, a single error (difference between two data values read) will be detected and kept by the set/reset flipflops 522, while no error will result in no change of state.

[0092] The delay selection stage 108 of Fig. 5 A operates in a manner similar to the delay selection stage of Fig. 4. However, the selection processor 524 can also be programmed to cause the switch 514 to revert back to the data mode position when the selection processor 524 generates the selection data and provides the selection data to the multiplexor 532.

[0093] Another difference in the implementation of Fig. 5 A from the implementation of Fig. 4 is that output selection stage 110 need not include a data delay stage, as the delay stage 512 provides either delayed correlation output data or delayed input data, depending on the operating mode. Register 534, which is optional, may be included for timing improvement purposes.

[0094] Fig. 5B is another example implementation of a delay selection stage 108 that can be used with the example implementation of Fig. 5 A. In Fig. 5B, counters are used to receive the output of the register 520 instead of the set/reset flip flops. The counters thus accumulate the values of the respectively delayed instances of the correlated output data that are stored in the register 520. In Fig. 5B, ‘'RS’’ means “reset counter’’, “IN” means “increment counter” or “counter input” and “COUNT” means the value of the counter. The accumulations result in a more refined selection of the appropriate time delay, as the accumulation will have a highest value near or at the time delays with the most detections of positive instances of correlation output data. Thus, with the show n configuration of Fig. 5B, the counter values indicate the number of errors (mismatches) between two successive data samples. If an exclusive NOR gate was used instead for comparison unit preceding selector 514, the counters would count the number of valid data encountered in a given delay position. [0095] The selection processor 524 generates the selection data based on the respectively accumulated delayed instances of the correlation output data. In some implementations, the selection processor 524 is configured or programmed such that the selection data specifies a respective time delay for the correlation output data that has a lowest accumulated value relative to the other respectively accumulated delayed instances of the correlation output data.

[0096] Fig. 6A is another example implementation of a delay selector 600 that determines a delay from processing input data. Fig. 6B is an example timing diagram 650 of phase signals for the example implementation of Fig. 6A.

[0097] In Fig. 6A, the output selection stage 110 operates in similar manner to the output selection stage 110 of Fig. 5A, and is realized by a multiplexor 632. The implementation of Fig. 6A has the advantage that there is no need for a higher speed clock to perform the time shifting. Instead, a DLL 602 is included to obtain a multi-phase clock. This is then used to obtain multiple timing events. This can, in some instances, result in a lower power consumption since there is no need for a higher speed system clock. The optional output delay is not included in this implementation. Likewise, the selection stage 108 operates in a manner similar to the selection stage 108 of Fig. 4.

[0098] The delay selector 600 includes a DLL 602 with a multiphase output that generates the output phase signals based on the input clock, as show in Fig. 6B. The stability detection stage 106. however, differs from the previously described examples in that it includes a delay stage 612 that receives, as input, the input data at the frequency of the data clock signal and generates, as output, delayed instances of the input data. Again, each delayed instance of the input data is the input data delayed by a respective time delay. More specifically, the delay stage 612 is a set of digital delays, e.g., D-type flip flops, and each delay is driven by a respectively phase output of the DLL 602.

[0099] The delayed instances of the input data are provided to both the multiplexor 632 of the output selections stage 110 and a correlation circuit 610 of the stability detection stage 106. The correlation circuit 610 is, in this example, a series of exclusive OR gates that each receive respectively paired instances of the input data, where each paired instance is a respective instance of the input data and an instance delayed by one time delay. The correlated output data that is generated is then provided to the register 620, and the delay selector 108 then operates in a manner as previously described with reference to Figs. 4 and 5 A. [00100] Fig. 7 is another example implementation of a delay selector 700 that determines a delay from processing input data. In Fig. 7. the output selection stage 110 operates in similar manner to the output selection stage 110 of Fig. 5 A, and is realized by a multiplexor 732. Likewise, the selection stage 108 operates in a manner similar to the selection stage 108 of Fig. 4. The implementation of Fig. 7 has the same advantage as the implementation of Fig. 6A in that no oversampled (faster) clock is required for operation.

[00101] The stability detection stage 106. however, includes a delay stage 712 made up of analog delay stages, e.g., analog delay cells. The delay stage 712 receives, as input, the input data at the frequency of the data clock signal and generates, as output, delayed instances of the input data. Again, each delayed instance of the input data is the input data delayed by a respective time delay. Absolute accuracy of the delay in each analog delay cell is not critical, as long as the entire delay line formed by the delay stage 712 covers the range needed for adjustment, e.g., one half (or more) of the data clock period.

[00102] The correlation circuit 710 is, in this example, a series of exclusive OR gates that each receive respectively paired instances of the input data, where each paired instance is a respective instance of the input data and an instance delayed by one time delay. The correlated output data that is generated is then provided to the register 720, and the delay selector 108 then operates in a manner as previously described with reference to Figs. 4 and 5 A.

[00103] Fig. 7 also includes an optional selectable delay 740 that can be used to compensate for overall system latency. An optional selectable delay 740 can also be used in the other implementations described above.

[00104] Fig. 8 is a flow diagram of another example process 800 for determining a timing delay. The process can be implemented in the delay selector 100 of Fig. 3A. [00105] The process 800 starts a calibration process (802). For example, the delay selector 100 enters a mode to begin calibration. The mode can be entered during a startup process, at a user request, or based on some other event.

[00106] The process 800 enables traffic on the data bus (804). For example, the delay selector 100 enables the reception of data for processing.

[00107] The process 800 waits for data traffic to be stable (806). For example, the delay selector 100 may wait a fixed amount of time, e.g., 50 milliseconds, or may use some other process to ensure that data are being received. [00108] The process 800 resets counters and transition checkers (808). For example, the delay selector 100 resets the registers, flops, and processors.

[00109] The process 800 waits for M clock period (810). For example, the delay selector 100 may process data for M data clock periods, e.g., 1000 clock periods, or some other number of clock periods. In some implementations, M can be as low as 1 clock period.

[00110] The process 800 determines whether enough positive instances are detected (812). For example, the delay selector 100 may determine, in the delay selection stage, whether positive instances of correlations are detected. In some implementations, the selection processor can process a single register of data to generate the selection data and look for at least one positive instance. In other implementations, the selection processor can read multiple instances of register data, e.g., K instances, and look for at least one positive instance, e.g., stable data, in each register of data. In still other implementations, the selection processor can read multiple instances of register data and generate the selection data after a stability- condition is met, e.g., where, for each register of data, a same time delay is selected, or a set of time delays within a stable condition (e.g., with two or three time delay values) are selected.

[00111] If enough positive instances are not determined, the process 800 returns to step 812. Conversely, if enough positive instances are determined, the process 800 sets an optimal delay value (814). For example, the delay value may be set to about the middle of the positive instances. This ensures that data are captured near the center of the data eye. For example, the delay selection stage generates selection data, and provides the selection data to the output selection stage.

[00112] The process 800 indicates sensor data are now valid (816). For example, the delay selector 100 may generate a data signal that indicates an appropriate time delay has been selected.

[00113] The process 800 determines the calibration is complete (818). For example, the delay selector 100 may continue to output data at the selected time delay until another a calibration is performed.

[00114] The example implementations above are illustrative only, and the delay selector can be used in other systems, such as TDM systems, PDM systems, and PWM systems, for example. [00115] Fig. 9A is a block diagram of a time division multiplexing system 900 that uses the delay selector 100 to realize automatic data adjustment. The system 900 includes a data processor 920 that communicates with three devices 940, 950 and 960 through a TDM protocol. The processor 920 includes a clock 922 and buffer 924 that outputs a system clock.

[00116] Data are received over the TDI input and buffer 928, and processed by the data receiver 930 and the DSP 932. Likewise, output data (TDO) generated by the DSP 932 are provided to the transmitter 934 and output via the buffer 936. A frame sync generator 938 generates a frame sync for the three devices 940, 950 and 960.

[00117] Components 940. 950 and 960 each have devices 942, 952 and 962 for outputting or receiving data. Components 940 and 950 also have respective sensor systems 944 and 954 and buffers 946, 948, 956, and 958 for clocking and receiving and processing data. Component 960 has a delay select 970 for outputting the data via the data receiver 966 and the devices 964 and 962. Component 960 also has buffer devices 968 and 972.

[00118] As can be appreciated from the system diagram, the TDM system 900 may have latencies for which a delay adjustment is needed. The TDM timing diagram 980 of Fig. 9B illustrates one example of proper delay adjustment resulting from use of the delay selector 100. The clock signal 982 from clock 922 is provided to the components 940, 950 and 960. as is the frame sync signal 984. By the delay selector 100 detecting when the data for particular TD11 and TDI2 are stable, the TDI1 data 986 and TD12 data 988 can be delayed accordingly, as indicated by the horizontal arrows. Similarly, Select Delay 970 (Fig. 9A) can detect when TDO 990 data is stable and delay received TDO samples accordingly. In this example, the data 968, 988 and 990 are aligned relative to the frame sync signal 984 and clock 982, though the internal clock in component 960 may have a clock reference that is delayed as compared to main external clock 982.

[00119] Fig. 10 is a timing diagram 1000 for a multi-bit pulse density modulation (PDM) system. A clock signal 1002 is used as the timing reference for alignment of data 1004 from multiple sensors, e.g., sensor 1 and sensor 2. In this example, the data from each sensor are three bit values, separated by a tri-state condition to avoid data collision. Again, the delay selector 100 can process the data to determine when stability occurs, and thus ensure optimal alignment. [00120] Fig. 11 is a timing diagram 1100 for a stereo pulse width modulation (PWM) system. Here, the width of the signals is used as symbols to communicate a value. The clock signal 1102 is used as the timing reference for alignment of data 1104 from multiple sensors, e.g., sensor 1 and sensor 2. The alignment may be selected by the data selector 100 such that the signals, defined by their pulse width, begin at an appropriate sample time with respect to the clock 1102. A tri-state period is used for handover when switching between two or more data sources as shown on Fig. 11 with dashed lines on the data line 1104. It can be seen, that every signaling value only involves a single change of the data line, thereby enabling low power communication by transferring multiple bits or a variable value using a single data bus line change. In some configurations, Sensor 1 and Sensor 2 may be the same component.

[00121] Likewise, Fig. 12 is a timing diagram 1200 of a mono PWM system. Here, a clock signal 1202 is used as the reference for alignment of data 1204 from a single sensor, sensor 1. Again, the alignment may be selected by the delay selector 100 such that the signal, defined by its pulse width, beings at an appropriate sample time with respect to the clock 1102. It can be seen that this is also a low power signaling system, since all transferred values are communicated using a single change of the data line, even though each value may be comprised of multiple bits or indicate an analog signal value.

[00122] While the examples above have described generating delayed data signals, the systems and methods can also generate a phase shifted data clock to accomplish the same advantage. One such example implementation is shown in Fig. 13, which illustrates a delay selector 1300 that determines a delay to phase shift a clock relative to the input data.

[00123] The delay selector 1300 of Fig. 13 operates in a manner similar to the delay selector 400 of Fig. 4 in some respects. For example, elements 402, 404, 406, 410, 412, 420, 422, 424, 430, and 432 and elements 1302, 1304, 1306, 1310, 1312, 1320, 1322, 1324, 1330, and 1332 perform similar operations. However, in Fig. 13, instead of the input data being provided to the delay stage 1330, the data clock is provided to the delay stage 1330. The selection processor 1324 reads the values of the set/reset flip flops 1322. and, based on the correlation output data and the delayed instances of the correlation output data, generates selection data that corresponds to the particular time delay for which the input data can be read reliably by phase shifting the data clock. [00124] The output selection stage 110 receives, as input, the selection data from the delay selection stage 108, and in response, generates, as output, a phase-shifted version of the data clock that is phase shifted by the particular time delay. For example, if the selection data indicates an optimal time delay of 4At, then the data clock is phase shifted by 4At, which corresponds to a selected channel in the multiplexor 1332. Output stages 1334 and 1335 are used to generate signals that allow for clocking on both edges of the data clock for multiple channels.

[00125] Embodiments of the subject matter and the operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on computer storage medium for execution by, or to control the operation of, data processing apparatus.

[00126] A computer storage medium can be, or be included in, a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination of one or more of them. Moreover, while a computer storage medium is not a propagated signal, a computer storage medium can be a source or destination of computer program instructions encoded in an artificially-generated propagated signal. The computer storage medium can also be, or be included in, one or more separate physical components or media.

[00127] The operations described in this specification can be implemented as operations performed by a data processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

[00128] The term "‘data processing apparatus’’ encompasses all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, a system on a chip, or multiple ones, or combinations, of the foregoing. The apparatus can include special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). The apparatus can also include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, a cross- platform runtime environment, a virtual machine, or a combination of one or more of them. The apparatus and execution environment can realize various different computing model infrastructures, such as web services, distributed computing and grid computing infrastructures.

[00129] The processes and logic flows described in this specification can, where appropriate, be performed by one or more programmable processors executing one or more computer programs to perform actions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., a FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

[00130] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any features or of what may be claimed, but rather as descriptions of features specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[00131] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[00132] Thus, particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

Claims

CLAIMS What is claimed is:

1. An apparatus in a data processing system, comprising: a stability detection stage that receives, as input, input data at a frequency of a data clock signal and processes the input data at a different frequency rate than the data clock signal and generates stabi 1 i ty range data that is indicative of stability within the input data; a delay selection stage that receives, as input, the stability range data and generates, based on the stability range data, selection data that corresponds to a particular time delay that corresponds to a time at which the input data is stable; and an output selection stage that receives, as input, the selection data and, in response, generates, as output, one of a delayed version of the input data or data clock signal that is delayed by the particular time delay.

2. The apparatus of claim 1, wherein: the stability' detection stage comprises a correlation stage that receives, as input, the input data at the frequency of the data clock signal and correlates the input data with a delayed instance of the input data to generate correlation output data and generates, as output, a plurality of delayed instances of correlation output data, each delayed instance of the correlation output data being correlation output data delayed by a respective time delay; and the delay selection stage receives, as input the plurality of delayed instances of the correlation output data and generates, based on the delayed instances of the correlation output data, the selection data that corresponds to the particular time delay.

3. The apparatus of claim 2, wherein the correlation stage comprises: a correlation circuit that receives, as input, the input data at the frequency of the data clock signal and correlates the input data with the delayed instance of the input data to generate the correlation output data; and a first delay stage that receives, as input, the correlation output data and generates, as output, the plurality of delayed instances of the correlation output data.

4. The apparatus of claim 3, wherein the delay selection stage comprises: a storage circuit that stores data based on the correlation output data and the delayed instances of the correlation output data; and a selection processor that generates, based on the correlation output data and the delayed instances of the correlation output data, the selection data that corresponds to the particular time delay.

5. The apparatus of claim 4, wherein the selection processor generates the selection data based on a plurality of delayed instances of the correlation output data being a same value, and wherein the selection data specifies a respective time delay of one of the respective time delays of the plurality of delayed instances of the correlation output data that are of the same value.

6. The apparatus of claim 4, wherein the storage circuit comprises a plurality of set/reset flip flops, wherein each set/reset flip flop corresponds to a respective time delay.

7. The apparatus of claim 6, wherein the selection processor generates the selection data based on the output of the set/reset flip-flops indicating a stable data value, and wherein the selection data specifies a respective time delay of one of the respective time delays of the plurality of set/reset flip-flops.

8. The apparatus of claim 1, wherein the output selection stage comprises a multiplexor that receives, as input, the input data and a plurality of delayed instances of the input data, each delayed instance of the input data being the input data delayed by a respective time delay, and, based on the selection data received from the delay selection stage, selects one the input data or one of the plurality of delayed instances of the input data as output.

9. The apparatus of claim 8, wherein the output selection stage further comprising a second delay stage that receives, as input, the input data at the frequency of the data clock signal and generates, as output, the plurality of delayed instances of the input data.

10. The apparatus of claim 2, wherein the correlation stage comprises a dual-mode correlation and delay stage, comprising: a correlation circuit that receives, as input, the input data at the frequency of the data clock signal and correlates the input data with a delayed instance of the input data to generate correlation output data; a dual-mode delay stage that operates in a first mode and a second mode, wherein: in the first mode, the dual mode delay stage receives, as input, the correlation output data and generates, as output, the plurality of delayed instances of the correlation output data; and in the second mode, the dual mode delay stage receives, as input, the input data at the frequency of the data clock signal and generates, as output, a plurality of delayed instances of the input data, each delayed instance of the input data being the input data delayed by a respective time delay.

11. The apparatus of claim 10, wherein the delay selection stage comprises: a storage circuit that stores data based on the correlation output data and the delayed instances of the correlation output data; and a selection processor that generates, based on the correlation output data and the delayed instances of the correlation output data, the selection data that corresponds to the particular time delay.

12. The apparatus of claim 11, wherein the selection processor generates the selection data based on a plurality of delayed instances of the correlation output indicating data being of the same value, and wherein the selection data is specified by one of the respective time delays of the plurality of delayed instances of the correlation output data that are of the same value.

13. The apparatus of claim 11, wherein the selection processor generates the selection data based on a plurality of respectively accumulated delayed instances of the correlation output data, and wherein the selection data specifies a respective time delay of one of the respective time delays of one of the respectively accumulated delayed instances of the correlation output data.

14. The apparatus of claim 13, wherein the selection processor generates the selection data based on a respectively accumulated delayed instances of the correlation output data that has a highest accumulated value relative to the other respectively accumulated delayed instances of the correlation output data.

15. The apparatus of claim 1, wherein the output selection stage comprises a multiplexor that receives, as input, the input data and a plurality of delayed instances of the input data, each delayed instance of the input data being a delayed by a respective time delay, and, based on the selection data received from the delay selection stage, selects one the input data or one of the plurality of delayed instances of the input data as output.

16. The apparatus of claim 2, wherein the correlation stage comprises: a first delay stage that receives, as input, the input data at the frequency of the data clock signal and generates, as output, a plurality of delayed instances of the input data, each delayed instance of the input data being a delayed instance of the input data delayed by a respective time delay; and a correlation circuit that receives, as input, the delayed instances of the input and generates, as output the plurality of delayed instances of the correlation output data.

17. The apparatus of claim 1 , wherein the first delay stage comprises a plurality of analog delay stages.

18. The apparatus of claim 16, wherein the first delay stage comprises a plurality of digital delays, and each digital delay is driven by a respectively phase output of a delay locked loop multi-phase clock generator that is driven by a source clock signal.

19. A method implemented in a data processing apparatus, the method comprising the operations of: generating, based on input data received at a frequency of a data clock signal, stability detection stage that receives, as input, input data at the frequency of the data clock signal and processes the input data at a rate greater than the data clock signal to generate stability range data that is indicative of stability within the input data; selecting, based on the stability range data, a particular time delay, the particular time delay being a time delay that corresponds to a time at which the input data is stable; and generating, as output, one of a delayed version of the input data or data clock signal that is delayed by the particular time delay.

20. The method of claim 19, wherein generating one of a delayed version of the input data or data clock signal that is delayed by the particular time delay comprises: generating, based on the input data received at a frequency of a data clock signal, a plurality of delayed instances of the input data, each delayed instance of the input data being delayed by a respective time delay; and based on the selected particular time delay, selecting, as an output, one of the input data or one of the plurality of delayed instances of the input data.

21. The method of claim 19, wherein: the stability range data comprises correlation output data and a plurality of delayed instances of the correlation output data, wherein each correlation output data is a correlation of the input data with a delayed instance of the input data delayed by a respective time delay; and selecting, based on the stability data, the particular time delay comprises selecting a time delay that corresponds to a plurality of positive instances detected within the correlation output data and the plurality of delayed instances of the correlation output data.

22. The method of claim 20, wherein selecting a particular time delay comprises: generating a plurality of respectively accumulated delayed instances of the correlation output data; and generating the selection data based on a respectively accumulated delayed instances of the correlation output data that has a highest accumulated value relative to the other respectively accumulated values.

23. The method of claim 19, wherein selecting a particular time delay comprises: determining consecutive portions of the plurality' of delayed instances of the correlation output data of indicating a stable data value; and selecting a respective time delay of one of the respective time delays of the plurality of delayed instances of the correlation output data that are indicating a stable data value.