WO2026001700A1 - Host backplane and valve control apparatus - Google Patents

Abstract

The present application belongs to the technical field of power distribution control. Provided are a host backplane (10) and a valve control apparatus. The host backplane (10) comprises a circuit substrate (100), the circuit substrate (100) being provided with at least two CPU board connectors (111, 112) and a plurality of interface board connectors (121-124), wherein different CPU board connectors (111/112) and the same interface board connector (121/122/123/124) are connected by means of signal transceiving lines of the same length (130). The signal transceiving lines (130) between different CPU board connectors (111, 112) and the same interface board connector (121/122/123/124) are set to have the same length, and thus synchronous reception/transmission of the communication between different CPU boards and the same interface board is achieved, timing consistency is maintained, and the requirement of realizing synchronous communication as much as possible is met. In addition, since there are signal transceiving lines (130) between different CPU board connectors (111/112) and the same interface board connector (121/122/123/124), effective communication can still be maintained in the case of a failure of a single signal transceiving line (130), thereby improving the reliability of the system.

Description

Main unit backplane and valve control device

This application claims priority to Chinese Patent Application No. 202421525216.5, filed on June 28, 2024, with the State Intellectual Property Office of the People's Republic of China, entitled "Main Unit Backplane and Valve Control Device", the entire contents of which are incorporated herein by reference.

Technical Field

This application belongs to the field of power distribution control technology, and in particular relates to a host backplane and valve control device.

Background Technology

High-voltage direct-connected energy storage valve control devices are an important hub between DC control protection and energy storage valve sub-modules. The controller of the valve control device communicates with the interface (i.e., I/O port) board via a low-voltage differential signaling (LVDS) bus. However, the current communication between the controller and the interface board cannot meet the requirement of synchronous communication as much as possible.

Application content

In view of the above problems, this application provides a host backplane and valve control system for valve control device, which aims to solve the problem that the communication between the controller and the interface board of the valve control device cannot meet the requirement of synchronous communication as much as possible.

In a first aspect, embodiments of this application provide a host backplane, including a circuit board, on which at least two CPU board connectors and multiple interface board connectors are provided;

Among them, different CPU board connectors are connected to signal transceiver lines of equal length to the same interface board connector.

In the technical solutions of this application, by setting the signal transceiver lines of different CPU board connectors and the same interface board connector to be of equal length, the communication between different CPU boards and the same interface board can be received/delivered as synchronously as possible, maintaining timing consistency and meeting the requirement of synchronous communication as much as possible, thereby satisfying higher-speed communication. In some embodiments, both different CPU board connectors and the same interface board connector have signal transceiver lines, which can maintain effective communication even when a single signal transceiver line fails, improving the reliability of the system.

In some embodiments, equal-length signal transceiver lines include equal-length signal transmitting lines and equal-length signal receiving lines.

In the technical solution of this application embodiment, the signal transceiver lines of equal length between different CPU board connectors and the same interface board connector are composed of mutually independent signal transmission lines and signal reception lines, which can realize low power consumption and low bit error rate serial communication.

In some embodiments, the signal transceiver line includes copper plating disposed on a circuit board. This application provides an implementation method for a signal transceiver line.

In some embodiments, copper cladding includes bent traces.

In the technical solution of this application embodiment, copper plating with bent traces is used on the circuit board to arrange signal transmission lines and signal reception lines of equal length, saving space on the circuit board.

In some embodiments, there is a gap between the bent trace and the CPU board connector and the interface board connector. During communication, this reduces interference between the bent trace and the CPU board connector and the interface board connector, thereby improving communication reliability.

In some embodiments, the signal transceiver line includes a connecting cable that is connected to the circuit board.

In the technical solution of this application embodiment, another implementation method for signal transceiver lines is provided.

In some embodiments, the signal transmitting line includes a pair of differential signal transmitting lines, and the signal receiving line includes a pair of differential signal receiving lines.

The technical solution of this application embodiment provides a signal transmission line communication method for low voltage differential signals.

In some embodiments, two CPU board connectors are included.

In the technical solution of this application embodiment, a host backplane with dual CPU boards is provided, which provides sufficient computing power and reliability.

In some embodiments, two CPU board connectors are arranged in the middle area of the circuit board.

In the technical solution of this application embodiment, it is advantageous to arrange the signal transceiver lines of the CPU board connector to the interface board connectors on opposite sides or around it as equal in length.

In some embodiments, multiple interface board connectors are distributed on opposite sides or around the two CPU board connectors.

In the technical solution of this application embodiment, the symmetrical structural layout can meet the requirement that the CPU board or interface board can be interchanged at any time, improve the redundancy of the system, and facilitate the arrangement of the signal transmission and reception lines of the CPU board connector to the interface board connectors on the opposite sides or around it as equal in length.

In some embodiments, the distance between the edges of two CPU board connectors is greater than the distance between the edges of two adjacent interface board connectors.

In the technical solution of this application embodiment, the CPU board heat dissipation is facilitated by the CPU board connector insertion.

In some embodiments, two sets of redundant signal lines are connected between the CPU board connectors.

In the technical solution of this application embodiment, the communication reliability of the CPU boards connected to each CPU board connector is improved.

Secondly, embodiments of this application provide a valve control device, including the host backplane as described above, two CPU boards and at least one interface board, wherein the two CPU boards are respectively connected to the two CPU board connectors of the host backplane, and the interface board is connected to the interface board connector of the host backplane.

In the technical solution of this application embodiment, the host backplane of the valve control device sets the signal transceiver lines of different CPU board connectors and the same interface board connector to be of equal length, which can make the communication between different CPU boards and the same interface board as synchronous as possible, maintain timing consistency, achieve the requirement of synchronous communication as much as possible, and improve the reliability of the valve control device.

The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application.

Attached Figure Description

Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiments below. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

Figure 1 shows a schematic diagram of the structure of a host backplane provided in an embodiment of this application;

Figure 2 shows a schematic diagram of the circuit board structure of a host backplane provided in an embodiment of this application;

Figure 3 shows a schematic diagram of the circuit board structure of a host backplane provided in an embodiment of this application.

Detailed Implementation

The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

In the description of the embodiments in this application, the term "and/or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and/or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character "/" in this document generally indicates that the preceding and following related objects have an "or" relationship.

In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

According to some embodiments of this application, referring to FIG1, FIG1 shows a schematic diagram of the structure of a host backplane provided in an embodiment of this application. For ease of explanation, only the parts related to this embodiment are shown, which are described in detail below:

The main backplane 10 can be applied to a high-voltage direct-connected energy storage valve control device (hereinafter referred to as the valve control device), which is an important hub between DC control protection and energy storage valve submodules. The main backplane 10 includes a circuit board 100, on which at least two central processing unit (CPU) board connectors 111 and 112 and multiple interface board connectors 121 to 124 are provided; wherein, different CPU board connectors 111 and 112 are connected to the same interface board connectors 121/122/123/124 with signal transceiver lines 130 of equal length.

The circuit board 100 is generally a conventional printed circuit board (PCB). The CPU board is a control board or communication board used to install the CPU, and the CPU board connector 111 is used to plug into the CPU board. Figure 1 shows four interface board connectors: interface board connector 121, interface board connector 122, interface board connector 123, and interface board connector 124. Interface board connectors 121-124 use fiber optic communication to control and protect the energy storage valves of the energy storage submodule, providing reliable communication control for the energy storage submodule.

In the technical solution of this application embodiment, by setting the signal transceiver lines 130 of different CPU board connectors 111, 112 and the same interface board connector 121/122/123/124 to the same length, the communication between different CPU boards and the same interface board can be received/delivered as synchronously as possible, maintaining timing consistency and meeting the requirement of synchronous communication as much as possible, thereby satisfying higher speed communication. The signal transceiver line 130 can be a line for serial communication or parallel communication.

In some embodiments, different CPU board connectors 111, 112 and the same interface board connectors 121/122/123/124 all have signal transceiver lines 130, which can maintain effective communication even when a single signal transceiver line 130 fails, thereby improving the reliability of the system.

The signal transceiver line 130 includes a signal transmitting line and a signal receiving line.

In some embodiments, the signal transmission line and signal reception line connected to a CPU board connector and an interface board connector are the same wire. In this case, the signal transmission lines and signal reception lines connected to different CPU board connectors 111, 112 and the same interface board connector 121/122/123/124 are all of equal length.

According to some embodiments of this application, referring to Figures 2 and 3, Figure 2 shows a schematic diagram of the structure of a host backplane provided in an embodiment of this application, and Figure 3 shows a schematic diagram of the structure of a host backplane provided in an embodiment of this application. For ease of explanation, only the parts related to this embodiment are shown, and the details are as follows:

In some embodiments, the signal transmission lines and signal reception lines connecting a CPU board connector and an interface board connector are different wires. For example, the equal-length signal transceiver lines 130 include equal-length signal transmission lines TX1-TX4 and equal-length signal reception lines RX1-RX4. This ensures that communication between CPU boards connected to different CPU board connectors 111 and 112 and interface boards connected to the same interface board connector 121/122/123/124 is as synchronized as possible, maintaining consistent timing. In some embodiments, the equal-length signal transceiver lines 130 are composed of mutually independent signal transmission lines TX1-TX4 and signal reception lines RX1-RX4, enabling low-power, low-error-rate serial communication.

According to some embodiments of this application, referring to Figures 2 and 3, the signal transceiver line 130 includes copper plating disposed on the circuit board 100. This copper plating refers to the copper plating on the PCB board, and can be composed of straight copper plating and/or bent copper plating. According to some embodiments of this application, the copper plating includes bent traces.

As shown in Figure 2, signal transmission line TX1 connects CPU board connector 111 and interface board connector 121, and signal transmission line TX2 connects CPU board connector 112 and interface board connector 121. Signal transmission lines TX1 and TX2 are of equal length. Signal reception line RX1 connects CPU board connector 111 and interface board connector 121, and signal reception line RX2 connects CPU board connector 112 and interface board connector 121. Signal transmission lines RX1 and RX2 are of equal length.

The distance between CPU board connector 111 and interface board connector 121 is less than the distance between CPU board connector 112 and interface board connector 121. Therefore, in order to make signal transmission line TX1 and signal transmission line TX2 of equal length, a bent trace 131 is provided on signal transmission line TX1; similarly, a bent trace 132 is provided on signal receiving line RX1, thereby saving space on the circuit board 100.

As shown in Figure 3, signal transmission line TX3 connects CPU board connector 111 and interface board connector 122, and signal transmission line TX4 connects CPU board connector 112 and interface board connector 122. Signal transmission lines TX3 and TX4 are of equal length. Signal reception line RX3 connects CPU board connector 111 and interface board connector 122, and signal reception line RX3 connects CPU board connector 112 and interface board connector 122. Signal transmission lines RX3 and RX4 are of equal length.

The distance between CPU board connector 111 and interface board connector 122 is less than the distance between CPU board connector 112 and interface board connector 122. Therefore, in order to make signal transmission line TX3 and signal transmission line TX4 of equal length, a bent trace 133 is provided on signal transmission line TX3; similarly, a bent trace 134 is provided on signal receiving line RX3, thereby saving space on the circuit board 100.

According to some embodiments of this application, there are gaps between the bent traces and CPU board connectors 111, 112, and interface board connectors 121/122/123/124. During communication, the interference isolation between the bent traces and CPU board connectors 111, 112, and interface board connectors 121/122/123/124 is improved, mutual interference is reduced, and the reliability of communication is improved.

According to some embodiments of this application, the signal transceiver line 130 includes a connection cable connected to the circuit board 100. The connection cable is, for example, made based on a flexible printed circuit (FPC) or other balanced cable.

According to some embodiments of this application, please continue to refer to Figures 2 and 3. The equal-length signal transmission lines TX1 to TX4 include a pair of differential signal transmission lines, and the signal reception lines RX1 to RX4 include a pair of differential signal reception lines. In the technical solution of this application embodiment, the host backplane 10 provides an LVDS signal transmission line communication mode, which features low power consumption and low bit error rate.

According to some embodiments of this application, please continue to refer to Figures 1 to 3. The host backplane 10 includes two CPU board connectors 111 and 112. The technical solution of this application provides a host backplane 10 with dual CPU boards, offering sufficient computing power and reliability.

According to some embodiments of this application, please continue to refer to Figures 1 to 3. Two CPU board connectors 111 and 112 are arranged in the middle area of the circuit board 100; a plurality of interface board connectors 121 to 124 are distributed on the opposite sides or around the two CPU board connectors 111 and 112.

In the technical solution of this application embodiment, the signal transceiver lines 130 of the CPU board connectors 111 and 112 to the interface board connectors 121 to 124 on opposite sides or around are arranged in an equal length and symmetrical structural layout to meet the requirement that the CPU board or interface board can be interchanged at any time, thereby improving the redundancy of the system.

According to some embodiments of this application, please continue to refer to Figures 2 and 3. The distance between the edges of the two CPU board connectors 111 and 112 is greater than the distance between the edges of two adjacent interface board connectors. This is beneficial for heat dissipation of the CPU board to which the CPU board connectors 111 and 112 are plugged in.

According to some embodiments of this application, please continue to refer to FIG1, two sets of redundant signal lines are connected between each CPU board connector 111, 112.

In the technical solution of this application embodiment, two sets of redundant signal lines are provided between each CPU board connector 111 and 112 to improve the communication reliability of the CPU boards connected to each CPU board connector 111 and 112.

It is understandable that the aforementioned equal lengths of the lines should be considered relatively equal. Through some tests, it can be seen that the line length error is related to the signal transmission rate, for example:

When the signal transmission rate is less than 1 gigabits per second (Gbps), the line length error between the two lines is allowed to be ±0.5 millimeters (mm).

When the signal transmission rate is 1Gbps to 10Gbps, the allowable error in line length between the two lines is ±0.25mm.

When the signal transmission rate is greater than 10Gbps, the allowable error in line length between the two lines is ±0.125mm.

Secondly, embodiments of this application provide a valve control device, including the host backplane 10 as described above, two CPU boards and at least one interface board, the two CPU boards being plugged into the two CPU board connectors 111 and 112 of the host backplane 10 respectively, and the interface board being plugged into the interface board connectors 121 to 124 of the host backplane 10.

According to some embodiments of this application, each interface board and each energy storage submodule need to communicate in two ways so that effective control of the energy storage submodule can still be maintained when the control system fails in one way.

In the technical solution of this application embodiment, the host backplane 10 and the valve control device have at least the following functions or effects:

It allows the same CPU board to be swapped at the positions of the two CPU board connectors 111, and the two CPU boards can still maintain normal data communication.

It enables high-speed differential signal communication between each CPU board and each interface board, and each interface board achieves dual-path communication redundancy control with two CPU boards.

It allows the same interface board to be inserted into all interface board connectors 121-124, and enables dual-channel communication redundancy control with two CPU boards.

It can ensure that the signal transmission delay from the same interface board to two CPU boards is the same, thus guaranteeing timing consistency.

A single valve control device requires only one type of CPU board and one type of interface board to meet the device installation requirements, effectively reducing the number of board types.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims (13)

A host backplane includes a circuit board, wherein at least two CPU board connectors and multiple interface board connectors are provided on the circuit board. The different CPU board connectors and the same interface board connector are respectively connected to signal transceiver lines of equal length. The host backplane as described in claim 1, wherein the equal-length signal transceiver lines include equal-length signal transmitting lines and equal-length signal receiving lines. The host backplane as described in claim 1 or 2, wherein the signal transceiver lines include copper plating disposed on the circuit board. The host backplane as described in claim 3, wherein the copper plating includes bent traces. The host backplane as described in claim 4, wherein there is a gap between the bent trace and the CPU board connector and the interface board connector. The host backplane as described in claim 1 or 2, wherein the signal transceiver line includes a connecting cable connected to the circuit base plate. The host backplane as described in any one of claims 2 to 6, wherein the signal transmission line includes a pair of differential signal transmission lines, and the signal reception line includes a pair of differential signal reception lines. The host backplane as described in any one of claims 1 to 6, wherein it includes two of the CPU board connectors. The host backplane as claimed in claim 8, wherein the two CPU board connectors are arranged in the middle area of the circuit board base. The host backplane as described in claim 8 or 9, wherein the plurality of interface board connectors are distributed on opposite sides or around the two CPU board connectors. The host backplane as described in any one of claims 8 to 10, wherein the distance between the edges of the two CPU board connectors is greater than the distance between the edges of two adjacent interface board connectors. The host backplane as described in any one of claims 1 to 11, wherein two sets of redundant signal lines are connected between each of the CPU board connectors. A valve control device includes a host backplane as described in any one of claims 1 to 12, two CPU boards and at least one interface board, wherein the two CPU boards are respectively plugged into two CPU board connectors of the host backplane, and the interface board is plugged into an interface board connector of the host backplane.