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WO2025219918A1 - Duplication d'un sous-élément stockable d'un premier élément stockable - Google Patents

Duplication d'un sous-élément stockable d'un premier élément stockable

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Publication number
WO2025219918A1
WO2025219918A1 PCT/IB2025/054023 IB2025054023W WO2025219918A1 WO 2025219918 A1 WO2025219918 A1 WO 2025219918A1 IB 2025054023 W IB2025054023 W IB 2025054023W WO 2025219918 A1 WO2025219918 A1 WO 2025219918A1
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WO
WIPO (PCT)
Prior art keywords
previously calculated
prompts
attention content
graphic processing
value storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/IB2025/054023
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English (en)
Inventor
Eshcar Hillel
Moshe Twitto
Aryeh Mergi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pliops Ltd
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Pliops Ltd
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Filing date
Publication date
Application filed by Pliops Ltd filed Critical Pliops Ltd
Publication of WO2025219918A1 publication Critical patent/WO2025219918A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0475—Generative networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N5/00—Computing arrangements using knowledge-based models

Definitions

  • LLM Large Language Models
  • SLA Service Level Agreement
  • FIG. 1 illustrates an example of performing in parallel (a) prefetching a next layer previously calculated attention content, (b) performing transformer related calculations to a current layer, and (c) storing previously calculated attention content of a previous layer;
  • FIG. 2 illustrates an example of prefill operation and decode operations
  • FIG. 3 illustrates an example of a system that includes multiple compute nodes and multiple storage nodes that communicate with each other;
  • FIG. 4 illustrates an example of a system that includes multiple compute nodes and multiple storage nodes that communicate with each other;
  • FIG. 5 illustrates an example of a compute node and a storage node
  • FIG. 6 illustrates an example of a compute node and a storage node
  • FIG. 7 illustrates an example of a compute node and a storage node
  • FIG. 8 illustrates an example of a software stack, a storage node software stack and functionalities of the GPU host, GPU and KV store supported by the software stack
  • FIG. 9 illustrates an example of a method.
  • KV- cache Key-Value cache
  • This application illustrates a solution that uses a hardware-based accelerator for KV-cache processing.
  • the solution exhibits significant performance improvements and cost savings compared to existing LLM inference engines.
  • Attention-based language models such as those employing transformers, calculate attention scores signifying the correlation between each input token and all other preceding tokens in the sequence. This is a computationally intensive process, especially for long sequences. It is processed by the self-attention block at each layer of the model.
  • a query is handled in two parts: (1) the prefill stage, in which attention is computed for the entire prompt, (2) the auto-regressive decoding stage, generating the tokens that comprise the response to the query.
  • the context is gradually growing as each decoding step adds a token to the context.
  • the attention context is captured by two tensors called Key and Value.
  • KV-cache Key-Value cache
  • the prefill phase computes and prefills the KV-cache with the keys and the values of the entire prompt. Decoding steps reuse the entries from the KV-cache and append new entries to it upon each generated token.
  • Three main indicators are used to evaluate the performance of LLM inference systems: Time-To-First-Token (TTFT), Time-Per-Output-Token (TPOT), Throughput.
  • TTFT measures how quickly users start seeing the model’s output after entering their query. Low waiting times for a response are essential in real-time interactions. This metric is driven by the time required to process the prompt, prefill the KV-cache and then generate the first output token.
  • TPOT measures time to generate an output token for each user query in the decode phase.
  • the reciprocal metric is tokens-per-second-per-user (tps/user). This metric corresponds with how each user perceives the “speed” of the model. For example, a TPOT of 100 milliseconds/tok is 10 tokens per second per user, or approximately 450 words per minute, which is faster than a typical person can read.
  • Throughput measures the number of output tokens per second the inference system can generate across all users and requests. This can be presented as tokens-per- second- per-GPU (tps/GPU).
  • the inference system is composed of a cluster of GPU servers for handling multiple concurrent user requests. Each server is equipped with high- performance GPUs and is responsible for processing a subset of the incoming requests.
  • KV-cache is known to have a huge memory footprint. Hence, many techniques are aimed at reducing its size. Multi-Head Latent Attention is an advanced KV- cache compression technique that generalizes Grouped Query Attention. While these innovations optimize memory footprint and reduce memory bandwidth usage, they do not reduce the computational overhead for generating KV-cache - which is reduced by using the suggested solution.
  • Chatbots are the most widely adopted use case for leveraging the powerful chat and reasoning capabilities of LLMs. GPU memory capacity is limited, and the cache eviction policy discards stale conversations. It may even delete content related a conversation round soon after the conversation round ends. I such case, when a client resumes (after being idle for some time) the prefill phase must recompute the cache for the entire history. This re-computation incurs a computational cost quadratic in the dimension of token embedding and in the total conversation length. With the increase of sequence (context) length to 100s thousands to millions, and the dimension of token embeddings to more than 10K, quadratic computation at prefill phase translates to 100s Tera-Flops.
  • KV-Cache Offloading moves large KV- caches from GPU memory to KV-cache pools that reside on another memory or storage device enabling much higher KV-cache hits.
  • the mission is to design a system to store and retrieve precomputed KV-cache entries efficiently. The goal is reducing the compute and accelerating the prefill phase, specifically in multi-tum applications with recurring requests.
  • a. Data sharing allow multiple GPU servers to share the KV -cache data for optimal load balancing and efficiency. b.
  • each KV-cache block, or prefix-tree node is composed of 16 - 32 tokens, with one token carrying few KBs. Total of less than 100KB of data per block.
  • the benefit of small blocks is minimal redundancy as multiple branching contexts can share prefix blocks.
  • Object Size Modem techniques, such as GQA, reduce the vector size without improving compute requirements. The result is significantly smaller IO size.
  • the object size per attention layer depends on D the model hidden dimension (e.g., 5120, 8K, 16K); P the precision in bytes per element (1/2, 1, 2), which can change across layers; C the number of tokens indexed together in a block (16, 32); G the GQA factor (1, 4, 8); TP the tensor parallelism. Across various parameter sets, single-layer object size can span from a few hundred bytes to several tens ofkilobytes.
  • Compression and adaptive quantization techniques further reduces the vector size. It also causes the vector size to vary significantly with up to 4x compression gain. Variable size objects within files suffers from a major overhead.
  • a non-optimal approach would be to first fetch entries of history KV- cache from storage, then compute the new entries, and finally store the newly computed KV-cache entries (called delta prefill) back in storage.
  • delta prefill the newly computed KV-cache entries
  • This IO-compute overlap can result in excessive CPU-GPU synchronization overhead, and small read IOs of size between 1KB to 20KBs.
  • Traditional file systems and DRAM-HBM data transfers perform poorly for many tiny requests.
  • the solution includes LLM KV-Cache Offloading.
  • the solution leverages GPU-initiated KV storage to offload KV-cache processing to dedicated KV-store hardware that includes (for example - the LightningAI of Pliops Ltd. Of Tel Aviv, Israel).
  • the solution replaces prefill by compute with prefill by IO operations.
  • the KV-cache tensors are persisted to KV-storage as they are produced: either two dense vectors per token, or one sparse vector per token in more advanced models.
  • the full context of the user conversation is stored in storage.
  • the application can choose to restore only a prefix of the history based on availability of resources, specifically HBM space, compute, and memory bandwidth based on served traffic.
  • the entire context of all user history is stored in KV storage. It can be restored even days after the session was last visited.
  • the application can manage the history storage: delete expired sessions (e.g., for GDPR compliance) or move them to “cold” storage.
  • Users’ context history store can be mined and be the basis for analytics, BI, personalization, and monetization opportunity for app owner, and as a third-party data provider.
  • the solution is implemented by the LightningAI which is a generic infrastructure for Al applications and app lie s disaggregated KV storage, extreme performance, GPU-Initiated KV IO Pliops HW KV solution saturates the fabric (including 400Gb and above) also when the traffic is with extremely small Random IOs size in read and write.
  • LightningAI is a generic infrastructure for Al applications and app lie s disaggregated KV storage, extreme performance, GPU-Initiated KV IO Pliops HW KV solution saturates the fabric (including 400Gb and above) also when the traffic is with extremely small Random IOs size in read and write.
  • Pliops XDP Delivers Required Efficiency Combining hardware-accelerated KV with compression and quantization delivers end-to-end system efficiency: high IOPS per dol- lar/watt, and Low networking overhead.
  • the solutions' performance gains are proportional to both IO speed and compute requirements. Since MLA, like GQA, reduces KV cache size without lowering compute needs, it results in a net gain for the solution. More broadly, any KV compression technique that does not proportionally reduce compute requirements — such as MQA, GQA, and MLA — inherently enhance the solutions efficiency.
  • Expected Gain Analysis We first analyse the expected gain for static batching scheduling: Denote by TTLT (B) and TPOT (B) the time it takes to run a prefrll and decode steps, respectively, in a batch of size B.
  • the solutions source of gain is pre-fill time reduction.
  • Replacing GPU compute with storage IO in prefrll allows higher HBM bandwidth efficiency in decode steps via larger batch size.
  • TTFT kv4kv (B) B * TTFT (l)/x.
  • the solution can increase batch size by a factor of x and still meet SLAs
  • DeepSeek models incorporate architectural modifications that facilitate speculative decoding, where multiple tokens are predicted in each decoding round. This reduces HBM bandwidth requirements per token, particularly benefiting batched inference.
  • the solution performance gain is tied to HBM bandwidth efficiency.
  • speculative decoding reduces the HBM bandwidth tax per token, it enables larger batch sizes, which in turn amplifies the solutions advantages.
  • Prefill -decode disaggregation is an inference deployment strategy adopting separate prefill and decode GPU clusters that is becoming popular.
  • the solution delivers massive efficiency gains — up to 8x.
  • prefill GPU cluster footprints can be reduced by at least 5x, significantly improving deployment efficiency and cost-effectiveness.
  • the solution utilizesKV storage accesses to replace compute-based prefill with an IO- based prefill.
  • Compute is quadratic in model dimension
  • IO is linear in model dimension.
  • Attention tensors are persisted to KV storage as they are produced: two dense vectors per layer per token: single token in each decoding round, all prompt tokens in the prefill phase of each conversation turn.
  • the pre-fill phase restores the attention tensors in HBM by retrieving them from the KV-storage instead of computing them from the prompt itself.
  • Requests are batched and allocated resources in a way that maximizes resources utilization - the batching may include applying continuous batching or other type of batching.
  • NVLink a wire-based serial multi -lane near-range communications link developed by Nvidia
  • NVlink connecting Grace memory with Hopper memory in a Grace Hopper superchip.
  • the full context of the user conversation is stored in storage.
  • the application can choose to restore only a suffix of the history based on availability of resources, specifically HBM space/compute/bandwidth based on served traffic.
  • the application can manage the history storage: delete expired sessions (e.g., for GDPR compliance) or move them to "cold” storage.
  • Figure 1 illustrates an example of performing in parallel (a) prefetching a next layer previously calculated attention content, (b) performing transformer related calculations to a current layer, and (c) storing previously calculated attention content of a previous layer.
  • Figure 1 illustrates: a. A computation of a token in relation to a transformer model having N layers - which shows a sequence of N computation steps (compute L0 - compute LN) and related get/put submission/completion kernel instructions/notifications denoted 21, 22, 23 and 3. b. Prefetching a next layer previously calculated attention content (IOs GET L0...IOs GET L4 12-0 - 12-4) in parallel to compute LO-Compute L3. For simplicity of explanation the prefetching related to an N layer (preceding Compute LN) is not shown. c.
  • Figure 3 illustrates a system that includes multiple compute nodes 40 and multiple storage nodes 50 that communicate with each other.
  • the compute nodes are disaggregated from the storage nodes 50.
  • the compute nodes 40 include GPUs 42, application containers 41 that (at least) execute applications).
  • the storage nodes 50 include memory units 52 that may buffer content, controllers 53 that manage the operation of the storage nodes - including managing KV content , and Solid State Disks (SSDs) 51.
  • SSDs Solid State Disks
  • Figure 4 illustrates a system that includes multiple compute nodes 40a and multiple storage nodes 50a that communicate with each other.
  • the compute nodes 40a are disaggregated from the storage nodes 50a.
  • Figure 8 illustrates an example of a software stack 60, storage node software stack 70 and functionalities of the GPU host, GPU and KV store supported by the software stack.
  • the software stack includes at least some of: a. vUUM production stack that is a combination of tools and infrastructure used to serve vUUM (a high-throughput and memory-efficient UUM inference engine) in production environments. b. vUUM + KV cache acceleration manages at least in part the interaction of between the vUUM and the key-value cache mechanism. c. KV I/O SDK (software development kit exposing KV API for developers). d.
  • KV Key-Value
  • GPUs GPUs
  • DPUs Data Processing Units
  • KV SDK API KV SDK API
  • GPU KV I/O GPU KV I/O
  • DPU NVMe emulation CPU NVMe emulation
  • CPU KO I/O NV NVMe
  • the KV SDK API Key-Value Software Development Kit API
  • KV SDK API is a programming interface for interacting with key-value storage systems. It abstracts put/get/delete operations like in RocksDB, Redis, or KV-based flash storage.
  • the KV SDK may interface with specialized hardware to: Speed up access, Enable parallelism, Offload operations from the CPU.
  • the GPU KV I/O GPU Key-Value Input/Output
  • UUM inference engines like vUUM, where models can store and retrieve cached key-value tensors entirely within GPU memory.
  • the DPU NVMe Emulation is executed by a DPU that emulates an NVMe SSD, responding to block read/write commands.
  • the CPU NVMe Emulation is executed by a CPU that emulates an NVMe SSD, responding to block read/write commands.
  • the triggered Multi I/O is a high-performance I/O scheduling mechanism. Multiple I/O operations (like NVMe reads/writes) are triggered by a single event or condition, allowing batch execution. Especially useful in parallel systems (like GPUs or DPUs) to reduce the number of syscall context switches or DMA triggers.
  • Figure 8 illustrates, in addition to software elements illustrated above, a software node production stack 70 which coordinates scheduling of inference tasks to different vllm instances running on various GPU nodes.
  • Figure 9 illustrates an example of method 100 for transformer inference.
  • method 100 starts by step 110 of receiving one or more prompts.
  • step 110 is followed by step 120 of responding to the one or more prompts by executing multiple prefill and decoding iterations.
  • step 120 includes step 121 of disaggregating graphic processing unit prefill related calculations from graphic processing unit decoding related calculations.
  • step 120 includes step 122 of storing attention content in the hardware key-value storage immediately following a calculating of the attention content.
  • the multiple prefill and decoding iterations are associated with different layers of a transformer model.
  • step 120 includes step 123 of pipelining (i) retrieving operations, (ii) transformer related calculations and (iii) storing operations related to the hardware key-value storage.
  • step 123 includes performing in parallel (a) prefetching a next layer previously calculated attention content, (b) performing transformer related calculations to a current layer, and (c) storing previously calculated attention content of a previous layer.
  • method 120 includes step 124 of storing by the hardware key-value storage previously calculated attention content for a period that exceeds (for example by factors of 10, 100, 1000 and even more) a time to live period of content cached in at least one of a graphic processing unit cache, a local cache, or a data processing unit cache.
  • the extended delay period guarantees that even hen processing multiple threads and/or skipping from one task to the other, the required attention content will still reside in the key-value storage and can be used for retrieving the attention state from the key value storage.
  • the size of the hardware key-value storage exceeds by a factor of at least 100, 1000, 10000 the size of the graphic processing unit cache, a local cache, or a data processing unit cache - whish allows the storage the entire (or significant selected portions of) conversation history (even when the conversation is very long and is associated with extensive amount of attention content).
  • step 120 includes step 125 of applying contentbased and application- agnostic indexing of attention content items stored in the hardware keyvalue storage.
  • the one or more prompts are associated with a conversation history that is stored in the hardware key-value storage, and the previously calculated attention content forms the entire history or forms only a portion of the history.
  • the portion of the history is determined based on batching.
  • step 120 includes step 126 of triggering the retrieving the previously calculated attention content by at least one of the graphic processing units.
  • step 120 includes step 127 of initiating the retrieving the previously calculated attention content by at least one of the graphic processing units.
  • a data processing unit controls the retrieving.
  • step 110 includes step 112 of batching multiple received prompts to provide a batch of the one or more prompts.
  • the hardware key-value storage includes multiple key-value storage nodes.
  • the graphic processing units are in multiple graphic processing nodes that are in communication with the multiple key-value storage nodes.
  • a storable element includes information and [00111] Any reference to “may be” should also refer to “may not be.”
  • Any reference in the specification to a method should be applied mutatis mutandis to a system capable of executing the method and should be applied mutatis mutandis to a non-transitory computer readable medium that stores instructions that once executed by a computer result in the execution of the method.
  • Any reference in the specification to a system and any other component should be applied mutatis mutandis to a method that may be executed by a system and should be applied mutatis mutandis to a non-transitory computer readable medium that stores instructions that may be executed by the system.
  • any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved.
  • any two components herein combined to achieve a particular functionality may be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components.
  • any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality.
  • the illustrated examples may be implemented as circuitry located on a single integrated circuit or within a same device.
  • the examples may be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word ‘comprising’ does not exclude the presence of other elements or steps then those listed in a claim.
  • the terms “a” or “an,” as used herein, are defined as one or more than one.

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Abstract

L'invention concerne un procédé d'inférence de transformeur, le procédé consistant à (a) recevoir une ou plusieurs invites ; et (b) répondre à la ou aux invites en exécutant de multiples itérations de préremplissage et de décodage. Une exécution d'une itération de préremplissage qui nécessite du contenu d'attention calculé précédemment consiste à récupérer le contenu d'attention calculé précédemment à partir d'un stockage matériel de clé-valeur qui est désagrégé d'unités de traitement graphique utilisées pour effectuer des calculs associés au transformeur pendant les multiples itérations de préremplissage et de décodage.
PCT/IB2025/054023 2024-04-16 2025-04-16 Duplication d'un sous-élément stockable d'un premier élément stockable Pending WO2025219918A1 (fr)

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US63/634,907 2024-04-16

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030172149A1 (en) * 2002-01-23 2003-09-11 Andiamo Systems, A Delaware Corporation Methods and apparatus for implementing virtualization of storage within a storage area network
US20070043771A1 (en) * 2005-08-16 2007-02-22 Ludwig Thomas E Disaggregated resources and access methods
US20200356724A1 (en) * 2019-05-06 2020-11-12 University Of Electronic Science And Technology Of China Multi-hop attention and depth model, method, storage medium and terminal for classification of target sentiments
US11531863B1 (en) * 2019-08-08 2022-12-20 Meta Platforms Technologies, Llc Systems and methods for localization and classification of content in a data set

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030172149A1 (en) * 2002-01-23 2003-09-11 Andiamo Systems, A Delaware Corporation Methods and apparatus for implementing virtualization of storage within a storage area network
US20070043771A1 (en) * 2005-08-16 2007-02-22 Ludwig Thomas E Disaggregated resources and access methods
US20200356724A1 (en) * 2019-05-06 2020-11-12 University Of Electronic Science And Technology Of China Multi-hop attention and depth model, method, storage medium and terminal for classification of target sentiments
US11531863B1 (en) * 2019-08-08 2022-12-20 Meta Platforms Technologies, Llc Systems and methods for localization and classification of content in a data set

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