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WO2025214078A1 - 计算设备及控制方法 - Google Patents

计算设备及控制方法

Info

Publication number
WO2025214078A1
WO2025214078A1 PCT/CN2025/082718 CN2025082718W WO2025214078A1 WO 2025214078 A1 WO2025214078 A1 WO 2025214078A1 CN 2025082718 W CN2025082718 W CN 2025082718W WO 2025214078 A1 WO2025214078 A1 WO 2025214078A1
Authority
WO
WIPO (PCT)
Prior art keywords
ssd
pin
circuit board
connector
bmc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/082718
Other languages
English (en)
French (fr)
Other versions
WO2025214078A9 (zh
Inventor
赵洪涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
XFusion Digital Technologies Co Ltd
Original Assignee
XFusion Digital Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by XFusion Digital Technologies Co Ltd filed Critical XFusion Digital Technologies Co Ltd
Publication of WO2025214078A1 publication Critical patent/WO2025214078A1/zh
Publication of WO2025214078A9 publication Critical patent/WO2025214078A9/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
    • G06F1/186—Securing of expansion boards in correspondence to slots provided at the computer enclosure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1608—Error detection by comparing the output signals of redundant hardware
    • G06F11/1616—Error detection by comparing the output signals of redundant hardware where the redundant component is an I/O device or an adapter therefor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver

Definitions

  • the embodiments of the present application relate to the field of server technology, and in particular to a computing device and a control method.
  • SSDs solid-state drives
  • M.2 Next Generation Form Factor
  • PCIE peripheral component interconnect express
  • the M.2 interface is mainly compatible with Socket 2 and Socket 3 slots.
  • the Socket 2 slot can support M.2 SSDs compatible with SATA and PCIe x2 channel interfaces, and the corresponding key position is B Key
  • the Socket 3 slot supports M.2 SSDs compatible with PCIe x4 channel interfaces, and the corresponding key position is M Key.
  • SSD interfaces include SATA M.2 interface and Non-Volatile Memory express (NVMe) M.2 interface.
  • NVMe Non-Volatile Memory express
  • the M.2 interface and SSD are both set on a carrier board.
  • the carrier board is set inside the server chassis, taking up space inside the chassis.
  • the SSD has a problem, the chassis must be disassembled, making maintenance difficult.
  • the current M.2 interface is not compatible with the SATA M.2 interface and the NVMe M.2 interface.
  • the embodiments of the present application provide a computing device and a control method that can save internal space of a chassis, facilitate maintenance, and be compatible with SATA M.2 interfaces and NVMe M.2 interfaces.
  • An embodiment of the present application provides a computing device, comprising: a first card slot, a first circuit board and a mainboard; the first card slot is used to plug in the first circuit board; the first circuit board comprises: an M.2 connector; the M.2 connector is used to connect to a solid-state drive (SSD); the mainboard comprises a baseboard management controller (BMC); a presence pin of the first circuit board is connected to the BMC; a presence pin and an SSD type pin of the M.2 connector are connected to a serial bus interface of the BMC; the BMC is used to detect the status of the presence pin of the first circuit board to determine whether the first circuit board is in place; when the first circuit board is in place, whether the SSD is in place is determined according to the level of the presence pin of the M.2 connector; and when the SSD is in place, the type of the SSD is determined according to the level of the SSD type pin.
  • the BMC baseboard management controller
  • the embodiment of the present application inserts a newly designed first circuit board into the first card slot, and an M.2 connector and a serial bus expansion device are designed on the first circuit board.
  • the presence pin of the first circuit board is connected to the BMC on the server motherboard; the presence pin and the SSD type pin of the M.2 connector are both connected to the serial bus interface of the BMC through the serial bus expansion device; the BMC determines whether the SSD on the first circuit board is in place by detecting the status of the presence pin. When the SSD is in place, it continues to determine whether the type of the SSD is SATA or NVMe. It is compatible with both types of SSDs, expands application scenarios, and is more flexible to use.
  • the motherboard further includes: a central processing unit; the M.2 connector is connected to the central processing unit; the BMC is further used to inform the central processing unit of the SSD type; the central processing unit is used to determine a protocol that matches the SSD type based on the SSD type, the protocol including a Serial Advanced Technology Attachment interface (SATA) protocol and a Non-Volatile Memory Host Controller Interface (NVMe) protocol.
  • SATA Serial Advanced Technology Attachment interface
  • NVMe Non-Volatile Memory Host Controller Interface
  • the M.2 SSD carrier board in the form of an OCP card provided in the embodiment of the present application only occupies the space of an OCP card in size, and there is no need to reserve a dedicated space for the M.2 SSD carrier board in the chassis of the computing device in advance.
  • the M.2 SSD carrier board can be conveniently removed without opening the chassis of the computing device, thereby realizing maintenance of the M.2 SSD without unpacking the chassis.
  • the M.2 connector includes a first M.2 connector and a second M.2 connector, and the first circuit board also includes a serial bus expander; the first M.2 connector is used to connect to a first SSD, and the second M.2 connector is used to connect to a second SSD; the first SSD and the second SSD are backed up for each other; the in-position pin and the SSD type pin of the first M.2 connector are both connected to the serial bus interface of the BMC through the serial bus expander; the in-position pin and the SSD type pin of the second M.2 connector are both connected to the serial bus interface of the BMC through the serial bus expander; the first M.2 connector includes a PCIE X4 pin, the PCIE X3 pin of the first M.2 connector is connected to the central processing unit, and the remaining PCIE X1 pin of the first M.2 connector is connected to the central processing unit as a SATA pin; the second M.2 connector includes a PCIE X4 pin, the PCIE X3 pin of the
  • an OCP card is equipped with two M.2 connectors, corresponding to two SSDs.
  • the following describes how to connect an OCP card to two SSDs.
  • the M.2 connector provided in this embodiment is compatible with both SATA and NVMe SSDs, expanding its application scenarios and bringing greater convenience to actual use.
  • a first presence pin and a second presence pin of the first circuit board are respectively connected to two IO pins of the BMC, and the first presence pin and the second presence pin are both grounded on the first circuit board; a third presence pin and a fourth presence pin of the first circuit board are respectively connected to two other IO pins of the BMC; the third presence pin and the fourth presence pin of the first circuit board are both left floating on the first circuit board; and the BMC is configured to determine that the first circuit board is in place when detecting that the levels of the two IO pins connected to the first presence pin and the second presence pin are low.
  • the embodiments of the present application do not specifically limit the high and low level states of the presence pin.
  • the embodiments of the present application do not specifically limit the high and low level states of the SSD type pin.
  • the SSD type pin when the level of the SSD type pin is low, the SSD type is determined to be SATA; conversely, when the level of the SSD type pin is high, the SSD type is determined to be NVMe.
  • a board ID is also stored on the first circuit board; the BMC is further used to read the board ID and determine whether the first circuit board is an M.2 carrier board based on the board ID. If it is not the M.2 carrier board, the central processor configures the first circuit board according to the bandwidth requirements of the standard OCP card.
  • the BMC can determine the function of the inserted OCP card by reading the Board ID information. Specifically, the BMC uses the Board ID to determine whether the first circuit board 100 is an M.2 carrier board. If not, the BMC configures it as a standard OCP card.
  • the BMC is specifically used to determine that the SSD type is NVMe when it is detected that the level of the SSD type pin is high; and when it is detected that the level of the SSD type pin is low, determine that the SSD type is SATA.
  • the embodiment of the present application does not specifically limit the high and low levels of the SSD type pins, and can be set according to actual needs.
  • an embodiment of the present application also provides a control method for a computing device, wherein the computing device includes: a first card slot, a first circuit board and a motherboard; the first card slot is used to plug in the first circuit board; the first circuit board includes: an M.2 connector; the M.2 connector is used to connect to a solid-state drive (SSD); the motherboard includes a baseboard management controller (BMC); the presence pin of the first circuit board is connected to the BMC; the presence pin of the M.2 connector and the SSD type pin of the M.2 connector are both connected to the serial bus interface of the BMC; the method includes: judging whether the first circuit board is in place according to the level of the presence pin of the first circuit board; if the first circuit board is in place, judging whether the SSD is in place according to the level of the presence pin of the M.2 connector; if the SSD is in place, determining the type of the SSD according to the level of the SSD type pin.
  • the computing device includes: a first card slot, a first circuit board and
  • the method provided in an embodiment of the present application further includes: determining a protocol that matches the SSD type based on the SSD type; the protocol includes a Serial Advanced Technology Attachment interface SATA protocol and a non-volatile memory host controller interface NVMe protocol.
  • a board ID is also stored on the first circuit board in an embodiment of the present application.
  • the method further includes: reading the board ID, determining whether the first circuit board is an M.2 carrier board through the board ID, and if it is not the M.2 carrier board, configuring the first circuit board according to the bandwidth requirements of the standard OCP card by the central processor.
  • a possible implementation method is the method provided in an embodiment of the present application, wherein the type of the SSD is determined by the level of the SSD type pin, specifically including: when the level of the SSD type pin is detected to be high, determining that the SSD type is NVMe; when the level of the SSD type pin is detected to be low, determining that the SSD type is SATA.
  • FIG1A is a schematic diagram of a computing device provided in an embodiment of the present application.
  • FIG1B is a schematic diagram of another computing device provided in an embodiment of the present application.
  • FIG1C is a schematic diagram of another computing device provided in an embodiment of the present application.
  • FIG2 is a schematic diagram of a SATA M.2 provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of an NVMe M.2 provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of another computing device provided in an embodiment of the present application.
  • FIG5 is a flowchart of a method for controlling a computing device provided in an embodiment of the present application.
  • FIG6 is a flowchart of another method for controlling a computing device provided in an embodiment of the present application.
  • the computing device provided in the embodiments of this application is not limited to specific application scenarios.
  • the computing device is described using a server as an example, and the type of server is not specifically limited.
  • the computing device can be a server.
  • the server can be located in a data center or other areas, and this embodiment of the application does not specifically limit it.
  • a server is a type of computing device that runs faster and has a higher load than ordinary computers. It provides computing or application services to other clients (such as PCs, smartphones, and other devices) on the network. Servers have high-speed CPU computing power, long-term reliable operation, strong external data throughput, and improved scalability. Servers are categorized into rack-mount, blade-mount, tower, and cabinet-mount types based on their appearance; functionally, servers can also include AI servers, such as GPU servers.
  • a single board is a common component in servers. It can be understood as a general term for circuit boards, which can take various forms, such as a mainboard, power management board, or network data exchange board.
  • a single board can be equipped with other components, such as a controller, processor, or other chips, to implement the server's computing functions.
  • a single board can also be equipped with an electrical connector, which allows the board to connect to other electrical components or to electrically connect to another single board.
  • the server may include a single board and a power supply, where the power supply is used to supply power to various loads on the single board; the loads may be a central processing unit, memory, baseboard management controller, etc., which are arranged on the single board.
  • the embodiments of the present application do not specifically limit the type of single board.
  • the single board may be a main board or other single board.
  • the motherboard is a circuit board in a server. It can be equipped with components such as controllers, memory modules, and electrical connectors.
  • the controller may include a central processing unit (CPU), a south bridge chip (PCH), a microcontroller unit (MCU), a complex programmable logic device (CPLD), and a field programmable gate array (FPGA).
  • the CPU can be electrically connected to peripheral devices through internal wiring and electrical connectors on the motherboard.
  • the CPU can be electrically connected to devices such as network cards and graphics cards through electrical connectors.
  • a typical server motherboard can be equipped with a CPU, PCH, and CPLD, where there can be one or more CPUs.
  • memory modules include but are not limited to the following types: dual-inline-memory modules (DIMMs) and single-inline-memory modules (SIMMs).
  • the memory chips on the DIMMs can be synchronous dynamic random access memory (SDRAM), fourth-generation double data rate synchronous dynamic random access memory (DDR4), and fifth-generation double data rate synchronous dynamic random access memory (DDR5).
  • SDRAM synchronous dynamic random access memory
  • DDR4 fourth-generation double data rate synchronous dynamic random access memory
  • DDR5 fifth-generation double data rate synchronous dynamic random access memory
  • the baseboard management controller (BMC) can be set on the motherboard.
  • the BMC is an essential component of a server, used to monitor its operational status, such as temperature, fan speed, power supply status, and operating system status.
  • the BMC operates independently of the server and is not affected by it. It can perform operations such as firmware upgrades, device monitoring, and remote startup while the server is in standby mode. It can also record critical logs in the event of a server downtime.
  • solid-state drive also known as solid-state drive
  • solid-state drive is a hard disk made of an array of solid-state electronic storage chips.
  • the Open Compute Project (OCP) card is a hardware design specification customized for data centers, including custom design specifications for computer rooms, cabinets, servers, storage, network equipment, and cloud hardware management.
  • An OCP card is an Open Compute Project network interface card.
  • the sides of a server chassis typically include multiple first card slots, but some of these slots are typically empty, without an OCP card inserted.
  • the embodiment of the present application is designed to be compatible with both SATA and NVMe interfaces.
  • a newly designed first circuit board is inserted into the first card slot.
  • the first circuit board has the same size and interface shape as an existing OCP card and can also be an M.2 carrier board.
  • An M.2 connector and a serial bus expander are designed on the first circuit board.
  • the in-position pin of the first circuit board is connected to the BMC on the server motherboard.
  • the in-position pin and SSD type pin of the M.2 connector are both connected to the serial bus interface of the BMC through the serial bus expander.
  • the BMC determines whether the SSD on the first circuit board is in place by detecting the status of the in-position pin. When the SSD is in place, the BMC continues to determine whether the SSD type is SATA or NVMe.
  • FIG. 1A is a schematic diagram of a computing device provided in an embodiment of the present application.
  • the side of the server 1000 chassis typically includes multiple first card slots.
  • these first card slots can be used to insert an OCP card.
  • these first card slots are typically vacant and do not have an OCP card inserted.
  • the vacant first card slots can be used to insert the first circuit board 100 provided in an embodiment of the present application.
  • the first circuit board 100 has the same size and interface shape as existing OCP cards and can also be an M.2 carrier board.
  • FIG. 1B is a schematic diagram of another computing device provided in an embodiment of the present application.
  • the computing device provided in the embodiment of the present application includes a first circuit board 100 and a mainboard 200.
  • the mainboard 200 is provided with a first card slot 300.
  • the first card slot can be an OCP slot, which can be plugged into an OCP card or the first circuit board 100 in the embodiment of the present application.
  • the first circuit board 100 provided in the embodiment of the present application can be used as an M.2 carrier board.
  • the embodiment of the present application does not specifically limit the number of M.2 connectors provided thereon.
  • One M.2 connector can be provided, or multiple M.2 connectors can be provided.
  • the M.2 connector can be inserted into SATA or NVMe. See Figure 1C, which is a schematic diagram of another computing device provided in the embodiment of the present application.
  • the computing device provided in the embodiment of the present application includes: a first card slot (not shown), a first circuit board 100 and a mainboard (MB) 200; the following description will be made using the computing device as a server as an example.
  • the OCP card slot is used to plug in the first circuit board 100; it should be understood that the first card slot is located on the side of the chassis of the server, which is not shown in Figure 1C.
  • the first circuit board 100 can be directly inserted into the first card slot.
  • a chassis is provided with multiple first card slots, and there will be idle first card slots. Therefore, the embodiment of the present application utilizes the idle first card slot to plug in the OCP card designed in the embodiment of the present application.
  • the first circuit board 100 involved in the embodiment of the present application is different from the traditional OCP card.
  • the first circuit board 100 provided in the embodiment of the present application serves as an M.2 carrier board.
  • An M.2 connector is provided on the M.2 carrier board.
  • the M.2 carrier board can be connected to the motherboard to expand the storage device.
  • at least one M.2 SSD can be installed on the M.2 carrier board, for example, one M.2 SSD can be installed, or multiple M.2 SSDs can be installed.
  • SATA type SSDs and NVMe type SSDs can be installed on the carrier board.
  • the OCP card provided in the embodiment of the present application includes: a first M.2 connector 101 and a serial bus expander 103; the first M.2 connector 101 is used to connect a solid-state drive SSD (not shown in the figure); the first M.2 connector 101 provided in the embodiment of the present application can be connected to a SATA type SSD and can also be connected to an NVMe type SSD, that is, it is compatible with SATA type SSDs and NVMe type SSDs.
  • the mainboard 200 includes a BMC 202 .
  • the on-position pins of the first circuit board 100 are connected to BMC202; it should be understood that the on-position pins of the first circuit board 100 provided in the embodiment of the present application comply with the standard protocol of the OCP card, and the first circuit board 100 includes four on-position pins, namely the first on-position pin PRSNTB3#, the second on-position pin PRSNTB2#, the third on-position pin PRSNTB1# and the fourth on-position pin PRSNTB0#.
  • a first on-position pin PRSNTB3# and a second on-position pin PRSNTB2# are respectively connected to two IO pins of the BMC 202. Both the first on-position pin PRSNTB3# and the second on-position pin PRSNTB2# are grounded on the first circuit board 100.
  • a third on-position pin PRSNTB1# and a fourth on-position pin PRSNTB0# of the first circuit board 100 are respectively connected to two other IO pins of the BMC 202. That is, the other two IO pins within the BMC are connected to a high potential via a resistor or directly connected to a high potential.
  • the third on-position pin PRSNTB1# and the fourth on-position pin PRSNTB0# of the first circuit board 100 are both left floating on the first circuit board 100.
  • the serial bus expander 103 is typically an expansion interface for the Inter-Integrated Circuit (I2C) bus, used for serial communication between the first circuit board 100 and the BMC 202.
  • I2C is a serial communication bus that uses a multi-master-slave architecture.
  • the I2C serial communication bus generally includes two signal lines: a bidirectional data line (SDA) and a clock line (SCL).
  • SDA serial data lines
  • SCL clock lines
  • the in-position pin M2_PRSNT1# and the SSD type pin PEDET1 of the first M.2 connector 101 are both connected to the serial bus interface Searial Bus of the BMC through the serial bus expander 103.
  • BMC202 is used to determine whether the first circuit board 100 is in place by detecting the status of the in-place pin of the first circuit board 100.
  • the status of the in-place pin of the M.2 connector is detected to determine whether the SSD is in place.
  • the type of the SSD is obtained through the SSD type pin.
  • BMC 202 is configured to determine that first circuit board 100 is in place when the levels of two IO pins are low, that is, when the two IO pins connected to first on-position pin PRSNTB3# and second on-position pin PRSNTB2# are both low. Because first on-position pin PRSNTB3# and second on-position pin PRSNTB2# are both grounded on first circuit board 100, the levels of the two IO pins detected by BMC 202 are both low.
  • the above four in-position pins are compatible with the in-position detection of a standard OCP card, and the BMC can allocate PCIE bandwidth to the first circuit board 100 based on the detection of the four in-position pins.
  • the above describes the BMC's determination of the presence of the first circuit board 100.
  • the following describes the determination of the presence of an SSD when the first circuit board 100 is in place. Since the first circuit board 100 provided in this embodiment includes an M.2 connector for connecting to an SSD, the M.2 connector is included when the first circuit board 100 is in place. The only further determination is whether an SSD is connected to the M.2 connector.
  • the BMC202 on the motherboard can automatically identify whether the first M.2 connector 101 on the first circuit board 100 is connected to a SATA SSD or an NVMe SSD disk, and configure the interface to make the server compatible with both types of SSDs.
  • the BMC 202 when determining whether an SSD is plugged into the first M.2 connector 101 and the type of the plugged-in SSD, the BMC 202 reads the level of the presence pin M2_PRSNT1# of the first M.2 connector 101 through the serial bus expander 103 to determine whether the SSD is in place. Furthermore, the BMC 202 reads the SSD type pin PEDET1 through the serial bus expander 103 to determine whether the SSD type is SATA or NVMe.
  • the embodiments of the present application do not specifically limit the high and low level states of the presence pins.
  • the embodiments of the present application do not specifically limit the high and low level states of the SSD type pin PEDET1.
  • the level of the SSD type pin PEDET1 when the level of the SSD type pin PEDET1 is low, the SSD type is judged to be a SATA type; conversely, when the level of the SSD type pin PEDET1 is high, the SSD type is judged to be an NVMe type.
  • the first circuit board 100 is structurally replaceable without unpacking the computer, if an M.2 SSD fails, the first circuit board 100 can be removed and the M.2 SSD can be replaced without opening the computer chassis while the power is disconnected. This eliminates the need to plug and unplug cables and move the entire computing device out of the cabinet and disassemble it. Especially when the computing device is heavy, the pluggable maintenance method of this application brings great convenience to operation and maintenance.
  • the M.2 SSD carrier board in the form of an OCP card provided in the embodiment of the present application only occupies the space of an OCP card in size. There is no need to reserve dedicated space for the M.2 SSD carrier board in the chassis of the computing device in advance. At the same time, the M.2 SSD carrier board can be easily removed without opening the chassis of the computing device, thereby realizing maintenance of the M.2 SSD without unpacking the box.
  • motherboard 200 also includes a processor CPU and an integrated southbridge (Platform Controller Hub, PCH) 201.
  • PCH Platinum Controller Hub
  • the first M.2 connector 101 is connected to processor CPU 201 as an example.
  • CPU 201 has IO expansion capabilities. Typically, these IO expansion ports are compatible with multiple protocols. For example, the same IO port can support both PCIE and SATA protocols, and can be configured to implement different functions according to actual needs.
  • BIOS Basic Input/Output System
  • BIOS can also obtain information from BMC 202 and flexibly configure business system parameters based on this information.
  • the PCIE interface of the first M.2 connector 101 is connected to the CPU 201 .
  • the BMC 202 is also used to inform the CPU 201 of the SSD type.
  • CPU 201 is used to determine the protocol that matches the SSD type based on the SSD type.
  • SSD types include SATA and NVMe.
  • SATA-type SSDs only require one PCIE pin, such as PCIE X1/SATA0 as shown in FIG1 .
  • NVMe uses four PCIE pins, so CPU 201 configures a four-pin PCIE interface to connect to the first M.2 connector 101.
  • SATA-type SSDs and NVMe-type SSDs do not exist at the same time. Therefore, CPU 201 only requires four PCIE pins, as shown in FIG1C .
  • SATA uses one pin, PCIE X1/SATA0
  • NVMe uses four pins. That is, in addition to using PCIE X3, NVMe also shares PCIE X1/SATA0 with SATA.
  • the computing device provided in the embodiment of the present application utilizes an OCP card as an M.2 carrier board.
  • the OCP card is provided with an M.2 connector, and the M.2 connector can be used to plug in an SSD. Since the OCP card is located on the side of the chassis of the computing device, it can be directly plugged in and out. When the SSD or the M.2 connector fails, it can be directly plugged in and out for maintenance without disassembling the chassis.
  • the computing device provided in the embodiment of the present application utilizes the idle slot of the OCP card, so there is no need to reserve space inside the chassis of the computing device to set up an M.2 carrier board, thereby saving the internal space of the chassis.
  • the M.2 connector on the OCP card provided in the embodiment of the present application is compatible with SATA-type SSDs and NVMe-type SSDs, and has universal applicability.
  • M.2 connector is only compatible with NVMe SSDs and not SATA SSDs, its practical application scenarios would be limited. Since M.2 is mostly used for system drives in the industry, and SATA SSDs are widely used due to their strong software compatibility and ease of use, if it is only compatible with NVMe SSDs, its application would be significantly limited.
  • the M.2 connector provided in the embodiments of the present application is compatible with both SATA and NVMe SSDs, expanding its application scenarios and bringing greater convenience to practical use.
  • the OCP card provided in the embodiment of the present application uses one less PCIE M.2 adapter card, which can save costs because the PCIE slot is expanded from the motherboard through the PCIE M.2 adapter card, while the OCP card is directly inserted into the motherboard.
  • FIG. 2 is a schematic diagram of a SATA M.2 provided in an embodiment of the present application.
  • SATA M.2 has two key positions: B Key and M Key.
  • SATA M.2 is compatible with both Socket 2 and Socket 3 slots.
  • FIG. 3 is a schematic diagram of an NVMe M.2 provided in an embodiment of the present application.
  • NVMe M.2 includes a key, the M Key. NVMe M.2 is only compatible with Socket 3 slots.
  • the M.2 connector on the OCP card provided in the embodiment of the present application can be connected to both SATA key positions and NVMe key positions.
  • two M.2 connectors are set on the OCP card to connect two SSDs.
  • the following describes how to connect the OCP card to two SSDs.
  • FIG4 is a schematic diagram of another computing device provided in an embodiment of the present application.
  • the first circuit board 100 shown in FIG4 is further provided with a second M.2 connector 102 compared to the first circuit board 100 shown in FIG1 .
  • the second M.2 connector 102 includes a position pin M2_PRSNT2# and an SSD type pin PEDET2.
  • the computing device provided in the embodiment of the present application includes an OCP card including a first M.2 connector 101 and a second M.2 connector 102; the first M.2 connector 101 is used to connect to a first SSD, and the second M.2 connector 102 is used to connect to a second SSD; the first SSD and the second SSD serve as backups for each other; the in-position pin M2_PRSNT2# and the SSD type pin PEDET1 of the first M.2 connector are both connected to the serial bus interface Searial Bus of the BMC 202 through the serial bus expander 103.
  • the in-position pin M2_PRSNT2# and the SSD type pin PEDET2 of the second M.2 connector 102 are both connected to the serial bus interface Searial Bus of the BMC through the serial bus expander 103;
  • the first M.2 connector 101 includes a PCIE X4 pin, the PCIE X3 pin of the first M.2 connector 101 is connected to the CPU 201, and the remaining PCIE X1 pin of the first M.2 connector 101 is used as the SATA pin 0 to connect to the CPU 201;
  • the second M.2 connector 102 includes a PCIE X4 pin, the PCIE X3 pin of the second M.2 connector 102 is connected to the CPU 201, and the remaining PCIE X1 pin of the second M.2 connector 102 is used as the SATA pin 1 to connect to the CPU 201.
  • the BMC 202 reads the level of the presence pin M2_PRSNT2# of the second M.2 connector 101 through the serial bus expander 103 to determine whether the SSD is in place. Furthermore, the BMC 202 reads the SSD type pin PEDET2 through the serial bus expander 103 to determine whether the SSD type is SATA or NVMe.
  • the embodiments of the present application do not specifically limit the high and low level states of the presence pin.
  • the embodiments of the present application do not specifically limit the high and low level states of the SSD type pin PEDET2.
  • the embodiments of the present application do not specifically limit the high and low level states of the SSD type pin PEDET2.
  • the level of the SSD type pin PEDET2 when the level of the SSD type pin PEDET2 is low, the SSD type is determined to be SATA; conversely, when the level of the SSD type pin PEDET2 is high, the SSD type is determined to be NVMe.
  • the second M.2 connector 102 is also connected to the CPU 201 through a PCIE interface.
  • CPU 201 is used to determine the protocol that matches the SSD type based on the SSD type.
  • SSD types include SATA and NVMe.
  • SATA-type SSDs only require a single PCIE pin, such as PCIE X1/SATA1 as shown in FIG4 .
  • NVMe uses a four-pin PCIE interface, so CPU 201 configures a four-pin PCIE interface to connect to the second M.2 connector 102.
  • SATA-type SSDs and NVMe-type SSDs do not exist at the same time. Therefore, CPU 201 only requires a total of four PCIE pins, as shown in FIG4 .
  • SATA uses a single pin
  • NVMe uses PCIE X3 and also shares PCIE X1/SATA1.
  • a board identification (Board ID) is stored on the first circuit board 100.
  • the first circuit board 100 includes a memory chip, and the memory chip stores the Board ID.
  • BMC 202 is also used to read the Board ID through serial bus expander 103.
  • BMC 202 uses the Board ID information to determine the function of the inserted OCP card. Specifically, BMC 202 uses the Board ID to determine whether first circuit board 100 is an M.2 carrier board. If not, it configures the board as a standard OCP card.
  • BMC202 uses the four presence signals PRSNTB0#-PRSNTB3# of the first circuit board 100 to determine whether an OCP card is installed in the OCP slot, and then determines the type of the installed OCP card based on the Board ID on the OCP card. If the OCP card is a standard universal OCP card, the PCIE bandwidth can be allocated based on the signal combination of PRSNTB0#-PRSNTB3#.
  • BMC202 determines that an M.2 carrier board is installed based on the Board ID, it will then use the M2_PRSNT# and PEDET signals to determine whether an M.2 SSD card is installed on the M.2 carrier board and whether it is a SATA M.2 SSD or an NVMe M.2 SSD. If a SATA M.2 SSD is installed on the M.2 carrier board, BMC202 will notify the BIOS in CPU201 to configure the M.2 connector as a SATA interface. If an NVMe M.2 SSD is installed on the M.2 carrier board, BMC202 will notify the BIOS in CPU201 to configure the M.2 connector as a PCIE interface, thereby achieving compatibility with different types of M.2 SSDs.
  • two M.2 connectors can be set on the OCP card, and the BMC can automatically identify whether the M.2 connector of the OCP card is connected to a SATA SSD or an NVMe SSD disk, and configure the PCIE interface of the CPU accordingly, thereby achieving compatibility of the motherboard with the two types of SSDs.
  • the embodiments of the present application do not specifically limit the number of M.2 connectors provided on the OCP card. It can be one, two, or more. The above only introduces one M.2 connector and two M.2 connectors as examples. The working principle is similar when more M.2 connectors are included, and will not be repeated here.
  • an embodiment of the present application further provides a clock configuration method for a computing device, which is described in detail below with reference to the accompanying drawings.
  • FIG5 is a flowchart of a method for controlling a computing device provided in an embodiment of the present application.
  • the present application provides a control method for a computing device, wherein the computing device comprises: a first card slot, a first circuit board, and a motherboard; the first card slot is used to insert an OCP card; the OCP card comprises an M.2 connector; the M.2 connector is used to connect to a solid-state drive (SSD); the motherboard comprises a baseboard management controller (BMC); the in-position pin of the OCP card is connected to the BMC; the in-position pin and the SSD type pin of the M.2 connector are both connected to a serial bus interface of the BMC;
  • the method includes:
  • the BMC determines whether the first circuit board is in place according to the status of the in-place pin of the first circuit board;
  • the OCP card's presence pins are connected to the BMC. It should be understood that the OCP card's presence pins provided in this embodiment comply with the standard OCP card protocol.
  • the OCP card includes four presence pins. Two of these pins are grounded on the OCP card; the remaining pins are left floating on the OCP card.
  • the BMC determines that the OCP card is in place when the voltage level on these two IO pins is low.
  • the BMC reads the level of the M.2 connector's presence pin through the serial bus expander to determine whether the SSD is in place.
  • the BMC reads the level of the SSD type pin through the serial bus expander and finds it is low, it determines that the SSD type is SATA; conversely, when the level of the SSD type pin PEDET1 is high, it determines that the SSD type is NVMe.
  • the computing device control method provided by the embodiments of the present application allows the BMC to determine whether the OCP card is in place using the presence pin.
  • the BMC determines whether the SSD is in place by detecting the status of the presence pin of the M.2 connector.
  • the BMC obtains the SSD type using the SSD type pin.
  • the M.2 connector on the OCP card is compatible with both SATA and NVMe SSDs, offering universal compatibility, expanding SSD application scenarios, and greatly facilitating practical use.
  • the central processing unit CPU may determine a protocol matching the SSD type according to the SSD type; for example, the SSD types include SATA and NVMe.
  • control method provided in the embodiment of the present application, after step S501, further includes:
  • the board ID is read through the serial bus expander and used to determine whether the OCP card is an M.2 carrier board. If it is not an M.2 carrier board, the card is configured as a standard OCP card.
  • FIG6 is a flowchart of another method for controlling a computing device provided in an embodiment of the present application.
  • the BMC determines whether the first circuit board is in place according to the in-place pin signal of the first circuit board.
  • the power supply is turned on, the AC power is turned on and the BMC is started.
  • the side of the server chassis is provided with a first card slot, and determining whether the first circuit board is in place means determining whether the first circuit board is inserted into the first card slot.
  • the server will start according to the default logic and ignore the PCIE bandwidth configuration on the first card slot.
  • the first card slot can be an OCP card slot located on the rear side of the server.
  • serial bus expander expands the I2C bus.
  • the BMC If an SSD is present, the BMC reads the SSD type pin via the serial bus expander to determine whether the SSD is SATA or NVMe. If an SSD is not present, the CPU BIOS configures the bandwidth based on two x4 PCIe interfaces.
  • the BMC determines that no SSD is inserted into the M.2 connector, the BMC transmits the information that the SSD is not in place to the CPU BIOS.
  • S605 When the SSD is determined to be a SATA M.2 SSD, the BIOS in the CPU configures the bandwidth according to the two SATA interfaces to ensure that the SATA M.2 SSD is available.
  • multiple M.2 connectors can be set on the first circuit board, and the BMC can automatically identify whether the M.2 connector of the first circuit board is connected to a SATA SSD or an NVMe SSD disk, and configure the PCIE interface of the CPU accordingly, thereby achieving the motherboard's compatibility with the two types of SSDs.
  • the control method of the computing device provided in the embodiment of the present application is designed to design an M.2 carrier board with the same form as the OCP card (including the size and the physical size of the gold finger/connector connected to the motherboard is the same as the OCP card), and the M.2 carrier board is provided with an M.2 connector, which can be used to plug in the SSD. Since the OCP card slot is located on the side of the chassis of the computing device, it can be directly plugged in and out. When the SSD or M.2 connector fails, it can be directly plugged in and out for maintenance without disassembling the chassis.
  • the computing device provided in the embodiment of the present application utilizes the idle slot of the OCP card, so there is no need to reserve space inside the chassis of the computing device to set up the M.2 carrier board, thereby saving the internal space of the chassis.
  • the M.2 connector on the OCP card provided in the embodiment of the present application is compatible with SATA type SSDs and NVMe type SSDs, and has universal applicability.
  • M.2 is mostly used for system drives in the industry, and SATA SSDs are widely used due to their strong software compatibility and ease of use, if they are only compatible with NVMe SSDs, their applications would be significantly limited.
  • the M.2 connector provided in the embodiments of this application is compatible with both SATA and NVMe SSDs, expanding its application scenarios and bringing greater convenience to actual use.
  • the first circuit board provided in the embodiment of the present application uses one less PCIE M.2 adapter card, because the PCIE slot is extended from the motherboard through the PCIE M.2 adapter card, and the OCP card is directly inserted into the motherboard.
  • the OCP card-shaped M.2 carrier board provided in the embodiment of the present application uses one less PCIE M.2 adapter card, which can save costs.

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Abstract

本申请实施例提供一种计算设备及方法，计算设备包括：第一卡槽、第一电路板和主板；第一卡槽用于插接第一电路板；第一电路板包括：M.2连接器；M.2连接器用于连接固态硬盘SSD；主板包括基板管理控制器BMC；第一电路板的在位管脚连接BMC；M.2连接器的在位管脚和SSD类型管脚连接BMC的串行总线接口；BMC，用于检测第一电路板的在位管脚的状态判断第一电路板是否在位；在第一电路板在位时的情况下，根据M.2连接器的在位管脚的电平判断SSD是否在位，在SSD在位的情况下，通过SSD类型管脚的电平确定SSD的类型，能够节省机箱内部空间，维护方便，而且能够兼容SATA M.2接口和NVMe M.2接口。

Description

计算设备及控制方法
本申请要求于2024年4月11日提交中国国家知识产权局、申请号为202410437270.2、申请名称为“一种计算设备及控制方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本申请实施例涉及服务器技术领域，特别涉及一种计算设备及控制方法。
背景技术
目前，服务器中需要固态硬盘(Solid State Drives，SSD)存储文档或视频等文件，SSD通过M.2接口(Next Generation Form Factor，NGFF)连接服务器的主板，主板对SSD中的数据进行读写。M.2接口是一种替代迷你版串行高级技术附加装置接口(mini-Serial Advanced Technology Attachment，mSATA)的新型接口规范，可以兼容SATA和高速串行计算机扩展总线标准(peripheral component interconnect express，PCIE)。
M.2接口主要适配Socket 2插槽和Socket 3插槽。Socket 2插槽可以支持兼容SATA及PCIe x2通道接口的M.2 SSD，对应的键位为B Key，而Socket 3插槽则支持兼容PCIe x4通道接口的M.2 SSD，对应的键位为M Key。目前，SSD的接口包括SATA M.2接口和非易失性内存主机控制器接口(Non-Volatile Memory express，NVMe)M.2接口。SATA M.2接口可以插M Key和B Key两种类型的SSD，但是NVMe M.2接口仅可以插M Key类型的SSD。
现有技术中，M.2接口和SSD均设置在载板上，载板设置在服务器的机箱内部，占用机箱内部的空间，而且载板在SSD出现问题时，必须拆开机箱，维护比较困难，而且，目前的M.2接口无法兼容SATA M.2接口和NVMe M.2接口。
发明内容
本申请实施例提供一种计算设备及控制方法，能够节省机箱内部空间，维护方便，而且能够兼容SATA M.2接口和NVMe M.2接口。
本申请实施例提供一种计算设备，包括：第一卡槽、第一电路板和主板；所述第一卡槽用于插接所述第一电路板；所述第一电路板包括：M.2连接器；所述M.2连接器用于连接固态硬盘SSD；所述主板包括基板管理控制器BMC；所述第一电路板的在位管脚连接所述BMC；所述M.2连接器的在位管脚和SSD类型管脚连接所述BMC的串行总线接口；所述BMC，用于检测所述第一电路板的在位管脚的状态判断所述第一电路板是否在位；在所述第一电路板在位时的情况下，根据所述M.2连接器的在位管脚的电平判断所述SSD是否在位，在所述SSD在位的情况下，通过所述SSD类型管脚的电平确定所述SSD的类型。
本申请实施例为了解决节省机箱内部空间，便于维护SSD和M.2连接器，并且M.2连接器可以兼容SATA还是NVMe两种类型的接口，在第一卡槽插接新设计的第一电路板，在第一电路板上设计了M.2连接器和串行总线扩展设备，第一电路板的在位管脚连接服务器主板上的BMC；所述M.2连接器的在位管脚和SSD类型管脚均通过所述串行总线扩展设备连接所述BMC的串行总线接口；BMC通过检测在位管脚的状态来判断第一电路板上的SSD是否在位，当SSD在位时，继续判断SSD的类型是SATA还是NVMe，可以兼容两种类型的SSD，扩大了应用场景，使用更加灵活。
一种可能的实现方式，所述主板还包括：中央处理器；所述M.2连接器连接所述中央处理器；所述BMC，还用于将所述SSD类型告知所述中央处理器；所述中央处理器，用于根据所述SSD类型确定与所述SSD类型匹配的协议，所述协议包括串行高级技术附加装置接口SATA协议和非易失性内存主机控制器接口NVMe协议。
由于第一电路板在结构上可以进行不开箱更换，因此，如果有M.2 SSD出现故障时，可以在整机断开电源的情况下不开机箱，便可以拆下第一电路板对M.2 SSD进行更换，免去插拔线缆和把整个计算设备搬下机柜并进行拆机的工作，尤其是在计算设备整机很重的情况下，本申请可插拔式地维护方式，为运维带来很大便利。本申请实施例提供的OCP卡形态的M.2 SSD载板，在尺寸上只占用一个OCP卡的空间，不用预先在计算设备的机箱内为M.2 SSD载板预留专用的空间，同时，可以在不打开计算设备的机箱的情况下，方便拆下M.2 SSD载板，实现不开箱对M.2 SSD进行维护。
一种可能的实现方式，所述M.2连接器包括第一M.2连接器和第二M.2连接器，所述第一电路板还包括串行总线扩展器；所述第一M.2连接器用于连接第一SSD，所述第二M.2连接器用于连接第二SSD；所述第一SSD和所述第二SSD互为备份；所述第一M.2连接器的在位管脚和SSD类型管脚均通过所述串行总线扩展器连接所述BMC的串行总线接口；所述第二M.2连接器的在位管脚和SSD类型管脚均通过所述串行总线扩展器连接所述BMC的串行总线接口；所述第一M.2连接器包括PCIE X4管脚，所述第一M.2连接器的PCIE X3管脚连接所述中央处理器，所述第一M.2连接器剩余的PCIE X1管脚作为SATA管脚连接所述中央处理器；所述第二M.2连接器包括PCIE X4管脚，所述第二M.2连接器的PCIE X3管脚连接所述中央处理器，所述第二M.2连接器剩余的PCIE X1管脚作为SATA管脚连接所述中央处理器。
一般情况下，为了实现数据备份，OCP卡上会设置两个M.2连接器，对应连接两个SSD，下面介绍OCP卡可以连接两个SSD的实现方式。本申请实施例提供的M.2连接器可以兼容SATA类型的SSD和NVMe类型的SSD，扩大了应用场景，给实际的使用带来了较大便利。
一种可能的实现方式，所述第一电路板的第一在位管脚和第二在位管脚分别连接所述BMC的两个IO管脚，所述第一在位管脚和所述第二在位管脚在所述第一电路板上均接地；所述第一电路板的第三在位管脚和第四在位管脚分别连接所述BMC的另外两个IO管脚；所述第一电路板的第三在位管脚和第四在位管脚在所述第一电路板上均悬空；所述BMC，用于在检测到与所述第一在位管脚和所述第二在位管脚连接的两个IO管脚的电平为低时，确定所述第一电路板在位。
本申请实施例不具体限定在位管脚的高低电平状态，例如一种可能的实现方式，在位管脚的电平为高电平时，判断SSD在位；反之在位管脚的电平为低电平时，判断SSD不在位。同理，本申请实施例也不具体限定SSD类型管脚的高低电平状态，例如一种可能的实现方式，SSD类型管脚的电平为低电平时，判断SSD类型为SATA类型；反之，SSD类型管脚的电平为高电平时，判断SSD类型为NVMe类型。
一种可能的实现方式，所述第一电路板上还存储有板ID；所述BMC，还用于读取所述板ID，通过所述板ID判断所述第一电路板是否为M.2载板，如果不是所述M.2载板，则按照标准OCP卡的带宽要求，使所述中央处理器对所述第一电路板进行配置。
BMC通过读取Board ID信息可以判断所插的OCP卡的功能。具体地，BMC通过Board ID判断第一电路板100是否为M.2载板，如果不是M.2载板，则按照标准OCP卡进行配置。
一种可能的实现方式，所述BMC，具体用于，在检测到所述SSD类型管脚的电平为高电平时，确定所述SSD类型为NVMe；在检测到所述SSD类型管脚的电平为低电平时，确定所述SSD类型为SATA。
本申请实施例对于SSD类型管脚的高低电平不做具体限定，可以根据实际需要来设置。
基于以上实施例提供的一种计算设备，本申请实施例还提供一种计算设备的控制方法，所述计算设备包括：第一卡槽、第一电路板和主板；所述第一卡槽用于插接所述第一电路板；所述第一电路板包括：M.2连接器；所述M.2连接器用于连接固态硬盘SSD；所述主板包括基板管理控制器BMC；所述第一电路板的在位管脚连接所述BMC；所述M.2连接器的在位管脚和所述M.2连接器的SSD类型管脚均连接所述BMC的串行总线接口；该方法包括：根据所述第一电路板的在位管脚的电平判断所述第一电路板是否在位；在所述第一电路板在位的情况下，根据所述M.2连接器的在位管脚的电平判断所述SSD是否在位；在所述SSD在位的情况下，通过所述SSD类型管脚的电平确定所述SSD的类型。
一种可能的实现方式，本申请实施例提供的方法，还包括：根据所述SSD类型确定与所述SSD类型匹配的协议；所述协议包括串行高级技术附加装置接口SATA协议和非易失性内存主机控制器接口NVMe协议。
一种可能的实现方式，本申请实施例提供的方法，所述第一电路板上还存储有板ID，所述方法还包括：读取所述板ID，通过所述板ID判断所述第一电路板是否为M.2载板，如果不是所述M.2载板，则按照标准OCP卡的带宽要求，使所述中央处理器对所述第一电路板进行配置。
一种可能的实现方式，本申请实施例提供的方法，所述通过所述SSD类型管脚的电平确定所述SSD的类型，具体包括：在检测到所述SSD类型管脚的电平为高电平时，确定所述SSD类型为NVMe；在检测所述SSD类型管脚的电平为低电平时，确定所述SSD类型为SATA。
附图说明
图1A本申请实施例提供的一种计算设备的示意图；
图1B本申请实施例提供的另一种计算设备的示意图；
图1C为本申请实施例提供的再一种计算设备的示意图；
图2为本申请实施例提供的一种SATA M.2的示意图；
图3为本申请实施例提供的一种NVMe M.2的示意图；
图4为本申请实施例提供的又一种计算设备的示意图；
图5为本申请实施例提供的一种计算设备的控制方法的流程图；
图6为本申请实施例提供的又一种计算设备的控制方法的流程图。
具体实施方式
本申请实施例提供的计算设备不具体限定应用的场景，例如，计算设备以服务器为例进行介绍，具体也不限定服务器的类型，例如计算设备可以为服务器。服务器可以位于数据中心，也可以位于其他区域，本申请实施例不做具体限定。
服务器，属于一种计算设备，服务器比普通计算机运行更快、负载更高。服务器在网络中为其它客户机(如PC机、智能手机等设备)提供计算或者应用服务。服务器具有高速的CPU运算能力、长时间的可靠运行、强大的外部数据吞吐能力以及更好的扩展性。服务器从外形分为机架式、刀片式、塔式和机柜式；服务器从功能上还可以包括AI服务器，例如GPU服务器等。
单板，服务器中的常用部件，单板可以理解为是一个对电路板的统称，可以为主板、电源管理板、网络数据交换板等多种形式。单板上可以设置有其他元器件，例如控制器，处理器，或者其他芯片，以实现服务器的运算功能。单板上还可以设置有电连接器，单板可以通过电连接器插接其他电器元件，或者通过电连接器与另一块单板电连接。
服务器可以包括单板和供电电源，供电电源用于给单板上的各个负载进行供电；负载可以是设置在单板上的中央处理器、内存、基板管理控制器等。
本申请实施例不具体限定单板的种类，单板可以为主板，也可以为其他单板。
主板，服务器中的一种电路板，主板上可以设置控制器、内存条、电连接器等部件。控制器可以包括中央处理器(central processing unit，CPU)、南桥芯片PCH、微控制单元(micro controller unit，MCU)、复杂可编程逻辑器件(complex programming logic device，CPLD)、现场可编程逻辑门阵列(field programmable gate array，FPGA)等。其中，CPU可以通过主板上的内部走线以及电连接器来电连接外围设备，例如CPU通过电连接器电连接网卡、显卡等设备。一般服务器的主板上可设置CPU、PCH和CPLD，其中，CPU可以为一个或多个。
本申请实施例不具体限定内存条的具体类型，例如内存条包括但不限定以下类型：双列直插式存储模块(dual-inline-memory-modules，DIMM)、单列直插存储器模块(single inline memory module，SIMM)。其中DIMM上的内存芯片可以是同步动态随机存储器(Synchronous Dynamic Random Access Memory，SDRAM)、第四代双倍速率同步动态随机存储器(Double Data Rate Synchronous Dynamic Random Access Memory4，DDR4)、第五代双倍速率同步动态随机存储器(Double Data Rate Synchronous Dynamic Random Access Memory5，DDR5)。
基板管理控制器(Baseboard Manager Controller，BMC)可以设置在主板上。
BMC是服务器必不可少的组件，用于监控该服务器的运作状况，如温度、风扇转速、供电状况、作业系统状态等等。BMC独立于服务器运作，不受服务器影响，可以在服务器未开机的待机状态下，对服务器进行固件升级、查看机器设备、远程控制机器开机等一些操作，可以在服务器宕机时记录关键日志。
SSD，固态硬盘又称固态驱动器，是用固态电子存储芯片阵列制成的硬盘。
开源计算项目(Open Compute Project，OCP)卡，针对数据中心定制的硬件设计规范，包括机房、机柜、服务器、存储、网络设备的定制设计规范，以及云端硬件的管理规范。OCP卡是一种开放式计算项目的网络接口卡。服务器机箱的侧面一般包括多个第一卡槽，但是一般的部分第一卡槽空缺，没有插入OCP卡。
本申请实施例为了解决节省机箱内部空间，便于维护SSD和M.2连接器，并且M.2连接器可以兼容SATA还是NVMe两种类型的接口，在第一卡槽插接新设计的第一电路板，第一电路板跟现有的OCP卡的尺寸大小以及接口形状一样，还可以是M.2载板。在第一电路板上设计了M.2连接器和串行总线扩展器，第一电路板的在位管脚连接服务器主板上的BMC；所述M.2连接器的在位管脚和SSD类型管脚均通过所述串行总线扩展器连接所述BMC的串行总线接口；BMC通过检测在位管脚的状态来判断第一电路板上的SSD是否在位，当SSD在位时，继续判断SSD的类型是SATA还是NVMe。
为了使本领域技术人员更好地理解本申请实施例提供的技术方案，下面结合附图进行详细介绍。
参见图1A，该图为本申请实施例提供的一种计算设备的示意图。
服务器1000机箱的侧面一般包括多个第一卡槽，例如，第一卡槽可以用来插接OCP卡，但是一般服务器1000的第一卡槽存在空缺，没有插入OCP卡。本申请可以使用空缺的第一卡槽来插接本申请实施例提供的第一电路板100。第一电路板100与现有的OCP卡的尺寸大小以及接口形状都一样，还可以是M.2载板。
参见图1B，该图为本申请实施例提供的另一种计算设备的示意图。
本申请实施例提供的计算设备，包括第一电路板100和主板200，主板200设有第一卡槽300，例如第一卡槽可以为OCP槽位，可以插接OCP卡，也可以插接本申请实施例中的第一电路板100。本申请实施例提供的第一电路板100可以作为M.2的载板，本申请实施例不具体限定上设置的M.2连接器的数量，可以设置一个M.2连接器，也可以设置多个M.2连接器。M.2连接器可以插入SATA，也可以插入NVMe。参见图1C，该图为本申请实施例提供的再一种计算设备的示意图。
本申请实施例提供的计算设备，包括：第一卡槽(未示出)、第一电路板100和主板(Mainboard，MB)200；下面以计算设备为服务器为例进行介绍。
OCP卡槽位用于插接第一电路板100；应该理解，第一卡槽位于服务器的机箱的侧面，图1C未示出，第一电路板100可以直接插入第一卡槽。一般机箱设置多个第一卡槽，会有闲置的第一卡槽，因此，本申请实施例就是利用闲置的第一卡槽，插接本申请实施例设计的OCP卡，应该理解，本申请实施例涉及的第一电路板100区别于传统的OCP卡。本申请实施例提供的第一电路板100是作为M.2载板，M.2载板上设置M.2连接器，M.2载板可以连接主板，用来扩展存储设备。例如，M.2载板上可以安装至少一个M.2 SSD，例如可以安装一个M.2 SSD，也可以安装多个M.2 SSD。载板上可以安装SATA类型的SSD和NVMe类型的SSD。
如图1C所示，本申请实施例提供的OCP卡包括：第一M.2连接器101和串行总线扩展器103；第一M.2连接器101用于连接固态硬盘SSD(图中未示出)；本申请实施例提供的第一M.2连接器101可以连接SATA类型的SSD，又可以连接NVMe类型的SSD，即可以兼容SATA类型的SSD和NVMe类型的SSD。
主板200包括BMC202。
第一电路板100的在位管脚连接BMC202；应该理解，本申请实施例提供的第一电路板100的在位管脚遵从OCP卡的标准协议，第一电路板100包括四个在位管脚，分别为第一在位管脚PRSNTB3#，第二在位管脚PRSNTB2#，第三在位管脚PRSNTB1#和第四在位管脚PRSNTB0#。
一种可能的实现方式，第一在位管脚PRSNTB3#和第二在位管脚PRSNTB2#分别连接所述BMC202的两个IO管脚，第一在位管脚PRSNTB3#和第二在位管脚PRSNTB2#在第一电路板100上均接地；第一电路板100的第三在位管脚PRSNTB1#和第四在位管脚PRSNTB0#分别连接BMC202的另外两个IO管脚，即在BMC内部另外两个IO管脚通过电阻连接高电位，或直接连接高电位。第一电路板100的第三在位管脚PRSNTB1#和第四在位管脚PRSNTB0#在第一电路板100上均悬空。
串行总线扩展器103一般为集成电路总线(Inter-Integrated Circuit，I2C)的扩展接口，用于第一电路板100与BMC202的串行通信。I2C是一种串行通信总线，使用多主从架构。I2C串行通信总线一般包括两根信号线，一根是双向的数据线SDA，另一根是时钟线SCL。所有接到I2C总线设备上的串行数据SDA都接到总线的SDA上，各设备的时钟线SCL接到总线的SCL上。
第一M.2连接器101的在位管脚M2_PRSNT1#和SSD类型管脚PEDET1均通过串行总线扩展器103连接BMC的串行总线接口Searial Bus。
BMC202，用于通过检测第一电路板100的在位管脚的状态来判断第一电路板100是否在位，当第一电路板100在位时，检测M.2连接器的在位管脚的状态判断SSD是否在位，当SSD在位时，通过SSD类型管脚获得SSD的类型。
BMC202，用于检测两个IO管脚的电平为低时，即，检测连接第一在位管脚PRSNTB3#和第二在位管脚PRSNTB2#的两个IO管脚均为低电平时，判断第一电路板100在位。因为，在第一电路板100上第一在位管脚PRSNTB3#和第二在位管脚PRSNTB2#均接地，BMC202识别的两个IO管脚的电平状态均为低电平。
以上四个在位管脚兼容标准OCP卡的在位检测。并且BMC根据四个在位管脚的检测，可以为第一电路板100分配PCIE带宽。
以上介绍的是BMC判断第一电路板100在位的情况，下面介绍，当第一电路板100在位时，继续判断SSD在位的情况。由于本申请实施例提供的第一电路板100包括用于连接SSD的M.2连接器，因此，当第一电路板100在位时，就包括M.2连接器，仅是需要进一步判断M.2连接器上是否连接有SSD。
主板上的BMC202可以自动识别第一电路板100上的第一M.2连接器101连接的是SATA SSD还是NVMe SSD盘，并对接口进行配置，以此实现服务器对两种类型的SSD进行兼容。
具体地，在判断第一M.2连接器101上是否插接有SSD以及插接的SSD的类型时，BMC202通过串行总线扩展器103读取第一M.2连接器101的在位管脚M2_PRSNT1#的电平，判断SSD在位。并且，BMC202通过串行总线扩展器103读取SSD类型管脚PEDET1，判断SSD的类型为SATA还是NVMe。本申请实施例不具体限定在位管脚的高低电平状态，例如一种可能的实现方式，在位管脚M2_PRSNT1#的电平为高电平时，判断SSD在位；反之在位管脚M2_PRSNT1#的电平为低电平时，判断SSD不在位。同理，本申请实施例也不具体限定SSD类型管脚PEDET1的高低电平状态，例如一种可能的实现方式，SSD类型管脚PEDET1的电平为低电平时，判断SSD类型为SATA类型；反之，SSD类型管脚PEDET1的电平为高电平时，判断SSD类型为NVMe类型。
由于第一电路板100在结构上可以进行不开箱更换，因此，如果有M.2 SSD出现故障时，可以在整机断开电源的情况下不开机箱，便可以拆下第一电路板100对M.2 SSD进行更换，免去插拔线缆和把整个计算设备搬下机柜并进行拆机的工作，尤其是在计算设备整机很重的情况下，本申请可插拔式地维护方式，为运维带来很大便利。
本申请实施例提供的OCP卡形态的M.2 SSD载板，在尺寸上只占用一个OCP卡的空间，不用预先在计算设备的机箱内为M.2 SSD载板预留专用的空间，同时，可以在不打开计算设备的机箱的情况下，方便拆下M.2 SSD载板，实现不开箱对M.2 SSD进行维护。
另外，主板200还包括处理器CPU和集成南桥(Platform Controller Hub，PCH)201。本申请实施例中以第一M.2连接器101连接处理器CPU201为例进行介绍。CPU201具有IO扩展能力，通常这些IO扩展端口可以兼容多种协议，例如，在同一个IO端口上可以同时支持PCIE和SATA两种协议，可以根据实际需要进行配置来实现不同的功能。
CPU201上还运行基本输入输出系统(Basic Input Output System，BIOS)，在计算设备业务系统启动过程中负责自检和参数配置。在启动过程中，BIOS也可以从BMC202获取信息，根据所获取的信息对业务系统中的参数做灵活配置。
第一M.2连接器101的PCIE接口连接CPU201。
BMC202，还用于将SSD类型告知CPU201。
CPU201，用于根据SSD类型确定与SSD类型匹配的协议，SSD类型包括SATA和NVMe。SATA类型的SSD仅用一个管脚的PCIE即可，如图1所示的PCIE X1/SATA0。NVMe用4个管脚的PCIE，因此，CPU201配置4个管脚的PCIE接口连接第一M.2连接器101，一般情况下，SATA类型的SSD和NVMe类型的SSD不会同时存在，因此，CPU201共配置4个PCIE管脚即可，如图1C所示，其中SATA用一个管脚PCIE X1/SATA0，NVMe使用四个管脚，即NVMe除了使用PCIE X3以外，还与SATA共用PCIE X1/SATA0。
本申请实施例提供的计算设备，利用OCP卡作为M.2的载板，OCP卡上设有M.2连接器，M.2连接器可以用来插接SSD。由于OCP卡位于计算设备的机箱侧面，可以直接插拔，在SSD或者M.2连接器出现故障时，可以直接插拔进行维护，不需要拆开机箱。而且本申请实施例提供的计算设备，由于利用了OCP卡闲置的槽位，不必在计算设备的机箱内部专门预留空间设置M.2载板，从而可以节省机箱的内部空间。而且本申请实施例提供的OCP卡上的M.2连接器可以兼容SATA类型的SSD和NVMe类型的SSD，具有普适性。
如果M.2连接器只能兼容NVMe SSD，不兼容SATA SSD，则实际应用场景受到限制。由于M.2在业界多用于系统盘，SATA SSD因为软件兼容性强，易使用，得到广泛的应用，如果只能兼容NVMe SSD，应用上有较大的局限性。本申请实施例提供的M.2连接器可以兼容SATA类型的SSD和NVMe类型的SSD，扩大了应用场景，给实际的使用带来了较大便利。
另外，本申请实施例提供的OCP卡与传统的PCIE的M.2转接卡相比，由于PCIE插槽是通过PCIE的M.2转接卡从主板上扩展出来，而OCP卡是直接插在主板上，相比较来说，本申请实施例提供的OCP卡形态的M.2载板少使用一个PCIE的M.2转接卡，可以节省成本。
为了方便理解，下面结合附图介绍SATA的键位和NVMe的键位的区别。
参见图2，该图为本申请实施例提供的一种SATA M.2的示意图。
SATA M.2包括两种键位，即包括B Key和M Key。SATA M.2可以适用于Socket 2、Socket 3两种插槽。
参见图3，该图为本申请实施例提供的一种NVMe M.2的示意图。
NVMe M.2包括一种键位，即斤包括M Key。NVMe M.2仅适用于Socket 3插槽。
本申请实施例提供的OCP卡上的M.2连接器既可以连接SATA的键位，又可以连接NVMe的键位。
一般情况下，为了实现数据备份，OCP卡上会设置两个M.2连接器，对应连接两个SSD，下面介绍OCP卡可以连接两个SSD的实现方式。
参见图4，该图为本申请实施例提供的又一种计算设备的示意图。
对比图4和图1可以发现，图4所示的第一电路板100相比图1所示的第一电路板100还多设置了第二M.2连接器102，第二M.2连接器102包括在位管脚M2_PRSNT2#和SSD类型管脚PEDET2。
本申请实施例提供的计算设备，OCP卡包括第一M.2连接器101和第二M.2连接器102；第一M.2连接器101用于连接第一SSD，第二M.2连接器102用于连接第二SSD；第一SSD和所述第二SSD互为备份；第一M.2连接器的在位管脚M2_PRSNT2#和SSD类型管脚PEDET1均通过串行总线扩展器103连接BMC202的串行总线接口Searial Bus。第二M.2连接器102的在位管脚M2_PRSNT2#和SSD类型管脚PEDET2均通过串行总线扩展器103连接BMC的串行总线接口Searial Bus；
第一M.2连接器101包括PCIE X4管脚，第一M.2连接器101的PCIE X3管脚连接CPU201，第一M.2连接器101剩余的PCIE X1管脚作为SATA管脚0连接CPU201；第二M.2连接器102包括PCIE X4管脚，第二M.2连接器102的PCIE X3管脚连接CPU201，第二M.2连接器102剩余的PCIE X1管脚作为SATA管脚1连接CPU201。
BMC202通过串行总线扩展器103读取第二M.2连接器101的在位管脚M2_PRSNT2#的电平，判断SSD在位。并且，BMC202通过串行总线扩展器103读取SSD类型管脚PEDET2，判断SSD的类型为SATA还是NVMe。
本申请实施例不具体限定在位管脚的高低电平状态，例如一种可能的实现方式，在位管脚M2_PRSNT2#的电平为高电平时，判断SSD在位；反之在位管脚M2_PRSNT2#的电平为低电平时，判断SSD不在位。同理，本申请实施例也不具体限定SSD类型管脚PEDET2的高低电平状态，例如一种可能的实现方式，SSD类型管脚PEDET2的电平为低电平时，判断SSD类型为SATA类型；反之，SSD类型管脚PEDET2的电平为高电平时，判断SSD类型为NVMe类型。
另外，第二M.2连接器102还通过PCIE接口连接CPU201。
CPU201，用于根据SSD类型确定与SSD类型匹配的协议，SSD类型包括SATA和NVMe。SATA类型的SSD仅用一个管脚的PCIE即可，如图4所示的PCIE X1/SATA1。NVMe用4个管脚的PCIE，因此，CPU201配置4个管脚的PCIE接口连接第二M.2连接器102，一般情况下，SATA类型的SSD和NVMe类型的SSD不会同时存在，因此，CPU201共配置4个PCIE管脚即可，如图4所示，其中SATA用一个管脚PCIE X1/SATA1，NVMe除了使用PCIE X3以外，还共用PCIE X1/SATA1。
本申请实施例提供的计算设备，第一电路板100上存储包括板标识(Board Identity，Board ID)。例如，第一电路板100包括存储芯片，存储芯片中存有Board ID。
BMC202，还用于通过串行总线扩展器103读取Board ID，BMC202通过读取Board ID信息可以判断所插的OCP卡的功能。具体地，BMC202通过Board ID判断第一电路板100是否为M.2载板，如果不是M.2载板，则按照标准OCP卡进行配置。
BMC202通过第一电路板100的四个在位信号PRSNTB0#-PRSNTB3#信号，判断OCP插槽上是否有OCP卡安装上去，再根据OCP卡上的Board ID来判断安装的OCP卡的类型，如果OCP卡是标准通用的OCP卡，可以根据PRSNTB0#-PRSNTB3#的信号组合对PCIE带宽进行分配。
如果BMC202根据Board ID判断安装的是M.2载板，则BMC202会继续根据上述M2_PRSNT#和PEDET信号判断M.2 SSD卡是否安装在M.2载板上，安装的是SATA M.2SSD还是NVMe M.2 SSD。如果M.2载板上安装的是SATA M.2 SSD，BMC202需要通知CPU201中的BIOS将M.2连接器配置为SATA接口，如果M.2载板上安装的是NVMe M.2SSD，则BMC202通知CPU201中的BIOS把M.2连接器配置成PCIE接口，从而实现对不同类型M.2 SSD的兼容。
本申请实施例提供的计算设备，OCP卡上可以设置两个M.2连接器，而且BMC可以自动识别OCP卡的M.2连接器上连接的是SATA SSD还是NVMe SSD盘，并对CPU的PCIE接口进行对应的配置，实现主板对两种类型的SSD的兼容。
应该理解，本申请实施例不具体限定OCP卡上设置的M.2连接器的数量，可以为一个，也可以为两个，也可以为更多个，以上仅是分别以一个M.2连接器和两个M.2连接器为例进行了介绍，当包括更多个时的工作原理类似，在此不再赘述。
基于以上实施例提供的一种计算设备，本申请实施例还提供一种计算设备的时钟配置方法，下面结合附图进行详细介绍。
参见图5，该图为本申请实施例提供的一种计算设备的控制方法的流程图。
本申请实施例提供的计算设备的控制方法，计算设备包括：第一卡槽、第一电路板和主板；第一卡槽用于插接OCP卡；OCP卡包括：M.2连接器；M.2连接器用于连接固态硬盘SSD；主板包括基板管理控制器BMC；OCP卡的在位管脚连接BMC；M.2连接器的在位管脚和SSD类型管脚均连接BMC的串行总线接口；
该方法包括：
S501：BMC根据第一电路板的在位管脚的状态判断第一电路板是否在位；
OCP卡的在位管脚连接BMC；应该理解，本申请实施例提供的OCP卡的在位管脚遵从OCP卡的标准协议，OCP卡包括四个在位管脚。有两个在位管脚在OCP卡上均接地；管脚在OCP卡上悬空。BMC检测两个IO管脚的电平为低时，判断OCP卡在位。
S502：在第一电路板在位的情况下，BMC根据M.2连接器的在位管脚的状态判断SSD是否在位；
BMC通过串行总线扩展器读取M.2连接器的在位管脚的电平，判断SSD是否在位。
S503：在SSD在位的情况下，BMC通过SSD类型管脚获得SSD的类型。
例如，BMC通过串行总线扩展器读取SSD类型管脚的电平为低电平时，判断SSD类型为SATA类型；反之，SSD类型管脚PEDET1的电平为高电平时，判断SSD类型为NVMe类型。
本申请实施例提供的计算设备的控制方法，BMC可以通过在位管脚判断OCP卡是否在位，当OCP卡在位时，通过检测M.2连接器的在位管脚的状态判断SSD是否在位；当SSD在位时，BMC通过SSD类型管脚获得SSD的类型。OCP卡上的M.2连接器可以兼容SATA类型的SSD和NVMe类型的SSD，具有普适性，扩大了SSD的应用场景，给实际的使用带来了较大便利。
中央处理器CPU可以根据SSD类型确定与SSD类型匹配的协议；例如，SSD类型包括SATA和NVMe。
一种可能的实现方式，本申请实施例提供的控制方法，在上述步骤S501之后，上述控制方法还包括：
通过串行总线扩展器读取板ID，通过板ID判断OCP卡是否为M.2载板，如果不是M.2载板，则按照标准OCP卡进行配置。
为了本领域技术人员更好地理解和实施本申请实施例提供的技术方案，下面结合附图介绍一种BMC识别OCP卡完整的流程。
参见图6，该图为本申请实施例提供的又一种计算设备的控制方法的流程图。
本申请实施例提供的计算设备的控制方法，包括：
S601：BMC根据第一电路板的在位管脚信号，判断第一电路板是否在位。
计算设备的硬件系统部署完成后接通电源，交流上电启动，BMC启动。应该理解，服务器的机箱的侧面设有第一卡槽，判断第一电路板是否在位即判断第一卡槽是否插有第一电路板。
如果没有第一电路板，服务器将按照默认逻辑启动，忽略第一卡槽上的PCIE带宽配置。第一卡槽可以为位于服务器后侧面的OCP卡槽位。
例如，串行总线扩展器扩展的为I2C总线。
S602：在第一电路板在位的情况下，则BMC通过串行总线扩展器读取第一电路板的Board ID，判断第一电路板是否为M.2转接卡。
S603：在第一电路板为M.2转接卡的情况下，BMC通过串行总线扩展器读取M.2连接器的在位管脚，判断SSD是否在位。
S604：在SSD在位的情况下，BMC通过串行总线扩展器读取SSD的类型管脚，判断SSD类型是SATA还是NVMe。如果SSD不在位，则CPU中的BIOS按照两个X4 PCIE接口进行配置带宽。
如果BMC判断M.2连接器没有插SSD，则BMC将SSD未在位的信息传递给CPU的BIOS。
S605：当判断SSD是SATA M.2 SSD时，CPU中的BIOS按照两个SATA接口进行配置带宽，保障SATA M.2 SSD可用。
S606：当判断SSD是NVMe M.2 SSD时，CPU中的BIOS按照两个X4 PCIE接口进行配置带宽，保障NVMe M.2 SSD可用。
本申请实施例提供的计算设备的控制方法，第一电路板上可以设置多个M.2连接器，而且BMC可以自动识别第一电路板的M.2连接器上连接的是SATA SSD还是NVMe SSD盘，并对CPU的PCIE接口进行对应的配置，实现主板对两种类型的SSD的兼容。
本申请实施例提供的计算设备的控制方法，设计与OCP卡形态相同(包括尺寸大小以及与主板连接的金手指/连接器的物理尺寸与OCP卡相同)的M.2的载板，并且该M.2载板上设有M.2连接器，M.2连接器可以用来插接SSD。由于OCP卡槽位于计算设备的机箱侧面，可以直接插拔，在SSD或者M.2连接器出现故障时，可以直接插拔进行维护，不需要拆开机箱。而且本申请实施例提供的计算设备，由于利用了OCP卡闲置的槽位，不必在计算设备的机箱内部专门预留空间设置M.2载板，从而可以节省机箱的内部空间。而且本申请实施例提供的OCP卡上的M.2连接器可以兼容SATA类型的SSD和NVMe类型的SSD，具有普适性。
由于M.2在业界多用于系统盘，SATA SSD因为软件兼容性强，易使用，得到广泛的应用，如果只能兼容NVMe SSD，应用上有较大的局限性。本申请实施例提供的M.2连接器可以兼容SATA类型的SSD和NVMe类型的SSD，扩大了应用场景，给实际的使用带来了较大便利。
另外，本申请实施例提供的第一电路板与传统的PCIE的M.2转接卡相比，由于PCIE插槽是通过PCIE的M.2转接卡从主板上扩展出来，而OCP卡是直接插在主板上，相比较来说，本申请实施例提供的OCP卡形态的M.2载板少使用一个PCIE的M.2转接卡，可以节省成本。
以上所述，仅是本申请的较佳实施例而已，并非对本申请作任何形式上的限制。虽然本申请已以较佳实施例揭露如上，然而并非用以限定本申请。任何熟悉本领域的技术人员，在不脱离本申请技术方案范围情况下，都可利用上述揭示的方法和技术内容对本申请技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本申请技术方案保护的范围内。

Claims (10)

  1. 一种计算设备，其特征在于，包括：第一卡槽、第一电路板和主板；
    所述第一卡槽用于插接所述第一电路板；
    所述第一电路板包括：M.2连接器；所述M.2连接器用于连接固态硬盘SSD；
    所述主板包括基板管理控制器BMC；
    所述第一电路板的在位管脚连接所述BMC；
    所述M.2连接器的在位管脚和所述M.2连接器的SSD类型管脚连接所述BMC的串行总线接口；
    所述BMC，用于检测所述第一电路板的在位管脚的状态判断所述第一电路板是否在位；在所述第一电路板在位时的情况下，根据所述M.2连接器的在位管脚的电平判断所述SSD是否在位，在所述SSD在位的情况下，通过所述SSD类型管脚的电平确定所述SSD的类型。
  2. 根据权利要求1所述的计算设备，其特征在于，所述主板还包括：中央处理器；
    所述M.2连接器连接所述中央处理器；
    所述BMC，还用于将所述SSD类型告知所述中央处理器；
    所述中央处理器，用于根据所述SSD类型确定与所述SSD类型匹配的协议，所述协议包括串行高级技术附加装置接口SATA协议和非易失性内存主机控制器接口NVMe协议。
  3. 根据权利要求1所述的计算设备，其特征在于，所述M.2连接器包括第一M.2连接器和第二M.2连接器，所述第一电路板还包括串行总线扩展器；
    所述第一M.2连接器用于连接第一SSD，所述第二M.2连接器用于连接第二SSD；
    所述第一SSD和所述第二SSD互为备份；
    所述第一M.2连接器的在位管脚和SSD类型管脚均通过所述串行总线扩展器连接所述BMC的串行总线接口；
    所述第二M.2连接器的在位管脚和SSD类型管脚均通过所述串行总线扩展器连接所述BMC的串行总线接口；
    所述第一M.2连接器包括PCIE X4管脚，所述第一M.2连接器的PCIE X3管脚连接所述中央处理器，所述第一M.2连接器剩余的PCIE X1管脚作为SATA管脚连接所述中央处理器；
    所述第二M.2连接器包括PCIE X4管脚，所述第二M.2连接器的PCIE X3管脚连接所述中央处理器，所述第二M.2连接器剩余的PCIE X1管脚作为SATA管脚连接所述中央处理器。
  4. 根据权利要求1所述的计算设备，其特征在于，所述第一电路板的第一在位管脚和第二在位管脚分别连接所述BMC的两个IO管脚，所述第一在位管脚和所述第二在位管脚在所述第一电路板上均接地；所述第一电路板的第三在位管脚和第四在位管脚分别连接所述BMC的另外两个IO管脚；所述第一电路板的第三在位管脚和第四在位管脚在所述第一电路板上均悬空；
    所述BMC，用于在检测到与所述第一在位管脚和所述第二在位管脚连接的两个IO管脚的电平为低时，确定所述第一电路板在位。
  5. 根据权利要求1-4任一项所述的计算设备，其特征在于，所述第一电路板上还存储有板ID；
    所述BMC，还用于读取所述板ID，通过所述板ID判断所述第一电路板是否为M.2载板，如果不是所述M.2载板，则按照标准OCP卡的带宽要求，使所述中央处理器对所述第一电路板进行配置。
  6. 根据权利要求1-4任一项所述的计算设备，其特征在于，所述BMC，具体用于，在检测到所述SSD类型管脚的电平为高电平时，确定所述SSD类型为NVMe；在检测到所述SSD类型管脚的电平为低电平时，确定所述SSD类型为SATA。
  7. 一种计算设备的控制方法，其特征在于，所述计算设备包括：第一卡槽、第一电路板和主板；所述第一卡槽用于插接所述第一电路板；所述第一电路板包括：M.2连接器；所述M.2连接器用于连接固态硬盘SSD；所述主板包括基板管理控制器BMC；所述第一电路板的在位管脚连接所述BMC；所述M.2连接器的在位管脚和所述M.2连接器的SSD类型管脚均连接所述BMC的串行总线接口；
    该方法包括：
    根据所述第一电路板的在位管脚的电平判断所述第一电路板是否在位；
    在所述第一电路板在位的情况下，根据所述M.2连接器的在位管脚的电平判断所述SSD是否在位；
    在所述SSD在位的情况下，通过所述SSD类型管脚的电平确定所述SSD的类型。
  8. 根据权利要求7所述的控制方法，其特征在于，还包括：
    根据所述SSD类型确定与所述SSD类型匹配的协议；所述协议包括串行高级技术附加装置接口SATA协议和非易失性内存主机控制器接口NVMe协议。
  9. 根据权利要求7所述的控制方法，其特征在于，所述第一电路板上还存储有板ID，所述方法还包括：
    读取所述板ID，通过所述板ID判断所述第一电路板是否为M.2载板，如果不是所述M.2载板，则按照标准OCP卡的带宽要求，使所述中央处理器对所述第一电路板进行配置。
  10. 根据权利要求1所述的计算设备，其特征在于，所述通过所述SSD类型管脚的电平确定所述SSD的类型，具体包括：
    在检测到所述SSD类型管脚的电平为高电平时，确定所述SSD类型为NVMe；在检测所述SSD类型管脚的电平为低电平时，确定所述SSD类型为SATA。
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