WO2025203026A1 - Multi-level current source inverter - Google Patents

Abstract

An inverter including: at least two parallel connected multi-level inverter cells for connection across a load, each cell comprising; two legs each including a complementary switch pair having two reverse-blocking switches; a DC-link inductor connecting the two legs between both switch pairs of the two legs in a h-bridge configuration, each of the four reverse-blocking switches positioned, when in an on state, to allow current to flow towards the DC-link inductor; a DC current source connected at a switch-inductor connection; a polarity control comprising a complementary switch pair, where the two cells are connected by their current sources between the polarity control switches, a state of the polarity control complementary switch pair determining direction of current through the load.

Description

MULTI-LEVEL CURRENT SOURCE INVERTER

RELATED APPLICATIONS

This application claims priority from U.S. Provisional Application No. 63/569,301, filed on 25 March 2024, the contents of which are incorporated by reference as if fully set forth herein.

TECHNOLOGICAL FIELD

The present disclosure, in some embodiments, thereof, relates to power conversion systems and, more particularly, but not exclusively, to multi-level current source inverters.

BACKGROUND ART

Background art, where each art is incorporated in its entirety by reference, includes the below list. In the following document these arts are referred to by number e.g. using the relevant reference number/s in square brackets: [number].

[1] F. A. Silva, "Power Electronics Handbook, Third Edition (Rashid, M.H.; 2011) [Book News]," in IEEE Industrial Electronics Magazine, vol. 5, no. 2, pp. 54-55, June 2011.

[2] I. Harbi et al., "Common DC-Link Multilevel Converters: Topologies, Control and Industrial Applications," in IEEE Open Journal of Power Electronics, vol. 4, pp. 512-538, 2023.

[3] J. Rodriguez et al., "Multilevel Converters: An Enabling Technology for High-Power Applications," in Proceedings of the IEEE, vol. 97, no. 11, pp. 1786-1817, Nov. 2009.

[4] K. K. Gupta, A. Ranjan, P. Bhatnagar, L. K. Sahu and S. Jain, "Multilevel Inverter Topologies With Reduced Device Count: A Review," in IEEE Transactions on Power Electronics, vol. 31, no. 1, pp. 135-151, Jan. 2016.

[5] N. Sandeep and U. R. Yaragatti, "Operation and Control of a Nine-Level Modified ANPC Inverter Topology With Reduced Part Count for Grid -Connected Applications," in IEEE Transactions on Industrial Electronics, vol. 65, no. 6, pp. 4810- 4818, June 2018 [6] N. Sandeep and U. R. Yaragatti, "Operation and Control of an Improved Hybrid Nine-Level Inverter," in IEEE Transactions on Industry Applications, vol. 53, no. 6, pp. 5676-5686, Nov.-Dec. 2017.

[7] K. J. Dagan, A. Zuckerberger and R. Rabinovici, "Fourth-Arm Common- Mode Voltage Mitigation," in IEEE Transactions on Power Electronics, vol. 31, no. 2, pp. 1401-1407, Feb. 2016.

[8] J. Holtz, "Pulsewidth modulation for electronic power conversion," in Proceedings of the IEEE, vol. 82, no. 8, pp. 1194-1214, Aug. 1994

[9] J. Bao, W. Bao, Z. Zhang and W. Fang, "A simple current-balancing method for a three-phase 5-level current- source inverter," 2009 35th Annual Conference of IEEE Industrial Electronics, Porto, Portugal, 2009, pp. 104-108.

[10] Shigeo Nagaya, Naoki Hirano, Toshio Katagiri, Tsutomu Tamada, Koji Shikimachi, Yu Iwatani, Fusao Saito, Yusuke Ishii,

[11] The state of the art of the development of SMES for bridging instantaneous voltage dips in Japan, Cryogenics, Volume 52, Issue 12, 2012, Pages 708-712.

[12] Li Jun, K. W. E. Cheng, D. Sutanto and DeHong Xu, "A multimodule hybrid converter for high-temperature superconducting magnetic energy storage systems (HT-SMES)," in IEEE Transactions on Power Delivery, vol. 20, no. 1, pp. 475-480, Jan. 2005.

[13] Z. C. Zhang and B. T. Ooi, "Multimodular current- source SPWM converters for a superconducting magnetic energy storage system," in IEEE Transactions on Power Electronics, vol. 8, no. 3, pp. 250-256, July 1993.

[14] V. Karasik, K. Dixon, C. Weber, B. Batchelder, G. Campbell and P. Ribeiro, "SMES for power utility applications: a review of technical and cost considerations," in IEEE Transactions on Applied Superconductivity, vol. 9, no. 2, pp. 541-546, June 1999.

[15] C. S. Hsu and W. J. Lee, "Superconducting magnetic energy storage for power system applications," in IEEE Transactions on Industry Applications, vol. 29, no. 5, pp. 990-996, Sept.-Oct. 1993.

[16] T. T. Nguyen and H. Cha, "Five-Level Current Source Inverter With Inductor Cell Using Switching -Cell Structure," in IEEE Transactions on Industrial Electronics, vol. 69, no. 7, pp. 6859-6869, July 2022. [17] J. Rodriguez, Jih-Sheng Lai and Fang Zheng Peng, "Multilevel inverters: a survey of topologies, controls, and applications," in IEEE Transactions on Industrial Electronics, vol. 49, no. 4, pp. 724-738, Aug. 2002.

[18] N. Mukundan C M et al., "A New Multilevel Inverter Based Grid Connected Reliable Solar Power Transfer Unit With Power Quality Enhancement," in IEEE Transactions on Industry Applications, vol. 59, no. 2, pp. 1887-1900, March-April 2023.

[19] Z. Bai and Z. Zhang, "Conformation of Multilevel Current Source Converter Topologies Using the Duality Principle," in IEEE Transactions on Power Electronics, vol. 23, no. 5, pp. 2260-2267, Sept. 2008.

[20] M. A. Al-Hitmi, M. R. Hussan, A. Iqbal and S. Islam, "Symmetric and Asymmetric Multilevel Inverter Topologies With Reduced Device Count," in IEEE Access, vol. 11, pp. 5231-5245, 2023.

[21] Bao, Jy., Li, Yl. & Zhang, Zc. A 6-switch single-phase 5-level currentsource inverter. J. Zhejiang Univ. - Sci. A 7, 1051-1055 (2006).

[22] B. P. McGrath and D. G. Holmes, "Natural Current Balancing of Multicell Current Source Converters," in IEEE Transactions on Power Electronics, vol. 23, no. 3, pp. 1239-1246, May 2008.

[23] B. Hassan, V. Pickert and B. Zahawi, "Control of five-level single-phase current- source inverters operating at high and low load conditions," Proceedings of the 2011 14th European Conference on Power Electronics and Applications, Birmingham, UK, 2011, pp. 1-9.

[24] L. Cheng et al., "A Multilevel Asymmetric Current Source Inverter Topology Using Switched Inductor," 2022 4th International Conference on Power and Energy Technology (ICPET), Beijing, China, 2022, pp. 311-316.

[25] Suroso and T. Noguchi, "Multilevel Current Waveform Generation Using Inductor Cells and H-Bridge Current-Source Inverter," in IEEE Transactions on Power Electronics, vol. 27, no. 3, pp. 1090-1098, March 2012.

[26] F. L. M. Antunes, H. A. C. Braga and I. Barbi, "Application of a generalized current multilevel cell to current- source inverters," in IEEE Transactions on Industrial Electronics, vol. 46, no. 1, pp. 31-38, Feb. 1999.

[27] S. H. Hosseini, M. F. Kangarlu and A. K. Sadigh, "A new topology for multilevel current source inverter with reduced number of switches," 2009 International Conference on Electrical and Electronics Engineering - ELECO 2009, Bursa, Turkey, 2009, pp. 1-273-1-277.

[28] P. McGrath and D. G. Holmes, "Multicarrier PWM strategies for multilevel inverters," in IEEE Transactions on Industrial Electronics, vol. 49, no. 4, pp. 858-867, Aug. 2002.

Acknowledgement of the above references herein is not to be inferred as meaning that these are in any way relevant to the patentability of the presently disclosed subject matter.

GENERAL DESCRIPTION

Following is a non-exclusive list of some exemplary embodiments of the disclosure. The present disclosure also includes embodiments which include fewer than all the features in an example and embodiments using features from multiple examples, even if not listed below.

Example 1. An inverter comprising: at least two parallel connected multi-level inverter cells for connection across a load, each cell comprising; two legs each including a complementary switch pair having two reverseblocking switches; a DC-link inductor connecting the two legs between both switch pairs of the two legs in a h-bridge configuration, each of the four reverse-blocking switches positioned, when in an on state, to allow current to flow towards the DC- link inductor; a DC current source connected at a switch-inductor connection; a polarity control comprising a complementary switch pair, where the two cells are connected by their current sources between the polarity control switches, a state of the polarity control complementary switch pair determining direction of current through the load.

Example 2. The inverter according to Example 1, comprising a gate switching controller configured to select a switching state for each of the complementary switch pairs based on a desired output current level, and, if there are redundant switching states for the desired output current level, based on measurement of inductor currents for the DC-link inductors and a measurement of output voltage across the load. Example 3. The inverter according to any one of Examples 1-2, where each said complementary switch pair includes two switches, where, for all switching states, one of the switches of the switch pair is in an on configuration, and one is in an off configuration.

Example 4. The inverter according to any one of Examples 1-3, wherein each reverse-blocking switch includes a transistor-diode pair.

Example 5. The inverter according to any one of Examples 1-4, wherein polarity control is implemented by lower power rating devices than the switch pairs of the inverter cells.

Example 6. The inverter according to any one of Examples 1-4, wherein the inverter is operated in a symmetric configuration where the current sources have a same magnitude.

Example 7. The inverter according to Example 6, wherein the inverter has 32 switching states and 9 output levels.

Example 8. The inverter according to any one of Examples 1-4, wherein the inverter is operated in an asymmetric configuration where the current sources have different magnitude.

Example 9. The inverter according to Example 8, wherein the inverter is operated in a binary asymmetric configuration where a current source of one cell is double that of a second cell, wherein the inverter has 32 switching states and 13 output levels.

Example 10. The inverter according to Example 8, wherein the inverter is operated in a trinary asymmetric configuration where a current source of one cell is triple that of a second cell, wherein the inverter has 32 switching states and 17 output levels.

Example 11. The inverter according to any one of Examples 1-7, wherein one or both of the cells comprises one or more additional complementary switch leg connected via an additional DC-link inductor.

Example 12. The inverter according to Example 11, wherein the cells have the same number of inductors, L, the same number of legs, and different current sources, I_dc2, wherein a number of output levels is according to the relationship:

Number of levels Example 13. The inverter according to Example 11, wherein a first cell of the at least two cells has a different number of inductors than a second cell of the at least two cells which has N₂ inductors, , are current levels of the first and second cell respectively, wherein a number of current levels is according to the relationship:

Number of levels

Example 14. The inverter according to any one of Examples 2-13, wherein the gate switching controller is configured to: compare each inductor current with a corresponding one or more threshold and, based on the comparison, select a switching state to charge, discharge, or maintain the inductor current.

Example 15. The inverter according to Example 14, wherein the gate switching controller is configured to compare each inductor current with a single threshold; if the inductor current exceeds the threshold, to select a discharging switching state; and if the inductor current is less than the threshold, to select a charging switching state.

Example 16. The inverter according to Example 15, wherein the gate switching controller is configured to: compare each inductor current with two thresholds, an upper and lower threshold; if the inductor current exceeds the upper threshold, to select a discharging switching state; and if the inductor current is less than the lower threshold, to select a charging switching state.

Example 17. A cascaded inverter comprising: a plurality of N parallel connected inverters according to any one of Examples 1- Example 16.

Unless otherwise defined, all technical and/or scientific terms used within this document have meaning as commonly understood by one of ordinary skill in the art/s to which the present disclosure pertains. Methods and/or materials similar or equivalent to those described herein can be used in the practice and/or testing of embodiments of the present disclosure, and exemplary methods and/or materials are described below. Regarding exemplary embodiments described below, the materials, methods, and examples are illustrative and are not intended to be necessarily limiting.

Some embodiments of the present disclosure are embodied as a system, method, or computer program product. For example, some embodiments of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” and/or “system.”

For example, hardware for performing selected tasks according to some embodiments of the present disclosure could be implemented as a chip or a circuit. As software, selected tasks according to some embodiments of the present disclosure could be implemented as a plurality of software instructions being executed by a computational device e.g., using any suitable operating system.

In some embodiments, one or more tasks according to some exemplary embodiments of method and/or system as described herein are performed by a data processor, such as a computing platform for executing a plurality of instructions. Optionally, the data processor includes a volatile memory for storing instructions and/or data and/or a non-volatile storage e.g., for storing instructions and/or data. Optionally, a network connection is provided as well. User interface/s e.g., display/s and/or user input device/s are optionally provided.

Some embodiments of the present disclosure may be described below with reference to flowchart illustrations and/or block diagrams. For example illustrating exemplary methods and/or apparatus (systems) and/or and computer program products according to embodiments of the present disclosure. It will be understood that each step of the flowchart illustrations and/or block of the block diagrams, and/or combinations of steps in the flowchart illustrations and/or blocks in the block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general -purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart steps and/or block diagram block or blocks. These computer program instructions may also be stored in a computer readable medium that can direct a computer (e.g., in a memory, local and/or hosted at the cloud), other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium can be used to produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer program instructions may also be run by one or more computational device to cause a series of operational steps to be performed e.g., on the computational device, other programmable apparatus and/or other devices to produce a computer implemented process such that the instructions which execute provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to better understand the subject matter that is disclosed herein and to exemplify how it may be carried out in practice, embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

FIG. 1A is a simplified schematic circuit diagram of a inverter system, according to some embodiments of the disclosure;

FIG. IB is a flow chart of a method of inverter control, according to some embodiments of the disclosure;

FIG. 2A is an illustration of a multilevel current source invertor, according to some embodiments of the disclosure;

FIG. 2B is an illustration of current source multilevel inverter connected to a gate switching controller, according to some embodiments of the disclosure;

FIG. 2C is an illustration of current source multilevel invertor, in switching state

2, according to some embodiments of the disclosure;

FIG. 2D is an illustration of current source multilevel invertor, in switching state

3, according to some embodiments of the disclosure;

FIG. 3 is a simplified schematic of a controller block diagram, according to some embodiments of the disclosure; FIG. 4A is a plot of inverter output current, according to some embodiments of the disclosure;

FIG. 4B is a plot of load current with time, according to some embodiments of the disclosure;

FIG. 4C is a plot of load current in the frequency domain, according to some embodiments of the disclosure;

FIGs. 5A-C are plots of gate switching signals, according to some embodiments of the disclosure;

FIG. 6 is an illustration of a multi level current source inverter, according to some embodiments of the disclosure; and

FIG. 7 is an illustration of a multi level current source inverter, according to some embodiments of the disclosure.

In some embodiments, although non-limiting, in different figures, like numerals are used to refer to like elements, for example, element 102 in FIG. 1 corresponding to element 202 in FIG. 2. In the figures, and this document components may be labelled and referred to using subscript text and without using subscript text, however the same letter and number combinations, regardless of script size should, generally, be interpreted as referring to the same component e.g. SI being equivalent to

DETAILED DESCRIPTION OF EMBODIMENTS

The present disclosure, in some embodiments, thereof, relates to power conversion systems and, more particularly, but not exclusively, to multi-level current source inverters.

Overview

A broad aspect of some embodiments of the disclosure relates to conversion of electrical power from DC (direct current) to AC (alternating current) using a multi-level current source (termed herein “MLCI” and “inverter”) having a low number of electrical components. The MLCI is controlled using pulse width modulation (PWM) where the current levels are selected and transitioned between to approximate a sinusoidal output. This output may then be filtered to provide the AC output of the inverter system.

An aspect of some embodiments of the disclosure relates to an inverter which includes at least two parallel-connected multi-level inverter cells (termed herein “MLIC” “inverter cell”, and “cell”, the inverter termed a “double cell” inverter), and a polarity switch (also herein termed “polarity control”). Each cell provides a plurality of switching states and output current levels, the combination of two cells increasing both the switching states and possible current levels. Where a switching state defines an ON/OFF configuration of power switches in the inverter.

The polarity switch doubles the number of switching states and determines the polarity of the current flowing through the load. Where, as a current level of zero does not have a polarity, the polarity switch increases the number, N, of current levels provided the two cells to (2 * IV) — 1 current levels, and this, while the polarity switch switches at the output frequency, which is lower than the PWM carrier frequency. A potential advantage of the increased number of output levels is an output waveform which more closely emulates a sinusoid (e.g., with reduced harmonic content). Potential advantages of the low switching frequency of the polarity switch may include low switching losses at the polarity switch and/or the ability to implement the polarity switch with low powerrated devices.

Each inverter cell includes a DC current source, at least four unidirectional (or reverse-blocking) switches, and an inductive DC-link. The four reverse-block switches include two complementary switch pairs, disposed on two legs, with the DC-link inductor connecting the legs between the two switches. This may be considered an H-bridge configuration. The reverse-block switches (e.g., as provided by a transistor-diode pair) are each positioned to allow current to flow towards the inductor. The current source may be connected at a junction between a leg and the inductor. The two cells may be connected at the current sources where the polarity control may include another complementary switch pair disposed on another leg. The term “complementary switch pair” may refer functioning of and/or to how the switches are driven; one of the pair being in an on configuration and the other in an off configuration when the inverter is activated.

The parallel connected inverter cells combined with the polarity switch provide a large ratio of switching states to output levels, providing switching state redundancy. This, with an inverter structure only including 10 switches, two inductors and two current sources.

In detail, each inverter cell includes four switches (two switch pairs) provides three current output levels and three switching states. Parallel connecting two inverter cells provides 16 switching states and 5 output levels, the polarity switch doubling the number of switching states to 32 states and increasing the number of output levels to 9 output levels. Having a low number of components may not only reduce circuit complexity but may additionally or alternatively reduce power losses as associated with component operation (e.g., switching losses).

An aspect of some embodiments of the disclosure relates to using switching state redundancy to maintain constant and/or low fluctuation DC-link inductor current (also herein termed “balancing” the inductor current e.g., using hysteresis control). The polarity switch combined with a multi-level inverter potentially provides a larger number of switching states and redundant states per output level for the number of components used. For example, the combination of dual current sources and cells provide 32 switching states providing switching state redundancy for more than one output current level for a plurality of inverter configurations (symmetric, asymmetric).

Potential advantages of balancing inductor current include one or more of; lower harmonic content, reduced losses, and eased output filter requirements.

In some embodiments balancing of inductor current/s, also herein termed “hysteresis control” is implemented where a gate switching controller, based on measured inductor current/s selects a switching state (and corresponding current paths which provide charging, discharging or no change to the inductor/s) from a plurality of options for a given current level. Where the different current paths provide inductor charging, discharging, or no change, as associated with different voltage drop polarities across the inductor in the different switching states.

In some embodiments, hysteresis control includes toggling between at least two switching states to control inductor current.

For example, for a given current output level, and when inductor current balancing is feasible, if the relevant inductor current exceeds a defined maximum threshold a switching state meeting the required output current and imposing a negative voltage drop over the inductor will be selected. The negative voltage drop will result in inductor current decreasing e.g., according to the following inductor current- voltage relation: = v_L.

Conversely, for example, for a given current output level and when inductor current balancing is feasible, if the relevant inductor current is bello a defined minimum threshold, a switching state meeting the required output current and imposing a positive voltage drop over the inductor will be selected. The positive voltage drop will result in inductor current increase e.g., according to the following inductor current- voltage relation

In some embodiments, inverter functionality may be extended by operating the inverter in different configurations, for example, asymmetrical operation where the two current sources have different levels. Asymmetrical operation, in some embodiments, may increase the number of output levels, although, without increasing component numbers it does not increase the number of switching states. For example, the double cell inverter operated in a binary asymmetrical configuration (where one current source is double the other) provides 13 output current levels. In some embodiments, possible ratios of current levels between two sources for include 1:1 (symmetric) and asymmetric configurations; 1:2 (binary), 1:3 (tertiary), 1:4 up to 1:N.

Numbers of output levels (and switching states), in some embodiments, may be increased by incorporating additional switch pairs in parallel (also herein termed “legs”), each pair connected by an additional DC-link inductor (the switch pair and inductor herein termed “leg cells”). Current levels provided by a configuration are related to inductor currents, which reduce along the chain of inductors.

For these configurations, as a ratio between inductor currents and source currents of a cell are multiples of 2, a number of output levels for an inverter configuration depends on a combination of; a ratio between the two source currents and the numbers of inductors in each cell.

In some embodiments, redundant switching states can be used to meet other operational criteria, for example, Common-mode voltage (CMV) mitigation. For example, in some embodiments, switching states are strategically selected from the redundant switching states to minimize CMV variations and, as a result, potentially reducing electromagnetic interference (EMI), motor bearing currents, and insulation stress.

In some embodiments, the inverter system may be employed in a variety of applications, for example, as a three-phase electric vehicle inverter drive, energy conversion, uninterruptible power supply, active filters, air conditioning, adjustable frequency applications, electric vehicle drives, flexible AC transmission systems, motor drives, and grid-tied renewable energy sources, and photovoltaic systems. The inverter, for example as associated with the inductor DC-links (which may be implemented using superconducting magnetic storage technology) may be employed in sensitive and/or extreme condition applications e.g., aircraft, photovoltaic systems.

Although description in this document is with respect to a single phase output, it should be understood that the inverter topologies described herein may be combined (e.g., an inverter per phase) to provide multi-phase (e.g., three phase or more) output signals. In some embodiments, for each phase, gating control uses inductor current measurements and measurement of each output phase.

An aspect of some embodiments of the disclosure relates to an inverter which includes at least one multi-level inverter cell and a polarity switch (also herein termed “polarity control”). The cell provides a plurality of switching states and output current levels, the polarity switch doubling the number of switching states and determining the polarity of the current flowing through the load. Where, as a current level of zero does not have a polarity, the polarity switch increases the number, N, of current levels provided the cells to (2 * N) — 1 current levels, and this, while the polarity switch switches at the output frequency, which is lower than the PWM carrier frequency.

The inverter cell includes a DC current source, at least four unidirectional (or reverse-blocking) switches, and an inductive DC-link. The four reverse-block switches include two complementary switch pairs, disposed on two legs, with the DC-link inductor connecting the legs between the two switches. This may be considered an H-bridge configuration. The reverse-block switches (e.g., as provided by a transistor-diode pair) are each positioned to allow current to flow towards the inductor. The current source may be connected at a junction between a leg and the inductor. In some embodiments, this single cell inverter includes one or m ore feature as described regarding the double cell inverter. For example, the single cell inverter may employ inductor current balancing, according to one or more feature as described regarding current balancing of the double cell inverter.

Before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not necessarily limited in its application to the details of construction and the arrangement of the components and/or methods set forth in the following description and/or illustrated in the drawings and/or the Examples. The invention is capable of other embodiments or of being practiced or carried out in various ways. Exemplary inverter system

FIG. 1A is a simplified schematic circuit diagram of an inverter system 100, according to some embodiments of the disclosure.

In some embodiments, system 100 includes a plurality (e.g., at least two) of multilevel inverter cells (MLIC) 106, 108, 110, a polarity switch 112, a controller 116, a power supply 114, and a load 104. Each MLIC includes a current source and a plurality of switches, and is configured to provide a multi-leveled current output.

Controller 116, in some embodiments, receives inductor current measurement/s form one or more of the inverter cells 106, 108, 110, and generates switching control signals for the cell switches and polarity switch 112 to provide an output current iL through and an output voltage V0 across load 104.

Exemplary inverter system control method

FIG. IB is a flow chart of a method of inverter control, according to some embodiments of the disclosure.

At 101, in some embodiments, one or more desired output features of an electrical output of the inverter system (e.g., system 100 FIG. 1) are received. Where the output may include a current supplied through a load (e.g., current iL across load 104 FIG. 1) and/or a voltage across the load (e.g., V0 FIG. 1). Desired output features may include one or more of a desired current amplitude, frequency, and phase of an oscillating output current.

At 103, in some embodiments, one or more indicator of inductor current and an indicator of load voltage are received. In some embodiments, current through one or more DC-link inductor of one or more inverter cell is received (e.g., measurement signal/s are received, e.g., a measurement signal for each DC-link inductor).

At 105, in some embodiments, based on the indicator/s of inductor current and the load voltage, the switching signal is generated, where the generation includes selecting switching states over time based on both the instantaneous desired output current and the inductor current/s. Where, for an instantaneous output current level determined by the modulator/modulation scheme (e.g., sine-PWM, space vector (SV), selective harmonic elimination (SHE)) employed to meet load requirements, a switching state may be selected from a plurality of possible switching states to meet other operational criteria than the current level (e.g., inductor current balancing, CMV mitigation). Exemplary inverter

FIG. 2A is an illustration of multilevel current source invertor 202, according to some embodiments of the disclosure.

In some embodiments, invertor 202 includes two multi-rating inductor cells 206, 208; a first cell 206 and a second cell 208. Where each cell includes a direct current (DC) source and a full-bridge (H-bridge) of reverse-blocking switches (or unidirectional switches) and an inductor DC-link. First cell 206 including a first current source I_dcl, unidirectional switches SI, S2, S3, S4, and a first inductor L₁ . Second cell 206 including a second current source I_dc2, reverse-blocking switches S5, S6, S7, S8, and a second inductor L₂. A load 204 may be driven by invertor 202, providing an output current IL and voltage V0.

In some embodiments, inverter 202 includes a polarity control switch which includes switches S9, S10. Switches S9, S10 determine the polarity of the output current such that the output current is positive for switching states for which switch S9 is in an on state and switch S10 is in an off state (S₉ = 1, S₁₀ = 0) and negative for switching states for which switch S9 is in an off state and switch S 10 is in an on state (S₉ = 0, S₁₀ = 1) .

In some embodiments, one or more (e.g., each) of unidirectional switches S1-S10 are implemented using a series transistor-diode pair.

In an exemplary embodiment, the transistors are insulated gate bipolar transistors (IGBTs), although MOSFETs (metal oxide semiconductor field effect transistors), BJTs (bipolar junction transistors) and other transistor types are envisioned and encompassed in this disclosure as are standard protection mechanisms and/or heat sinks e.g., for the individual devices.

FIG. 2B is an illustration of current source multilevel inverter 202 connected to a gate switching controller 216, according to some embodiments of the disclosure.

In some embodiments, FIG. 2B illustrates connections between inverter of FIG. 2A and controller 216. Where controller 216 receives one or more inductor current measurement signal, e.g., a measurement for each inductor current t_L1, t_L2. Where controller 216 receives one or more load voltage measurement signal. For example, measurement signals as illustrated by dashed arrows in FIG. 2B. Controller 216 outputs gate switching signals for each of switches S1-S10 e.g., as illustrated by dotted arrows in FIG. 2B.

FIG. 2D is an illustration of current source multilevel inverter 202, according to some embodiments of the disclosure.

FIG. 2D illustrates an alternative schematic representation of invert 202 of FIG. 2A. Where switches S_p, and S_n are equivalent to Sg and S₁₀ respectively. Where L_1± and L₂₁ are equivalent to and L₂ respectively. Where switches Si2< S’i₂, Sn, S”n are equivalent to S₁,S₄,S₂,S₃ and switches S₂₂, S'₂₂, $21’ $ '₂₁ are equivalent to switches S₆, S₇, S₅, Sg respectively.

Exemplary control of exemplary inverter

Symmetrical and Asymmetrical configurations

Referring to the inverter topology illustrated in FIGs. 2A-C, in some embodiments, the inverter may be in a symmetrical configuration where the DC current sources provide the same current (e.g., referring to FIGs. 2A-B, where I_dcl = I_dc2 and referring to FIG. 2C, where I_dl = I_d2).

In some embodiments, the inverter may be in an asymmetrical configuration where the DC current sources provide different currents (e.g., referring to FIGs. 2A-B, referring to FIG. 2C where I_dl I_dz)-

Potentially, an asymmetrical configuration may be used to produce a larger number of output levels from a same number of switching states and components. In some embodiments, the higher the difference between the currents, the more current levels are provided. For example, in a binary configuration where I_dcl = 2_/dc2, a 13-level output current is generated, and a trinary configuration where I_dcl = 3_/dc2 gives a 17-level output current.

Although increasing the amount of asymmetry in the DC current sources increases the number of output states increases, the number of switching states does not increase nor do the number of redundant switching states (the increasing number of output states reduces the amount of redundant switching states). This may result in a tradeoff between the ability to balance inductor currents and the number of output states for a given topology, unless additional components are added. Exemplary switching states

In some embodiments, the controller (e.g., controller 216 FIG. 2B) drives at least one of the switches of each switch pair into an on state e.g., having an on switch may prevent open circuit inductor currents.

It should be understood that, although the switching states described in this document assume that one switch of each complementary pair is always on while the other is off, the gating control may incorporate an off delay. For example, both switches in a pair may be briefly on simultaneously before one is turned off (e.g., to ensure a continuous conduction path for the inductor current during a state transition). Referring to FIG. 2A, the switch pairs are {S₁, S₄}, {S₂, S₃}, {S₆,S₇}, {S₅,S₈},and {S₉, S₁₀}. The 5 switch pairs then provide 32 potential switching states.

In some embodiments, it is assumed that inductor currents t_L1 and t_L2 carry currents of magnitude ^dci/2 , Idci/2 respectively.

In embodiments where inverter 202 operates symmetrically, both sources I_dcland I_dc2 carry constant current of magnitude I_d.

In embodiments where inverter 200 operates asymmetrically, in a binary asymmetrical configuration, I_dcl = 21 _d, l_dc2 = la-

Table 1 lists the practical switching states of inverter 202 for symmetrical and binary asymmetrical configurations, where switches in the ON state are listed.

In table 1 ‘C’, ‘D’, and ‘NE’ denote, respectively, charging, discharging, and no effect conditions on inductors L_± and L₂.

The inverter configuration provides several redundant switching states for many levels of the output current, for both symmetrical and binary asymmetrical configurations.

Referring now to the symmetrical configuration, which assumes de current levels I_dci ⁼ Idc2 ⁼ Id and inductor current levels t_L1 = t_L2 = I_d/2. Most output current levels have redundant switching states, for example, output current of magnitude 3/_d/2 can be maintained in 4 different switching states.

In the binary asymmetrical configuration t_L1 — ~ Id/2.

Table 1 illustrates that only one member of each switch pair is ON for any specific state. Switches S₉ and S₁₀ of the “polarity switch” are on for, respectively, positive and negative output currents. Table 1 illustrates how for the same circuit topology, symmetrical and asymmetrical configurations can provide different numbers of output levels, e.g., as detailed by the “general” output current column.

FIG. 2C is an illustration of current source multilevel invertor 202, in switching state 2, according to some embodiments of the disclosure.

FIG. 2D is an illustration of current source multilevel invertor 202, in switching state 3, according to some embodiments of the disclosure.

FIGs. 2C-D illustrate redundant switching states where off switches are represented by open circuit connections.

Output current 3I_d/2 for example can be attained using 4 different switching states denoted 2, 3. 4, and 5, in TABLE I, where state 2 and state 3 are illustrated respectively in FIG. 2C and FIG. 2D.

Redundant switching states, while keeping the same output current, given a positive load voltage, provide a different voltage drop over each inductor L_± and L₂.

Referring to FIG. 2C; Neglecting the voltage drop over the switches, and depending on the instantaneous magnitude of the load voltage State 2 provides a negative voltage drop over inductor and a zero voltage drop over inductor L₂. This results in decreasing current i_L1and constant current i_L.2.

Referring to FIG. 2D, Similarly, State 3 results in a constant current over inductor L₁ and decreasing of the current carried by inductor L₂. Other states can increase the current in inductor L_± while keeping inductor L₂ current constant and increasing current in inductor L₂ while keeping the current in inductor L_± constant.

Examining the switching states for inverter output current I_d shows 6 possible gate sequences. The first 2, States 6 and 7, have no effect over either one of the inductors. By selecting State 8 inductor current i_£1will be increased and inductor current i_L.2 decreased. Alternatively, by selecting State 9, inductor current t_L1 will be decreased while inductor current t_L2 increased. Finally, by utilising States 10 and 11 on the other hand, inductor currents can be jointly charged or discharged.

Referring to table 1, some switching states (and corresponding output levels) afford the ability to independently balance inductor currents e.g., state 2 which enables discharging of L_± without affecting (charging or discharging) L₂. Whereas some output levels enable balancing of both inductors at the same time, for example, states 8 and 9. Exemplary balancing of inductor currents

Regarding switching State 3 illustrated in FIG. 2D, inductor L_± forms a closed loop with switches S3 and S₄. Neglecting the on-state forward voltage of the switches (e.g., IGBTs), the voltage drop v_L over inductor is: (Equation 1) and hence the current t_L1 = constant.

Neglecting switch (transistor) forward voltage drop and applying Kirchhoff’s Voltage Law on the right-hand side loop provides in:

^VL₂ + ^VL = 0 (Equation 2)

Where v_L is the voltage drop impressed on the load (illustrated in the figures as VO or v₀).

Substituting the derivative relation between inductor current and voltage Equation 2 becomes:

(Equation 3)

Which maintains:

(Equation 4)

As can be derived from Equation 4 for switching State 3, inductor current derivative i_L is inversely related to the polarity of the load voltage. This analysis is in line with the description given above and the indications provided in TABLE I.

When the current tendency (derivative), when positive, the current will increase and when it is negative, the current will decrease. From Equation 4, if the load voltage v_L is negative, the derivative will be positive, and the current will increase. If, on the other hand, load voltage v_L is positive at a given instance, the derivative will be negative and the current will reduce. Hence, in some embodiments, to control the inductor current instantaneous measurements of both inductor current and load voltage are used e.g., to select switching states.

From the above analysis, inductor currents, in some embodiments, are regulated by selecting one of the redundant switching states based on the instantaneous state of the inductor currents and load voltage.

In some embodiments, switching states for output currents for which both inductors are under “no effect” conditions (e.g., switching states providing output currents 2I_d, 0, and -2I_d for the symmetrical configuration) are not used in control of the inductor currents.

FIG. 3 is a simplified schematic of a controller 316 block diagram, according to some embodiments of the disclosure.

In some embodiments, a pulse width modulation (PWM) technique is employed by the gating controller, where a pseudo-sinusoidal waveform is outputted by controlling current level and current pulse widths through the load.

For example, where a modulation technique may be selected from Sinusoidal PWM (SPWM), Space Vector PWM (SVPWM), Phase Disposition PWM (PDPWM), Phase Opposition Disposition PWM (PODPWM), Alternative Phase Opposition Disposition PWM (APODPWM), Selective Harmonic Elimination PWM (SHE-PWM), Carrier-Based PWM, Random PWM (RPWM), Hybrid PWM, Level-Shifted Multicarrier PWM, and Phase-Shifted Multicarrier PWM.

In some embodiments, gate switching is implemented using multicarrier phase opposition disposition sinusoidal pulse width modulation (PODPWM). Where an approximate sinusoidal waveform is outputted by adjusting current pulse widths according to optimal harmonic cancellation e.g., according to one or more feature of [28].

In some embodiments, pulse width modulation (PMW) gating waveforms 322 for inverter switches are generated by comparing (e.g., at a comparator 318) carrier signals, for example, triangular carrier signals 329 (provided by a carrier signal source 328) with a sine wave reference signal 341, also herein termed “AC reference” (provided by a AC reference source 340). AC reference 341 may represent a desired output current including a desired amplitude, frequency, and phase.

In some embodiments, an M-level MCSI uses (M - 1) carrier signals, where “M” is the number of current levels. For example, for the inverter of FIG. 2A, operated symmetrically, eight carrier signals are used to provide a nine-level output. The same inverter operated in the binary asymmetrical configuration or the tertiary asymmetrical configuration use thirteen and seventeen carrier signals respectively. In some embodiments, the carrier signals are of equal amplitude and frequency, although depending on the modulation scheme, the carrier signals may have different phase (e.g., when using phase disposition PWM). In some embodiments, a measurement of each inductor current i_L1, i_L2 is compared with a corresponding reference or threshold signal 328, 322. For example, at a first comparator 324 where a first inductor current i_L (e.g., see FIGs. 2A-C, and FIG. 6) is compared with a first reference signal 328 and at a second comparator 326 where second inductor current i_L2 (e.g., see FIGs. 2A-C, and FIG. 6) is compared with a second reference signal 328. For the symmetrical configuration, the first and second reference signals 328, 332 are the same, e.g., half the current source current I_d, I_Ref = /_d/2, or the same reference signal is supplied to both comparators 324, 326.

Alternatively, in some embodiments, a more sophisticated current control scheme is employed e.g., to reduce oscillation of inductor currents. In some embodiments, elements 324, 326 compare received inductor currents with more than one threshold, for example, a lower and an upper threshold. Where, for example, current levels between the thresholds are allowed and only when the current level falls below the lower threshold is the switching state selected to charge the corresponding inductor and/or when the current level rises above the upper threshold is the switching state selected to discharge the corresponding inductor. Other current control schemes are envisioned and encompassed by the current disclosure.

In some embodiments, a gate signal generator 320 selects a switching state which best affords the ability to maintain constant inductor currents and to provide a desired output (load) current. For example, by selecting different switching states the inductor currents may increase or decrease. Along with, for example, providing the desired output current.

In some embodiments, if a measured inductor current (i_L1 and/or i_L2) is greater than half of the reference current (/_Ref), as communicated by comparator/s the gate signal generator 320 (e.g., as a positive input signal) gate signal generator 320 corresponding selects (and/or generates and/or applies to the switch gates) a switching state which provides discharging to the inductor/s. On the other hand, when the measured inductor current/s are less than half of the reference current charging switching states the gate signal generator may select a switching state which provides charging conditions to the inductor/s.

For example, referring back to Table 1, if the output current should be l_d for the time period in question, first comparator 324 and second comparator 326 are both providing positive inputs to gate signal generator 320, switching state 10 may be selected. As in state 10 (see table 1), both inductors are being discharged to reduce the currents from their levels which are above /_Ref/2. In some embodiments, gate signal generator includes a memory having look-up tables for switching states (or is able to access remotely stored look-up tables). Where gate signal generator 320 may be configured to supply gating signals for the invertor in a plurality of configurations, in which case controller 316 may include a reference current generator able to supply reference signals 328, 332 for different inverter configurations (e.g., asymmetrical configurations).

In some embodiments, a load voltage measurement is used in selection of a switching state e.g., in addition to measurements of inductor currents. Where the load voltage v_L is negative, the current derivative will be positive, and the load current may increase. If, on the other hand, load voltage v_L is positive at a given instance, the derivative will be negative and load current will reduce. Hence, in some embodiments, the inductor current instantaneous measurements and load voltage are used to control the inverter, e.g., to select switching states. Inductor currents, in some embodiments, are regulated by selecting one of the redundant switching states based on the instantaneous state of the inductor currents and load voltage.

Exemplary simulation results

The inverter topology of FIG. 2A under symmetrical operation was simulated using a Simulink/MATLAB R2013B environment.

FIG. 4A is a plot of inverter output current with time, according to some embodiments of the disclosure. Visible in FIG. 4A are nine distinct levels of the output current.

FIG. 4B is a plot of load current with time, according to some embodiments of the disclosure.

FIG. 4C is a plot of load current in the frequency domain, according to some embodiments of the disclosure.

FIGs. 4B-C were produced by the simulation which includes an output filter and load having inductance and resistance. FIG. 4B illustrates the load current in the time domain and FIG. 4C in the frequency domain. The load current features a smooth sinusoidal waveform with little harmonic content and 0.75% THD (total harmonic distortion). The simulation used a fundamental frequency of 50Hz and a carrier frequency of 2,500HZ. Visible in FIG. 4C is the low carrier frequency content at the carrier frequency, at harmonic 42 (less than 0.1% of the fundamental frequency component), associated, for example, with the large number of inverter output levels and/or the output filter.

FIGs. 5A-C are plots of gate switching signals, according to some embodiments of the disclosure.

As the simulated inverter (FIG. 2A) includes two inverter cells which operate in similar conditions, including gating signals having at the same carrier and fundamental frequency, a complete picture of the switching characteristics of the inverter (FIG. 2A) can be provided by examining only one sub-module.

FIGs. 5A-C illustrate three gating signals, those of S_± (FIG. 5A), S₅ (FIG. 5B), and S₉ (FIG. 5C).

Referring to FIGs. 5A-B, the switches both commutate at the carrier frequency with a substantial toggling throughout the fundamental cycle.

A comparison of the two waveforms shows that the commutations of switch S₅ occur around 50% of the fundamental cycle. The power loss of a switch may be roughly determined by the amount of current it carries (conduction loss) and the number of commutations it experiences per fundamental cycle (switching loss). As switches and S₅both carry the same current, their power loss difference is only due to their switching frequency (number of commutations per cycle). S₅ commutating around 50% of the fundamental cycle, in some embodiments, means correspondingly a low power rating type switch may be selected.

Referring to FIG. 5C, S₉, along with S₁₀ carries the full source load I_d. As can be observed in the figure, the switch commutates at the low fundamental frequency, averaging switching loss of the transistor over this time period (long in comparison to switching rapidity of switches S 1-8).

Exemplary N-state inverter

FIG. 6 is an illustration of a multi level current source inverter 602, according to some embodiments of the disclosure. FIG. 6, in some embodiments, includes elements of FIG. 2C with like labeling for like elements. In FIG. 6, the two current sources I_dl and I_d2 remain along with a single polarity switch implemented with unidirectional switches S_p, S_n.

FIG. 6 illustrates how a number of switching states and output levels may be increased by adding one or more legs (each leg including a switch pair) and one or more DC-link inductors to one or more of the 4-switch-single-inductor cells 206, 208 of FIG. 2C (and FIGs. 2A-B).

FIG. 6 illustrates options including up to N legs for both of cells 606, 608.

Where, referring to first cell 606, addition of a single leg would include inductor L₁₂ connecting additional leg having switches S_1N, S'_1N forming an additional “leg cell” (and not including inductor L_1N and elements left thereof). In some embodiments, an additional leg, or an additional leg cell including a leg and connecting DC-link inductor would only be incorporated into first cell 606, second cell 608 having the configuration of second cell 208 FIG. 2C.

Embodiments including one additional leg cell for each of inverter cells 606, 608 are envisioned and encompassed, as are embodiments including any number (including zero) of additional leg cells for each of cells 606, 608 as indicated by dotted lines and usage of “N” in switch and inductor labeling in FIG. 6.

Additional leg cells, theoretically, increase the number of switching states of inverter 602, e.g., as related to currents through the inductors:

As defined using first cell 606, but should be understood to be applicable to second cell 608.

First inductor having a current of: (Equation 5)

Nth inductor L_1W having a current of: (Equation 6)

In some embodiments, the number of output levels, for symmetrical cells having the same number of inductors and legs (provided, for the given configuration the required output levels can be balanced) is defined by:

Where I_dc2 > I_dcl and L is the number of inductors per cell. In some embodiments, the number of output levels for a two cell configuration having different numbers of inductors in each cell (provided, for the given configuration the required output levels can be balanced) is defined by:

Were I_dcl is the DC source current level of the first 606 cell, is the number of inductors for first 606 cell, I_dc2 is the DC source current level of second cell 608, and N₂ is the number of inductors for second cell 608 cell.

Exemplary cascaded structure

FIG. 7 is an illustration of a multi level current source inverter 702, according to some embodiments of the disclosure.

In FIG. 7, a plurality of the inverter structures of FIGs. 2A-B have been cascaded across a single load 704.

In some embodiments, a cascaded configuration employing a plurality of the inverter structures (each inverter structure herein termed a “sub -converter”) of FIGs. 2A- C and/or of FIG. 6, may be used to increase the number of output levels whilst maintaining simplicity of sub-converter construction.

A potential benefit of using a cascaded configuration is robustness of the system in the face of faults, if one of the sub-converters fails, the other/s may continue to function. Although less current levels are generated in this situation, the inverter remains operational.

A potential advantage of the cascaded configuration is modularity of the sub- converters, potentially enabling replacement (or upgrade) of individual sub-blocks.

General

As used within this document, the term “about” refers to±20%

The terms “comprises”, “comprising”, “includes”, “including”, “having” and their conjugates mean “including but not limited to”.

The term “consisting of’ means “including and limited to”.

As used herein, singular forms, for example, “a”, “an” and “the” include plural references unless the context clearly dictates otherwise. Within this application, various quantifications and/or expressions may include use of ranges. Range format should not be construed as an inflexible limitation on the scope of the present disclosure. Accordingly, descriptions including ranges should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within the stated range and/or subrange, for example, 1, 2, 3, 4, 5, and 6. Whenever a numerical range is indicated within this document, it is meant to include any cited numeral (fractional or integral) within the indicated range.

It is appreciated that certain features which are (e.g., for clarity) described in the context of separate embodiments, may also be provided in combination in a single embodiment. Where various features of the present disclosure, which are (e.g., for brevity) described in a context of a single embodiment, may also be provided separately or in any suitable sub-combination or may be suitable for use with any other described embodiment. Features described in the context of various embodiments are not to be considered essential features of those embodiments, unless the embodiment is inoperative without those elements.

Although the present disclosure has been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, this application intends to embrace all such alternatives, modifications and variations that fall within the spirit and broad scope of the appended claims.

All references (e.g., publications, patents, patent applications) mentioned in this specification are herein incorporated in their entirety by reference into the specification, e.g., as if each individual publication, patent, or patent application was individually indicated to be incorporated herein by reference. Citation or identification of any reference in this application should not be construed as an admission that such reference is available as prior art to the present disclosure. In addition, any priority document(s) and/or documents related to this application (e.g., co-filed) are hereby incorporated herein by reference in its/their entirety.

Where section headings are used in this document, they should not be interpreted as necessarily limiting.

Claims

CLAIMS:

1. An inverter comprising: at least two parallel connected multi-level inverter cells for connection across a load, each cell comprising; two legs each including a complementary switch pair having two reverseblocking switches; a DC-link inductor connecting the two legs between both switch pairs of the two legs in a h-bridge configuration, each of the four reverse-blocking switches positioned, when in an on state, to allow current to flow towards the DC- link inductor; a DC current source connected at a switch-inductor connection; a polarity control comprising a complementary switch pair, where the two cells are connected by their current sources between the polarity control switches, a state of the polarity control complementary switch pair determining direction of current through the load.

2. The inverter according to claim 1, comprising a gate switching controller configured to select a switching state for each of the complementary switch pairs based on a desired output current level, and, if there are redundant switching states for the desired output current level, based on measurement of inductor currents for the DC-link inductors and a measurement of output voltage across the load.

3. The inverter according to any one of claims 1-2, where each said complementary switch pair includes two switches, where, for all switching states, one of the switches of the switch pair is in an on configuration, and one is in an off configuration.

4. The inverter according to any one of claims 1-3, wherein each reverseblocking switch includes a transistor-diode pair.

5. The inverter according to any one of claims 1-4, wherein polarity control is implemented by lower power rating devices than the switch pairs of the inverter cells.

6. The inverter according to any one of claims 1-4, wherein the inverter is operated in a symmetric configuration where the current sources have a same magnitude.

7. The inverter according to claim 6, wherein the inverter has 32 switching states and 9 output levels.

8. The inverter according to any one of claims 1-4, wherein the inverter is operated in an asymmetric configuration where the current sources have different magnitude.

9. The inverter according to claim 8, wherein the inverter is operated in a binary asymmetric configuration where a current source of one cell is double that of a second cell, wherein the inverter has 32 switching states and 13 output levels.

10. The inverter according to claim 8, wherein the inverter is operated in a trinary asymmetric configuration where a current source of one cell is triple that of a second cell, wherein the inverter has 32 switching states and 17 output levels.

11. The inverter according to any one of claims 1-7, wherein one or both of the cells comprises one or more additional complementary switch leg connected via an additional DC-link inductor.

12. The inverter according to claim 11, wherein the cells have the same number of inductors, L, the same number of legs, and different current sources, I_dc2, I_dci where I_dc2 > I_dc1, wherein a number of output levels is according to the relationship:

Number of levels

13. The inverter according to claim 11, wherein a first cell of the at least two cells has a different number of inductors than a second cell of the at least two cells which has N₂ inductors, , I_dc2, I_dcl are current levels of the first and second cell respectively, wherein a number of current levels is according to the relationship:

Number of levels

14. The inverter according to any one of claims 2-13, wherein the gate switching controller is configured to: compare each inductor current with a corresponding one or more threshold and, based on the comparison, select a switching state to charge, discharge, or maintain the inductor current.

15. The inverter according to claim 14, wherein the gate switching controller is configured to compare each inductor current with a single threshold; if the inductor current exceeds the threshold, to select a discharging switching state; and if the inductor current is less than the threshold, to select a charging switching state.

16. The inverter according to claim 15, wherein the gate switching controller is configured to: compare each inductor current with two thresholds, an upper and lower threshold; if the inductor current exceeds the upper threshold, to select a discharging switching state; and if the inductor current is less than the lower threshold, to select a charging switching state.

17. A cascaded inverter comprising: a plurality of N parallel connected inverters according to any one of claims 1-16.