WO2025265089A1

WO2025265089A1 - Reactive ion beam etch to reduce line-space pattern line width roughness and photoresist loss

Info

Publication number: WO2025265089A1
Application number: PCT/US2025/034648
Authority: WO
Inventors: Jengyi Yu; Samantha S.H Tan; Yisi Zhu; Chih-Min Lin; Shuogang Huang; Richard Wise; Shashank C Deshmukh
Original assignee: Lam Research Corp
Current assignee: Lam Research Corp
Priority date: 2024-06-21
Filing date: 2025-06-20
Publication date: 2025-12-26
Anticipated expiration: 2026-12-21

Abstract

Methods for processing of semiconductor substrates are provided. A method includes providing, to a processing chamber, a semiconductor substrate including a metal-containing patterned photoresist mask layer disposed thereon. In some embodiments, the pattern is a line-space pattern. In some embodiments, the method further includes exposing the semiconductor substrate to a reactive ion beam including at least one reactive gas in a direction parallel or substantially parallel to a pattern in the metal-containing patterned photoresist mask layer.

Description

REACTIVE ION BEAM ETCH TO REDUCE LINE-SPACE PATTERN LINE WIDTH

ROUGHNESS AND PHOTORESIST LOSS

INCORPORATION BY REFERENCE

[0000] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in its entirety and for all purposes.

BACKGROUND

[0001] One process frequently employed during fabrication of semiconductor devices is formation of an etched cylinder or other recessed feature in dielectric material. For instance, such processes are commonly used in memory applications such as fabricating dynamic random access memory (DRAM) structures. As the semiconductor industry advances and device dimensions become smaller, such features are increasingly difficult to etch in a uniform manner, especially for high aspect ratio cylinders having narrow widths and/or deep depths.

[0002] Ion beam etching an etch technique which may be advantageous for certain manufacturing conditions and purposes. It involves delivering ions to the surface of a substrate to physically and/or chemically remove atoms and compounds from the surface in an anisotropic manner. The impinging ions strike the substrate surface and remove material through momentum transfer (and through reaction in the case of reactive ion etching). There is a demand for sophisticated and precise methods such as ion beam etching to improve the quality of patterned substrates.

[0003] The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

SUMMARY

[0004] Methods and apparatuses for processing semiconductor substrates are provided herein. One aspect of the disclosure relates to a method for processing a semiconductor substrate. In some embodiments, the method includes providing, to a processing chamber, a semiconductor substrate that includes a metal-containing patterned photoresist mask layer disposed thereon and exposing the semiconductor substrate to a reactive ion beam that includes at least one reactive gas in a direction parallel or substantially parallel to a pattern in the metal-containing patterned photoresist mask layer.

[0005] In some embodiments, a material of the metal-containing patterned photoresist mask layer is a metal-oxide-containing photoresist material. In some embodiments, a material of the metal-containing patterned photoresist mask layer is a metal-organic-containing photoresist material. In some embodiments, the metal-containing patterned photoresist mask layer includes an Extreme Ultraviolet (EUV)-sensitive photoresist film.

[0006] In some embodiments, the reactive ion beam is an angled reactive ion beam. In some embodiments, an angle of incidence of the angled reactive ion beam is from about 5 degrees to about 90 degrees. In some embodiments, the angle of incidence of the angled reactive ion beam is from about 75 degrees to about 85 degrees.

[0007] In some embodiments, the at least one reactive gas is hydrogen, a halogen-containing gas, a hydrocarbon gas, a nitrogen-containing gas, or an oxygen-containing gas. In some embodiments, the oxygen-containing gas is CO, CO2, O2, CH3OH, SO2, or O3.

[0008] In some embodiments, the pattern is a line-space pattern. In some embodiments, the linespace pattern includes a first photoresist line, a second photoresist line, and a space disposed between the first photoresist line and the second photoresist line. In some embodiments, at least one defect is located in the space. In some embodiments, each defect of the at least one defect is scum or a nanobridge. In some embodiments, the method reduces the at least one defect.

[0009] In some embodiments, the method reduces roughness of sidewalls of the first photoresist line and the second photoresist line. In some embodiments, the method reduces material loss of the metal -containing patterned photoresist mask layer.

[0010] In some embodiments, the method further includes dry developing or wet developing the semiconductor substrate to form the metal-containing patterned photoresist mask layer before exposing the semiconductor substrate to the reactive ion beam.

[0011] Another aspect of the disclosure relates to a method for smoothing a patterned mask. In some embodiments, the method includes providing, to the processing chamber, the semiconductor substrate that includes the metal-containing patterned photoresist mask layer. In some embodiments, a pattern of the metal-containing patterned photoresist mask layer is a line-space pattern having a first roughness. In some embodiments, the method further includes exposing the semiconductor substrate to a reactive ion beam that includes at least one reactive gas in a direction parallel or substantially parallel to the line-space pattern to produce a smoothened metalcontaining patterned photoresist mask layer having a second roughness. In some embodiments, the second roughness is less than the first roughness.

[0012] In some embodiments, the line-space pattern includes a first photoresist line, a second photoresist line, and a space disposed between the first photoresist line and the second photoresist line. In some embodiments, at least one defect is located in the space. In some embodiments, each defect of the at least one defect is scum or a nanobridge.

[0013] In some embodiments, (i) the method reduces the at least one defect; and/or (ii) the method reduces roughness of sidewalls of the first photoresist line and the second photoresist line. [0014] In some embodiments, the method reduces material loss of the metal-containing patterned photoresist mask layer.

[0015] In some embodiments, the metal -containing patterned photoresist mask layer includes a first thickness, the smoothened metal-containing patterned photoresist mask layer includes a second thickness, and a difference between the first thickness and the second thickness is less than 5 percent. In some embodiments, the first roughness and the second roughness include line width roughness (LWR). In some embodiments, the first roughness and the second roughness include space width roughness (SWR).

[0016] In some embodiments, the reactive ion beam is an angled reactive ion beam. In some embodiments, the angle of incidence of the angled reactive ion beam is from about 5 degrees to about 90 degrees.

[0017] In some embodiments, the at least one reactive gas is co-flowed with an inert gas. In some embodiments, the at least one reactive gas is hydrogen, a halogen-containing gas, a hydrocarbon gas, a nitrogen-containing gas, or an oxygen-containing gas. In some embodiments, the oxygen-containing gas is CO, CO2, O2, CH3OH, H2O vapor, COS, SO2, NO, N2O, NO2, or O3. [0018] In some embodiments, a material of the metal-containing patterned photoresist mask layer is a metal-oxide-containing photoresist material, a metal-organic-containing photoresist material, or an organometallic oxide-containing photoresist material. In some embodiments, the metal-containing patterned photoresist mask layer includes the EUV-sensitive photoresist film.

[0019] In some embodiments, the method further includes dry developing or wet developing the semiconductor substrate to form the metal-containing patterned photoresist mask layer before exposing the semiconductor substrate to the reactive ion beam.

[0020] Another aspect of the disclosure relates to a method for polymer deposition on a semiconductor substrate. In some embodiments, the method includes providing, to the processing chamber, the semiconductor substrate that includes the metal -containing patterned photoresist mask layer. In some embodiments, the pattern of the metal-containing patterned photoresist mask layer is a line-space pattern. In some embodiments, the method further includes exposing the semiconductor substrate to a reactive ion beam that includes a first reactive gas and a reagent in a direction parallel or substantially parallel to the line-space pattern to deposit a polymer layer over the metal-containing patterned photoresist mask layer to form a protected patterned mask. In some embodiments, the first reactive gas is a hydrocarbon gas. [0021] In some embodiments, the hydrocarbon gas is methane, ethane, ethylene, propane, propylene, butane, or butylene. In some embodiments, the reagent includes hydrogen.

[0022] In some embodiments, the method further includes exposing the protected patterned mask to a reactive angled ion beam that includes a second reactive gas. In some embodiments, the second reactive gas is an oxygen-containing gas. In some embodiments, the oxygen-containing gas is CO, CO₂, O₂, CH3OH, H₂O vapor, COS, SO₂, NO, N₂O, NO₂, or O₃.

[0023] In some embodiments, the semiconductor substrate further includes an underlayer disposed beneath the metal-containing patterned photoresist mask layer. In some embodiments, at least one of the metal-containing patterned photoresist mask layer and the underlayer are protected from loss of material when the protected patterned mask is exposed to the reactive angled ion beam that includes the second reactive gas.

[0024] Another aspect of the disclosure relates to a method of processing a semiconductor substrate. In some embodiments, the method includes providing, to the processing chamber, the semiconductor substrate that includes the metal-containing patterned photoresist mask layer. In some embodiments, the pattern of the metal-containing patterned photoresist mask layer is a linespace pattern. In some embodiments, the method further includes exposing the semiconductor substrate to at least one cycle. In some embodiments, each cycle of the at least one cycle includes: (i) exposing the semiconductor substrate to a reactive angled ion beam that includes a first reactive gas and a first reagent in a direction parallel or substantially parallel to the line-space pattern to deposit a polymer layer over the metal-containing patterned photoresist mask layer; and (ii) exposing the semiconductor substrate to the reactive angled ion beam that includes a second reactive gas and a second reagent.

[0025] In some embodiments, operations (i) and (ii) are performed sequentially as: (i) and (ii). In some embodiments, the operations (i) and (ii) are performed sequentially as: (ii) and (i).

[0026] In some embodiments, each of the first reactive gas and the second reactive gas include a hydrocarbon gas. In some embodiments, each of the first reagent and the second reagent include hydrogen or oxygen.

[0027] Another aspect of the disclosure relates to an apparatus for processing a semiconductor substrate. In some embodiments, the apparatus includes a dry development module. In some embodiments, the dry development module includes one or more process chambers, where each process chamber that includes a chuck, one or more gas inlets into the process chambers and associated flow-control hardware, and a controller having at least one processor and a memory. In some embodiments, the apparatus further includes a vacuum transfer module coupled to the dry development module and a reactive ion beam etch module coupled to the vacuum transfer module. In some embodiments, the at least one processor and the memory are communicatively connected with one another. In some embodiments, the at least one processor is at least operatively connected with a flow-control hardware. In some embodiments, the memory stores computer-executable instructions for controlling the at least one processor to at least control the flow-control hardware to: dry develop a semiconductor substrate to form a metal-containing patterned photoresist mask layer on the semiconductor substrate and expose the metal-containing patterned photoresist mask layer to a reactive ion beam including a reactive gas in a direction parallel or substantially parallel to a pattern in the metal-containing patterned photoresist mask layer. In some embodiments, the reactive ion beam etch module is the angled reactive ion beam.

[0028] Another aspect of the disclosure relates to a method for processing the semiconductor substrate. In some embodiments, the method includes providing, to the processing chamber, the semiconductor substrate that includes the metal-containing patterned photoresist mask layer disposed thereon and exposing the semiconductor substrate to the reactive ion beam that includes the at least one reactive gas at the angle of incidence from about 5 degrees to about 90 degrees. In some embodiments, the reactive ion beam is configured to reduce roughness in the metalcontaining patterned photoresist mask layer and/or remove at least one defect in the metalcontaining patterned photoresist mask layer. In some embodiments, each defect of the at least one defect is scum or a nanobridge. In some embodiments, the angle of incidence is from about 75 degrees to about 85 degrees.

[0029] Another aspect of the disclosure relates to a method for processing the semiconductor substrate. In some embodiments, the method includes providing, to the processing chamber, the semiconductor substrate that includes a hardmask layer disposed thereon and exposing the semiconductor substrate to the reactive ion beam that includes the at least one reactive gas in the direction parallel or substantially parallel to the pattern in the hardmask layer.

[0030] In some embodiments, the hardmask layer includes an ashable hardmask layer. In some embodiments, the hardmask layer includes a spin-on carbon (SOC) hardmask.

[0031] In some embodiments, the reactive ion beam is configured to reduce roughness in the hardmask layer and/or remove at least one defect in the hardmask layer. In some embodiments, each defect of the at least one defect is scum or a nanobridge.

[0032] These and other aspects are described further below with reference to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figures 1 A-1C depict schematic diagrams of line width roughness (LWR), according to some embodiments.

[0034] Figure 2A illustrates a schematic diagram of an ion beam interacting with a line-space pattern to smoothen sidewalls, according to some embodiments. [0035] Figure 2B illustrates a schematic diagram of an ion beam interacting with a line-space pattern to remove contaminants or defects from spaces between the lines, according to some embodiments.

[0036] Figure 3 depicts a schematic diagram of an example ion beam etching apparatus, according to some embodiments.

[0037] Figure 4A is a process flow diagram for a method for processing a semiconductor substrate, according to some embodiments.

[0038] Figure 4B is a process flow diagram for a method for smoothing a patterned mask, according to some embodiments.

[0039] Figure 4C is a process flow diagram for a method for processing a semiconductor substrate, according to some embodiments.

[0040] Figure 4D is a process flow diagram for a method for processing a semiconductor substrate, according to some embodiments.

[0041] Figure 5 is a process flow diagram for a method for polymer deposition on a semiconductor substrate, according to some embodiments.

[0042] Figure 6 is a process flow diagram for another method of processing a semiconductor substrate, according to some embodiments.

[0043] Figure 7 depicts scanning transmission electron microscopy (STEM) images of photopatterned substrates subjected to smoothening, according to some embodiments.

[0044] Figure 8 depicts power spectral density (PSD) curves over various frequencies illustrating line width reduction, according to some embodiments.

[0045] Figure 9 depicts STEM images of photopattemed substrates subjected to smoothening, illustrating reduced photoresist material loss, according to some embodiments.

DETAILED DESCRIPTION

[0046] In the following description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosed embodiments.

Introduction & Context

[0047] Extreme ultraviolet (EUV) lithography - typically at a wavelength of 13.5 nm - is considered as the next enabling technology for lithographic patterning. A traditional chemically amplified resist (CAR) provides a cost-effective approach; however, organic polymer CARs generate line edge roughness (LER) and line width roughness (LWR). LER is a deviation of a feature edge from an ideal shape. LWR is a varaition in a width of a patterned feature along its length. For example, any fluctuation of plasma during etching may increase the LWR. Specifically, during etching, the patterning structure may collapse, resulting in the irregular sidewall features. The high aspect ratio feature may be more susceptible to the increased LWR.

[0048] Recent research and development efforts have focused on new Extreme Ultraviolet (EUV) inorganic photoresist platform development. Such systems offer several advantages compared to a polymer-based CAR system. For example, these inorganic photoresists are generally based on metal oxides, including metal hydroxide oxides. Metal oxide-based photoresists provide enhanced resolution of the patterning step, and metal oxide-based photoresists generally show higher etch resistance than CARs, which can reduce the thickness of the phororesist to reduce the structure aspect ratio.

[0049] Current EUV patterning film stacks consist of multiple thin film layers. For example, an EUV patterning film stack may include a photoresist layer having a thickness between about 20 nm to about 40 nm, an underlayer having a thickness of about 10 nm, a carbon-based hardmask layer (such as an ashable hardmask (AHM) layer or a Spin-On-Carbon (SOC) hardmask layer) having a thickesnss between about 30 nm to about 70 nm, optionally another hardmask layer (that includes an oxide, a nitride, or an oxynitride material) having a thickness of about 5 nm to about 20 nm, and other layers, such as a titanium nitride (TiN) layer or a tungsten-doped carbon (WDC) layer. However, EUV patterning film stacks typically have a high patterning aspect ratio (e.g., >1 :1) due to low etch selectivity. Line wiggling may result from the high patterning aspect ratio, a low material modulus, and/or a high film stress of the patterning stack.

[0050] SOC hardmask materials are often used in film stacks to which EUV photoresists are applied for patterning. However, hardmask materials have a soft carbon-rich film with poor etch resistance and poor LWR. Common hardmask materials, such as amorphous silicon, aluminum oxide, hafnium oxide, zirconium oxide, silicon dioxide, silicon nitride, and AHMs, can be used directly under the photoresist layer in the patterning structure for better etch selectivity, LER, and LWR. In some embodiments, the mask layer may be an amorphous carbon mask layer or a photoresist mask layer (such as a metal-oxide photoresist mask layer).

[0051] As the critical dimensions (CDs) of semiconductor integrated circuitry features shrink below 45 nm, the control of photoresist mask layers for line-space features with conventional photolithography processes is reaching its limits. Poor and distorted line edges, as well as incompletely developed residues of the photoresist layer, cause significant roughness at the edges of line-space features, causing LER and variation in the CD of the line-space features (e.g., LWR). This non-uniform edge pattern will be transferred and/or amplified during multiple etch process steps that are required for semiconductor device fabrication, causing degradation of device performance and loss yield.

[0052] Figures 1 A-1C depict schematic diagrams of line width roughness (LWR) in line-space features, according to some embodiments. In some embodiments, an ideal feature has an edge that is “straight as a ruler,” as shown in Figure 1A, when viewed from the top down. The schematic diagram in Figure 1 A is an illustration of low or no line width roughness. However, for various reasons, the actual line feature may appear jagged and have LWR. In some embodiments, the LWR includes a low-frequency roughness, such as a wiggling (as shown in Figure IB) and a high frequency roughness, such as an irregular edge surface (as shown in Figure 1C). Practically, the LWR is considered to be a combination of the high-frequency LWR and the low-frequency LWR. In some embodiments, the LWR is a measure of how smooth the edge of a liner feature is when viewed from the top down. In some embodiments, the features with high LWR are generally undesirable because the CD measured along the line feature varies from position to position, rendering operation of the resulting device unreliable. Processes, such as ion beam etching, may be advantageously deployed to attain perfect edges of the kind, as illustrated in Figure 1A. A general discussion of ion beam etching follows.

[0053] Ion beam etching is commonly used in fabrication of magnetic devices. In some embodiments, ion beam etching involves removing material from the surface of a semiconductor substrate by delivering energetic ions to the substrate surface. In some embodiments, the semiconductor substrate may be or may include an amorphous hydrogenated carbon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon boronitride, amorphous silicon, polysilicon, or a combination of any described herein, in any form (e.g., a bulk film, a thin film, another film, a stack, etc.). Ion beam etching may be broadly categorized into processes that solely involve inert ions (e.g., argon ions), and processes that involve reactive ions or chemical reactions initiated by ions (e.g., oxygen ions, certain ionized compounds such as fluorine-containing ionized compounds, reactive or inert ions initiating a chemical reaction with a reactant chemisorbed or physisorbed on the surface on the substrate, etc.). In these of processes, ions impinge on the substrate surface and remove material through either direct physical momentum transfer (sputtering) or a chemical reaction initiated by the energy transfer from the ions (e.g., reactive ion beam etching (RIBE) or chemically assisted ion beam etching (CAIBE)). In some embodiments, the RIBE includes utilization of an ion that can chemically react with the substrate (such as oxygen, fluorine and the like). In some embodiments, in the CAIBE, an inert ion either initiates a chemical reaction between the semiconductor substrate and a reactant (such as an applied gas that is adsorbed on the surface) or generates a reactive site on the surface of the semiconductor substrate that reacts with an applied reactant coincident with or subsequent to the generation of the reactant site, or any combination thereof.

[0054] Certain applications for ion beam etching processes relate to etching of non-volatile materials. In some embodiments, the material etched is an electrically conductive material. In some embodiments, the material is etched in the context of forming a magneto-resistive random-access memory (MRAM) device, a spin-torque-transfer memory device (STT-RAM), a phase-change memory device (PSM), or a non-volatile conductor (copper, platinum, gold, and the like). In some embodiments, the ability to control the angle of incidence can be useful in generating 3D devices, such as vertically stacked memory.

[0055] When performing ion beam etching processes, it is desirable to promote a highly uniform ion flux over the surface of the semiconductor substrate. In some embodiments, uniformity is beneficial in creating reliable devices across the entire surface of the semiconductor substrate. In some embodiments, it may be desirable to promote a high ion flux and/or a high flux of a gas phase reactant. High flux can help maximize throughput. Another factor that affects the quality of the etching results is the ability to control the energy and angle at which the ions impact the surface. These factors are important in forming features having desired dimensions and profiles.

[0056] Figure 2A illustrates a schematic diagram of an ion beam interacting with a line-space pattern to smoothen side walls , according to some embodiments. As noted, EUV lithography can cause roughness on the photoresist sidewall due to stochastic effects. For example, stochastic effects may be caused in part by photon absorption where the probability of photon absorption is higher closer to the top of a photoresist layer, and may be caused in part by secondary electron generation where the probability of secondary electron generation is higher closer to a photon absorption excitation event. Incomplete removal of material following EUV lithographic processing of photoresists during patterning operations can increase sidewall roughness due to undesired footings, stringers, or other forms of undesirable roughness. Removal of sidewall imperfections and defects can improve patterning methods and can reduce roughness.

[0057] In some embodiments, the semiconductor substrate includes an etch layer and a photoresist mask layer disposed over the etch layer. In some embodiments, the semiconductor substrate includes the etch layer and a patterned photoresist mask layer disposed over the etch layer. In some embodiments, a material of the photoresist mask layer is a metal-containing photoresist material. The metal-containing photoresist material may include a metal selected from a group consisting of tin (Sn), bismuth (Bi), tellurium (Te), cesium (Cs), antimony (Sb), indium (In), molybdenum (Mo), hafnium (Hf), iodine (I), zirconium (Zr), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), silver (Ag), platinum (Pt), germanium (Ge), and lead (Pb). For example, the metal includes tin. The metal-containing photoresist material may include a material having a high patterning radiation absorption (e.g., an EUV absorption cross-section that is equal to or greater than IxlO⁷ cm²/mol). In some embodiments, the material of the photoresist mask layer is a metal-oxide-containing photoresist material. In some embodiments, the material of the photoresist mask layer is a metal-organic-containing photoresist material. In some embodiments, the material of the photoresist mask layer includes an EUV-sensitive photoresist material. In some examples, the material of the photoresist mask layer includes an organotin oxide.

[0058] In some embodiments, an EUV-sensitive photoresist film may be a metal oxide film, such as an EUV-sensitive tin oxide-based photoresist film. As used herein, “tin oxide” includes any and all stoichiometric possibilities for Sn_xO_y, including integer values of x and y and noninteger values of x and y. For example, “tin oxide” includes compounds having the formula SnOn, where 1 < n < 2, where n can be an integer or non-integer values. In some embodiments, “tin oxide” can include sub-stoichiometric compounds such as SnOi.s. In some embodiments, “tin oxide” also includes tin dioxide (SnO? or stannic oxide) and tin monoxide (SnO or stannous oxide). In some embodiments, “tin oxide” also includes both natural and synthetic variations and also includes any and all crystalline and molecular structures. In some embodiments, “tin oxide” also includes amorphous tin oxide.

[0059] Such resists (also referred to as imaging layers) and their formation and use are described, for example, in WO2019/217749 and W02020/102085, the disclosures of which relating to the composition, deposition, and patterning of directly photopattemable metal-organic based metal oxide films to form EUV resist masks are incorporated by reference herein in their entirety and for all purposes. As described therein, according to various embodiments, the EUV-sensitive photoresist film may be a spin-on film or a vapor deposited film.

[0060] In some embodiments, a hardmask layer may be disposed on the semiconductor substrate. In some embodiments, the hardmask layer may include SiCh, silicon nitride, a doped carbon material, or an ashable hardmask (AHM) material. In some embodiments, the AHM material may be composed of an amorphous carbon film. In some embodiments, the amorphous carbon film may be undoped or doped with boron (B) or tungsten (W), for example. Suitable amorphous carbon films may have a composition including about 50 to 80 atomic % carbon (C), 10 to 20 atomic % hydrogen (H), and 5 to 40 atomic % B or W dopant, for example.

[0061] In some embodiments, the patterned photoresist mask layer includes a line-space pattern 200. As shown in Figure 2A, in some embodiments, the line-space pattern 200 includes a first photoresist line 204 A, a second photoresist line 204B, and a space 208 disposed between the first photoresist line 204A and the second photoresist line 204B. In some embodiments, an ion beam 202 can be delivered at a particular angle of incidence in order to target the patterned photoresist mask. It should be appreciated that the “angle of incidence” is the angle formed between the incident line and the perpendicular line from the surface of the substrate. Additional information regarding hardware and the operations to adjust ion beam angles is disclosed in PCT/US25/15389 filed on February 11, 2025, which is herein incorporated by reference in its entirety.

[0062] The ion beam 202 may be delivered in a particular direction relative to the orientation and pattern of the line-space pattern 200. In some embodiments, the semiconductor substrate is disposed on a support or stage 206 that is rotatable. In some embodiments, the support or stage 206 is rotatable about 180 degrees. As the semiconductor substrate rotates, the ion beam 202 may be delivered to the line-space pattern 200 in a direction that is parallel or perpendicular to the pattern of the line-space pattern 200.

[0063] Figure 2B illustrates a schematic diagram of an ion beam interacting with a line-space pattern 200 to remove contaminants or defects from spaces between the lines , according to some embodiments. Similar to Figure 2A, the semiconductor substrate in Figure 2B includes a patterned photoresist mask that has the line-space pattern 200. As shown in Figure 2B, the linespace pattern 200 includes the first photoresist line 204 A, the second photoresist line 204B, and the space 208 disposed between the first photoresist line 204A and the second photoresist line 204B. As shown in Figure 2B, contaminants or defects may form in the space.

[0064] In some embodiments, the contaminants or defects may be from residual photoresist from the lithography process or a byproduct of the photoresist. Such contaminants or defects may occur as a result of non-optimal Gaussian distribution of light during exposure and stochastic effects, exposure to moisture and/or oxygen during bake, exposure to moisture and/or oxygen during queue time, poor selectivity during development, and residual etch byproducts formed after development. In some embodiments, the contaminants or defects may be other material that forms at the bottom of the photoresist features during the photolithography process or during subsequent storage or transport of the semiconductor substrate.

[0065] In some embodiments, the contaminants or defects may be characterized as scum 212A, 212B and/or a nanobridge 210. In some embodiments, the scum 212A, 212B may include nondesirable carbon-containing material. In some embodiments, the scum 212A, 212B may include clusters of metal oxide that reside after development in the space 208. In some embodiments, the scum 212A, 212B may include residual etch byproducts that reside after development. For instance, vapors of halogen-containing gases may react with moisture or oxygen to form residual etch byproducts that are difficult to remove. As shown in Figure 2B, the scum 212A may be disposed on a sidewall of the first photoresist line 204A and the scum 212B may be disposed on the sidewall of the first photoresist line 204A and on a sidewall of the second photoresist line 204B. In some embodiments, the nanobridge 210 may from a “bridge-like” connection between the sidewall of the first photoresist line 204A and the sidewall of the second photoresist line 204B. [0066] In some embodiments, the ion beam 202 is delivered parallel or substantially parallel to the first photoresist line 204A and the second photoresist line 204B in the patterned photoresist mask to remove the contaminants or defects from the space 208 and to reduce LWR. The term “substantially parallel” as used throughout this disclosure refers to a direction that is within plus or minus 5 degrees of a parallel direction. Where ion beam etching in conventional applications delivers ion beams in directions that are perpendicular to the orientation or pattern of patterned features, ion beam etching in the present disclosure delivers ion beams in a direction parallel or substantially parallel to the orientation or pattern of the line-space pattern 200.

[0067] In some embodiments, the ion beam 202 is delivered in a direction parallel or substantially parallel to a surface of the semiconductor substrate that is relatively shallow. In some embodiments, the ion beam 202 is delivered in a direction parallel or substantially parallel to the surface of the semiconductor substrate that is equal to or less than about 30 degrees, equal to or less than about 25 degrees, equal to or less than about 20 degrees, equal to or less than about 15 degrees, between about 5 degrees and about 25 degrees, or between about 5 degrees and about 15 degrees. Ion beam etching in conventional applications delivers the ion beams in the directions that are perpendicular to the orientation or the pattern of patterned features at steep angles (e.g., greater than 30 degrees). Ion beam etching in the present disclosure delivers the ion beams in the direction parallel or substantially parallel to the orientation or the pattern of the line-space pattern 200 at shallow angles (e.g., equal to or less than 30 degrees). For line-space patterns, delivering the ion beams in the direction parallel or substantially parallel to the orientation or the pattern of the line-space pattern 200 results in less etch of the bottom material.

Apparatus

[0068] Figure 3 depicts a schematic diagram of an example ion beam etching apparatus, according to some implementations. As shown in Figure 3, an ion beam etching apparatus 310 includes a processing chamber 312 with a substrate holder 314 for supporting a substrate 316. In some embodiments, the substrate 316 may be a semiconductor wafer. In some embodiments, the substrate 316 may be attached to the substrate holder 314 using any suitable technique. For example, the substrate 316 may be mechanically or electrostatically connected to the substrate holder 314. In some embodiments, the substrate holder 314 provides precise tilting and rotation and may include an electrostatic chuck (ESC) to engage the substrate 316.

[0069] In some embodiments, the ion beam etching apparatus 310 further includes an ion beam source chamber 322, where the processing chamber 312 may be outside of and coupled to the ion beam source chamber 322. In some embodiments, the ion beam source chamber 322 may be separated from the processing chamber 312 by an ion extractor 340 and/or mechanical shutter 348. In some embodiments, an inductive coil 332 may be arranged around an outer wall of the ion beam source chamber 322. In some embodiments, a plasma generator 334 supplies RF power to the inductive coil 332. In some embodiments, the plasma generator 334 may include an RF source 336 and a matching network 338. In some embodiments, in use, a gas mixture is introduced to the ion beam source chamber 322 and RF power is supplied to the inductive coil 332 to generate plasma in the ion beam source chamber 322, where the plasma produces ions.

[0070] In some embodiments, the ion beam etching apparatus 310 further includes a first gas delivery system 350 that is fluidly coupled to the ion beam source chamber 322. In some embodiments, the first gas delivery system 350 delivers one or more gas mixtures to the ion beam source chamber 322. The first gas delivery system 350 may include one or more gas sources 352, valve(s) 354, mass flow controller(s) (MFCs) 356, and a mixing manifold 358 that are in fluid communication with the ion beam source chamber 322. In some embodiments, the first gas delivery system 350 is configured to deliver an inert gas such as argon (Ar), xenon (Xe), or krypton (Kr). In some embodiments the first gas delivery system 350 delivers gas mixtures that include reactive chemistries. The reactive chemistries may or may not be combined with inert gas. In some embodiments, the reactive chemistries include an oxygen-containing chemistry, a halogencontaining chemistry, a hydrogen, a hydrocarbon chemistry, a nitrogen-containing chemistry, or combinations thereof.

[0071] In some embodiments, the ion extractor 340 extracts positive ions from the plasma and accelerates the positive ions in a beam towards the substrate 316. In some embodiments, the ion extractor 340 may include a plurality of electrodes that form a grid or grid system. As shown in Figure 3, the ion extractor 340 includes three electrodes, where a first electrode 342, a second electrode 344, and a third electrode 346 are present in that order from the first gas delivery system 350. In some embodiments, a positive voltage is applied to the first electrode 342 and a negative voltage is applied to the second electrode 344 so that ions are accelerated due to a difference in their potentials. In some embodiments, the third electrode 346 is grounded. A difference in potentials between the second electrode 344 and the third electrode 346 is controlled to control a diameter of an ion beam. In some embodiments, application of DC voltage to the ion extractor 340 may be controlled to cause the ion beam to be delivered to continuously or in pulses.

[0072] In some embodiments, the mechanical shutter 348 is adjacent to the ion extractor 340. In some embodiments, a neutralizer 360 may supply electrons into the processing chamber 312 to neutralize the charge of the ion beam passing through the ion extractor 340 and the mechanical shutter 348, where the neutralizer 360 may have its own gas delivery system using an inert gas such as argon or xenon. In some embodiments, the ion extractor 340 and/or mechanical shutter 348 may be controlled to cause the ion beam to be delivered to the substrate 316 continuously or in pulses.

[0073] In some embodiments, a position controller 366 may be used to control a position of the substrate holder 314. In some embodiments, the position controller 366 can control a tilt angle about a tilt axis and rotation of the substrate holder 314 to position the substrate 316. In some embodiments, an endpoint detector 368 may be used to sense a location of the ion beam relative to the substrate 316 and/or substrate holder 314. In some embodiments, a pump 370, such as a turbomolecular pump, may be used to control pressure in the processing chamber 312 and evacuate reactants from the processing chamber 312.

[0074] In some embodiments, the ion beam etching apparatus 310 optionally includes a second gas delivery system 380 fluidly coupled to the processing chamber 312. In some embodiments, the second gas delivery system 380 delivers one or more gas mixtures directly into the processing chamber 312 without passing the gas mixtures through the ion beam source chamber 322. In some embodiments, the second gas delivery system 380 may include one or more gas sources 382, valve(s) 384, mass flow controller(s) (MFCs) 386, and a mixing manifold 388 that are in fluid communication with the processing chamber 312. In some embodiments, the second gas delivery system 380 is configured to deliver a reactive gas such as an oxygen-containing gas. In some embodiments, the oxygen-containing gas can be used to remove surface roughness. In some embodiments, oxygen ions can react with a metal oxide photoresist to increase metal-oxide crosslinking by removing the remaining organic contents in the metal oxide photoresist.

[0075] In some embodiments, the ion beam etching apparatus 310 may further include a controller 390. In some embodiments, the controller 390 (which may include one or more physical or logical controllers) controls some or all of the operations of the ion beam etching apparatus 310. In some embodiments, the controller 390 may be used to control the plasma generator 334, the first gas delivery system 350, the neutralizer 360, the position controller 366, the pump 370, and the second gas delivery system 380. In some embodiments, the controller 390 may include one or more memory devices and one or more processors. In some embodiments, the processor may include a central processing unit (CPU) or computer, analog and/or digital input/output connections, stepper motor controller boards, and other like components. In some embodiments, the instructions for implementing appropriate control operations are executed on the processor. In some embodiments, the instructions may be stored on the memory devices associated with the controller 390 they may be provided over a network.

[0076] In some embodiments, the controller 390 executes system control software. In some embodiments, the system control software may include instructions for controlling the timing of application and/or magnitude of any one or more of the following chamber operational conditions: the mixture and/or composition of gases, flow rates of gases, chamber pressure, chamber temperature, substrate/substrate holder temperature, substrate position, substrate holder tilt, substrate holder rotation, voltage applied to a grid, the frequency and power applied to coils or other plasma generation components, direction of an ion beam, angle of incidence of the ion beam, and other parameters of a particular process performed by the tool. In some embodiments, the system control software may further control purge operations and cleaning operations through the pump 370. In some embodiments, system control software may be configured in any suitable way. For example, various process tool component subroutines or control objects may be written to control operations of the process tool components necessary to carry out various process tool processes. System control software may be coded in any suitable compute readable programming language.

[0077] In some embodiments, the system control software includes input/output control (IOC) sequencing instructions for controlling the various parameters described above. For example, each phase of a semiconductor fabrication process may include one or more instructions for execution by the controller 390. In some embodiments, the instructions for setting process conditions for a phase may be included in a corresponding recipe phase, for example. In some embodiments, the recipe phases may be sequentially arranged, such that steps in an ion beam etching process are executed in a certain order for that process phase. For example, a recipe may be configured to perform ion beam etch operations and include gas treatment with a reactive gas at certain time intervals.

[0078] In some embodiments, the controller 390 is configured with instructions for performing one or more of the following operations: provide, to the processing chamber 312, a substrate 316 including a metal-containing patterned photoresist mask layer disposed thereon; and expose the substrate 316 to a reactive ion beam including at least one reactive gas in a direction parallel or substantially parallel to a pattern in the metal-containing patterned photoresist mask layer. In some embodiments, the metal-containing photoresist mask layer is an EUV-sensitive metal-oxide- containing patterned photoresist mask layer. In some embodiments, the at least one reactive gas includes an oxygen-containing gas. In some embodiments, the reactive ion beam is an angled reactive ion beam having an angle of incidence that is between about 5 degrees and about 90 degrees, or between about 75 degrees and about 85 degrees.

[0079] Other computer software and/or programs may be employed in some implementations. Examples of programs or sections of programs for this purpose include substrate positioning program, a process gas composition control program, a pressure control program, a heater control program, and an RF power supply control program.

[0080] In some embodiments, the controller 390 may control these and other aspects based on sensor output (e.g., when power, potential, pressure, gas levels, etc. reach a certain threshold), the timing of an operation (e.g., opening valves at certain times in a process, pulsing ion beam delivery, pulsing gas treatment delivery, etc.), or based on received instructions from the user.

[0081] Broadly speaking, the controller 390 may be defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller 390 in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor substrate or to a system. The operational parameters may, in some implementations, be part of a recipe defined by process engineers to accomplish one or more processing steps during the patterning on a substrate.

[0082] In some embodiments, the controller 390 may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller 390 may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the substrate processing. In some embodiments, the computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some embodiments, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. In some embodiments, the remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some embodiments, the controller 390 receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller 390 is configured to interface with or control. Thus as described above, the controller 390 may be distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller 390 for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

[0083] As noted above, depending on the process step or steps to be performed by the tool, the controller 390 might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller 390, or tools used in material transport that bring containers of substrates to and from tool locations and/or load ports in a semiconductor manufacturing factory.

Methods

[0084] Figure 4A is a process flow diagram 400A for a method for processing a semiconductor substrate, according to some embodiments. The operations of the flow diagram 400A may be performed in different orders and/or with different, fewer, or additional operations. In some embodiments, the operations of the flow diagram 400A may be implemented, at least in part, according to software stored in one or more non- transitory computer readable media.

[0085] As shown in Figure 4A, the method begins at an operation 402 that includes providing, to a processing chamber, a semiconductor substrate that includes a metal-containing patterned photoresist mask layer disposed thereon. In some embodiments, the semiconductor substrate may be a silicon or other semiconductor wafer, including wafers having one or more layers of material, such as dielectric, conducting, or semi-conducting material deposited thereon. In some embodiments, the semiconductor substrate includes a blanket layer of silicon, such as amorphous silicon, or a blanket layer of germanium. In some embodiments, the semiconductor substrate may be provided after exposure of a photoresist layer to form unexposed and exposed regions of the photoresist layer, and after development of the photoresist layer to form the metal-containing patterned photoresist mask. After development of the photoresist layer to form the metalcontaining patterned photoresist mask layer, the metal-containing patterned photoresist mask layer may include non-desirable roughness (e.g., LWR), defects, and/or contaminants.

[0086] In some embodiments, the material of the metal-containing patterned photoresist mask layer is a metal-oxide-containing photoresist material. In some embodiments, the material of the metal-containing patterned photoresist mask layer is a metal-organic-containing photoresist material or organometallic oxide-containing photoresist material. In some embodiments, the metal-containing patterned photoresist mask layer includes an EUV-sensitive photoresist material. [0087] In some embodiments, the metal-oxide-containing photoresist material, metal-organic- containing photoresist material, or organometallic oxide-containing photoresist material may include metals of tin, hafnium, tellurium, bismuth, indium, antimony, germanium, and combinations thereof. In some embodiments, the metal oxide is tin oxide. “Tin oxide” is referred to herein as including any and all stoichiometric possibilities for Sn_xO_y, including integer values of x and y and non-integer values of x and y. For example, “tin oxide” includes compounds having the formula SnO„, where 1 < n < 2, where n can be an integer or non-integer values. “Tin oxide” can include sub-stoichiometric compounds such as SnOi.s. “Tin oxide” also includes tin dioxide (SnCh or stannic oxide) and tin monoxide (SnO or stannous oxide). “Tin oxide” also includes both natural and synthetic variations and also includes any and all crystalline and molecular structures. “Tin oxide” also includes amorphous tin oxide.

[0088] As shown in Figure 4A, an operation 404 follows the operation 402 and includes exposing the semiconductor substrate to a reactive ion beam including at least one reactive gas. The reactive ion beam may be delivered in a direction parallel or substantially parallel to a pattern in the metal-containing patterned photoresist mask layer. In some embodiments, the reactive ion beam may be delivered in a direction parallel or substantially parallel to the surface of the semiconductor substrate. In some embodiments, the reactive ion beam is an angled reactive ion beam. In some embodiments, an angle of incidence of the angled reactive ion beam is from about 5 degrees to about 90 degrees. As noted previously, the angle of incidence refers to the angle in which an incident line makes with a line perpendicular to a surface of the semiconductor substrate. In some embodiments, the angle of incidence ranges from about 10 to about 85 degrees, about 15 to about 80 degrees, or about 20 to about 75 degrees. In some embodiments, the angle of incidence is less than about 90 degrees, less than about 85 degrees, less than about 80 degrees, or less than about 75 degrees. The degree is measured starting at 0 degrees when the beam is directly perpendicular to the substrate surface. In some embodiments, the angle of incidence ranges from 70-75 degrees, 75-80 degrees, 80-85 degrees, or 85-90 degrees. In some embodiments, the reactive ion beam is delivered in a direction parallel or substantially parallel to a surface of the substrate that is equal to or less than about 30 degrees, equal to or less than about 25 degrees, equal to or less than about 20 degrees, equal to or less than about 15 degrees, between about 5 degrees and about 25 degrees, between about 5 degrees and about 15 degrees. Without wishing to be bound by theory, the use of a low angle of incidence may minimize physical sputtering.

[0089] In some embodiments, the ion energy of the beam may be from about 20 to about 2000 V, or from about 100 to about 1200V. In some embodiments, the pressure may be from about 5 to about 100 mTorr. In some embodiments, the ion beam current may be from about 100 to about 300 mA. In some embodiments, the RF power may be from about 800 to about 1500W.

[0090] In some embodiments, the reactive gas includes an oxy gen-containing gas, including but not limited to oxygen (O2), ozone (O3), CO, CO2, CH3OH, H2O vapor, COS, SO2, NO, N2O, NO2, a peroxide, hydrogen peroxide, an alcohol, a dihydroxy alcohol, a polyhydroxy alcohol, a fluorinated dihydroxy alcohol, a fluorinated polyhydroxy alcohol, a fluorinated glycol, formic acid, and other sources of hydroxyl moieties, as well as combinations thereof. In some embodiments, the oxygen-containing gas may be co-flowed with an inert gas; for example as a combination of oxygen and argon, or oxygen and helium.

[0091] In some embodiments, the reactive gas may be flowed at a rate of from about 5 to about 100 seem, or from about 20 to about 30 seem. In some embodiments, the oxy gen-containing gas is co-flowed with an inert gas. The oxygen-containing gases may remove non-volatile organic components and/or increase metal oxide crosslinking of metal oxide photoresists.

[0092] In some embodiments, the reactive gas includes hydrogen, a halogen-containing gas, a hydrocarbon gas, a nitrogen-containing gas, or an oxygen-containing gas. In some embodiments, the halogen-containing gas may be carbon tetrafluoride (CF4) or trifluoromethane (CHF3). In some embodiments a combination of hydrogen gas and methane may be utilized. Suitable hydrocarbon gases may be defined by the formula C> H_V, where is an integer between 2 and 10, and y is an integer between 2 and 24. Examples include methane (CH4), acetylene (C2H2), ethylene (C2H4), propylene (CjHe), butane (C4H10), cyclohexane (C6H12), benzene (CeHe), and toluene (C?Hs). In some embodiments, the reactive gas includes the hydrocarbon gas, which can be used to etch metal oxide photoresist materials or to deposit a polymer on the photoresist. In some embodiments, the nitrogen-containing gas may be nitrogen (N2), ammonia (NH3), nitric oxide (NO), or nitrous oxide (N₂O).

[0093] Use of a reactive ion beam etch is advantageous in certain embodiments over a conventional ion beam etch with an inert gas alone, as it enables chemical modification of the photoresist, thereby minimizing photoresist loss and underlayer gouging because physical sputtering is reduced.

[0094] In some embodiments, the pattern is a line-space pattern. In some embodiments, the linespace pattern includes a first photoresist line, a second photoresist line, and a space disposed between the first photoresist line and the second photoresist line. In some embodiments, at least one defect is located in the space. In some embodiments, each defect of the at least one defect is scum or a nanobridge. In some embodiments, the method of Figure 4A reduces the at least one defect. In some embodiments, the method of Figure 4A enables reduction of scum, nanobridges, contaminants, sidewall roughness or a combination thereof, and patterned mask material loss is minimized.

[0095] In some embodiments, the operation 404 concludes the method of Figure 4A.

[0096] Figure 4B is a process flow diagram 400B for a method for smoothing a patterned mask, according to some embodiments. As used herein, “smoothing” refers to decreasing roughness and/or improving planarity. The operations of the flow diagram 400B may be performed in different orders and/or with different, fewer, or additional operations. In some embodiments, the operations of the flow diagram 400B may be implemented, at least in part, according to software stored in one or more non-transitory computer readable media.

[0097] In some embodiments, the method of Figure 4B begins at an operation 406 that includes providing, to the processing chamber, the semiconductor substrate including the metal-containing patterned photoresist mask layer. In some embodiments, the pattern of the metal-containing patterned photoresist mask layer is the line-space pattern having a first roughness. In some embodiments, the material of the metal-containing patterned photoresist mask layer is a metalcontaining photoresist material, a metal-oxide-containing photoresist material, or a metal-organic- containing photoresist material. In some embodiments, the metal-containing patterned photoresist mask layer includes the EUV-sensitive photoresist film.

[0098] In some embodiments, in the method of Figure 4B, an operation 408 follows the operation 406 and includes exposing the semiconductor substrate to the reactive ion beam including the at least one reactive gas in a direction parallel or substantially parallel to the linespace pattern to produce a smoothened metal-containing patterned photoresist mask layer having a second roughness. In some embodiments, the second roughness is less than the first roughness.

[0099] In some embodiments, the reactive ion beam is the angled reactive ion beam. In some embodiments, the angle of incidence of the angled reactive ion beam is from about 5 degrees to about 90 degrees. In some embodiments, the angle of incidence of the angled reactive ion beam is from about 75 degrees to about 85 degrees.

[0100] In some embodiments, the at least one reactive gas is co-flowed with an inert gas. In some embodiments, the at least one reactive gas is hydrogen, a halogen-containing gas, a hydrocarbon gas, a nitrogen-containing gas, and/or an oxygen-containing gas. In some embodiments, the at least one reactive gas includes the oxygen-containing gas, and the oxygen- containing gas is CO, CO2, O2, CH3OH, H2O vapor, COS, SO2, NO, N2O, NO2, and/or O3.

[0101] In some embodiments, the line-space pattern includes a first photoresist line, a second photoresist line, and a space disposed between the first photoresist line and the second photoresist line. In some embodiments, the at least one contaminant is located in the space, and each contaminant of the at least one contaminant is scum or a nanobridge. In some embodiments, the method of Figure 4B reduces the at least one contaminant and/or reduces roughness of sidewalls of the first photoresist line and the second photoresist line. In some embodiments, the method of Figure 4B reduces material loss of the metal-containing patterned photoresist mask layer.

[0102] In some embodiments, the metal-containing patterned photoresist mask layer in the operation 406 includes the first thickness and the smoothened metal-containing patterned photoresist mask layer in the operation 408 includes the second thickness. The difference between the first thickness and the second thickness may less than 10 %, less than 8% less than 5% less than 3% or less than 1%. In some embodiments, a difference between the first thickness and the second thickness is less than 5 %. In some embodiments, the first roughness and the second roughness include LWR or SWR.

[0103] Purges of the process chamber may optionally be performed before or after operations disclosed in the methods provided herein. Purging the chamber may involve flowing a purge gas or a sweep gas, which may be a carrier gas used in other operations or may be a different gas. In some embodiments, purging may involve evacuating the chamber. Example purge gases are inert gases including argon, nitrogen, hydrogen, and helium. In some embodiments, a purge may include one or more evacuation subphases for evacuating the process chamber. Alternatively, it will be appreciated that purges may be omitted in some embodiments. A purge may have any suitable duration, such as between about 0 seconds and about 60 seconds, for example about 0.01 seconds. [0104] Moreover, wet or dry development may optionally be performed before exposing the substrate to the reactive ion beam. Both the process of dry development and the process of reactive ion beam etching may be performed in an integrated system which includes a dry development module, a vacuum transfer module and a reactive ion beam etch module. Examples of suitable modules include those described in WO 2020/264158, entitled “Photoresist Development with Halide Chemistries”, which is incorporated herein by reference in its entirety. In some embodiments, the patterned photoresist mask layer includes an organo-tin oxide material. Subsequent negative tone development, a tin oxide material remains.

[0105] In some embodiments, the operation 408 concludes the method of Figure 4B.

[0106] Figure 4C is a process flow diagram 400C for a method for processing a semiconductor substrate, according to some embodiments. As shown in Figure 4C, the method begins at an operation 410 that includes providing, to the processing chamber, the semiconductor substrate comprising the metal-containing patterned photoresist mask layer disposed thereon. In some embodiments, in the method of Figure 4C, an operation 412 follows the operation 410 and includes exposing the semiconductor substrate to the reactive ion beam that includes the at least one reactive gas at the angle of incidence from about 5 degrees to about 90 degrees. In some embodiments, the reactive ion beam is configured to reduce roughness in the metal-containing patterned photoresist mask layer and/or remove the at least one defect in the metal-containing patterned photoresist mask layer. In some embodiments, each defect of the at least one defect is scum or a nanobridge. In some embodiments, the angle of incidence is from about 75 degrees to about 85 degrees. In some embodiments, the operation 412 concludes the method of Figure 4C.

[0107] Figure 4D is a process flow diagram 400D for a method for processing a semiconductor substrate, according to some embodiments. As shown in Figure 4D, the method begins at an operation 414 that includes providing, to the processing chamber, the semiconductor substrate that includes the hardmask layer disposed thereon. In some embodiments, the hardmask layer is the AHM layer. In some embodiments, the hardmask layer comprises the SOC hardmask.

[0108] In some embodiments, in the method of Figure 4D, an operation 416 follows the operation 414 and includes exposing the semiconductor substrate to the reactive ion beam that includes the at least one reactive gas in the direction parallel or substantially parallel to the pattern in the hardmask layer. In some embodiments, the reactive ion beam is configured to reduce roughness in the hardmask layer and/or remove the at least one defect in the hardmask layer. In some embodiments, each defect of the at least one defect is scum or a nanobridge. In some embodiments, the operation 416 concludes the method of Figure 4D.

[0109] Figure 5 is a process flow diagram 500 for a method for polymer deposition on a semiconductor substrate, according to some embodiments. As shown in Figure 5, the method begins at an operation 502 that includes providing, to the processing chamber, the semiconductor substrate including the metal-containing patterned photoresist mask layer. In some embodiments, the pattern of the metal-containing patterned photoresist mask layer is the line-space pattern.

[0110] In some embodiments, an operation 504 follows the operation 502 and includes exposing the semiconductor substrate to a reactive ion beam including a first reactive gas and a reagent in a direction parallel or substantially parallel to the line-space pattern to deposit a polymer layer over the metal-containing patterned photoresist mask layer to form a protected patterned mask. In some embodiments, the first reactive gas is the hydrocarbon gas. In some embodiments, the hydrocarbon gas is methane, ethane, ethylene, propane, propylene, butane, or butylene. In some embodiments, the reagent includes hydrogen.

[0111] In some embodiments, the method of Figure 5 may further include exposing the protected patterned mask to a reactive angled ion beam including a second reactive gas. In some embodiments, the second reactive gas is the oxygen-containing gas. In some embodiments, the oxygen-containing gas is CO, CO2, O2, CH3OH, H2O vapor, COS, SO2, NO, N2O, NO2, and/or O₃.

[0112] In some embodiments, the semiconductor substrate further includes an underlayer disposed beneath the metal-containing patterned photoresist mask layer. Non-limiting examples of underlayers include dielectric layers and conducting layers, e.g., silicon oxides, silicon nitrides, silicon carbides, metal oxides, metal nitrides, metal carbides, and metal layers. In some embodiments, at least one of the metal-containing patterned photoresist mask layer and the underlayer are protected from loss of material when the protected patterned mask is exposed to the reactive angled ion beam including the second reactive gas.

[0113] As noted, purges of the process chamber may optionally be performed before or after operations in Figure 5. Purging the chamber may involve flowing a purge gas or a sweep gas, which may be a carrier gas used in other operations or may be a different gas. In some embodiments, purging may involve evacuating the chamber. Example purge gases are inert gases including argon, nitrogen, hydrogen, and helium. In some embodiments, a purge may include one or more evacuation subphases for evacuating the process chamber. Alternatively, it will be appreciated that purges may be omitted in some embodiments. A purge may have any suitable duration, such as between about 0 seconds and about 60 seconds, for example about 0.01 seconds. [0114] Moreover, wet or dry development may optionally be performed before exposing the substrate to the reactive ion beam. Both the process of dry development and the process of reactive ion beam etching may be performed in an integrated system which includes a dry development module, a vacuum transfer module and a reactive ion beam etch module.

[0115] In some embodiments, the operation 504 concludes the method of Figure 5.

[0116] Figure 6 is a process flow diagram 600 for another method of processing a semiconductor substrate, according to some embodiments. As shown in Figure 6, the method begins at an operation 602 that includes providing, to the processing chamber, the semiconductor substrate including the metal-containing patterned photoresist mask layer. In some embodiments, the pattern of the metal-containing patterned photoresist mask layer is the line-space pattern.

[0117] In some embodiments, an operation 604 follows the operation 602 and includes exposing the semiconductor substrate to at least one cycle. Each cycle of the at least one cycle includes an operation 606 and an operation 608. In some embodiments, the operation 606 includes exposing the semiconductor substrate to the reactive angled ion beam including the first reactive gas and the first reagent at the angle parallel to the line-space pattern to deposit the polymer layer over the metal-containing patterned photoresist mask layer. In some embodiments, the operation 608 includes exposing the semiconductor substrate to the reactive angled ion beam including a second reactive gas and a second reagent. In some embodiments, the operation 606 occurs sequentially before the operation 608. In some embodiments, the operation 608 occurs sequentially before the operation 606.

[0118] In some embodiments, the first and second reactive gas may be the same gas, and the first and second reagent may be the same reagent. In some embodiments, each of the first reactive gas and the second reactive gas include the hydrocarbon gas. In some embodiments, each of the first reagent and the second reagent include hydrogen or oxygen. In one example, the first and second reactive gases are each methane, and the first and second reagents are each hydrogen. When more methane is present, deposition occurs. When more hydrogen is present, etch occurs.

[0119] In some embodiments, the first and second reactive gases and the first and second reagents may be flowed continuously into the process chamber or may be delivered in pulses.

[0120] In some embodiments, etching may occur prior to deposition to remove contaminants, such as scum and nanobridges. In some embodiments, deposition may occur before etching to deposit the polymer on line break defects to improve the line break defects.

[0121] It should be appreciated that the operations 606 and 608 may be repeated for as many cycles necessary to obtain the desired result. In some embodiments, 10 cycles or less, 9 cycles or less, 8 cycles or less, 7 cycles or less, 6 cycles or less, 5 cycles or less, 4 cycles or less, or 3 cycles or less may be performed.

[0122] As noted previously, purges of the process chamber may optionally be performed before or after the operations disclosed in Figure 6. Purging the chamber may involve flowing a purge gas or a sweep gas, which may be a carrier gas used in other operations or may be a different gas. In some embodiments, purging may involve evacuating the chamber. Example purge gases are inert gases including argon, nitrogen, hydrogen, and helium. In some embodiments, a purge may include one or more evacuation subphases for evacuating the process chamber. Alternatively, it will be appreciated that purges may be omitted in some embodiments. A purge may have any suitable duration, such as between about 0 seconds and about 60 seconds, for example about 0.01 seconds.

[0123] Moreover, wet or dry development may optionally be performed before exposing the substrate to the reactive ion beam. Both the process of dry development and the process of reactive ion beam etching may be performed in an integrated system which includes a dry development module, a vacuum transfer module and a reactive ion beam etch module.

[0124] In some embodiments, the operation 608 or the operation 606 concludes the method of Figure 6.

Examples

[0125] Figure 7 depicts scanning transmission electron microscopy (STEM) images of photopatterned substrates subjected to smoothening, according to some embodiments. In Figure 7, STEM images of a first example wafer 702A, a second example wafer 704 A, and a third example wafer 706A are depicted before ion beam etching. The CD loss (or LnCD measured in nm), the LWR, and the space width roughness (SWR) of the first example wafer 702A, the second example wafer 704A, and the third example wafer 706A are shown in Figure 7.

[0126] Figure 7 also depicts STEM images of a first example wafer 702B, a second example wafer 704B, and a third example wafer 706B after ion beam etching. As noted, ion beam etching removes contaminants/defects in spacing. Each of the first example wafer 702B, the second example wafer 704B, and the third example wafer 706B were exposed to the reactive ion beam including at least one reactive gas. Pure argon gas was used in the first example wafer 702B. Argon and oxygen gas was used in the second example wafer 704B. Further, pure oxygen gas was used in the third example wafer 706B. As shown, the LnCD, the LWR, and the SWR decreased for each of the first example wafer 702B, the second example wafer 704B, and the third example wafer 706B, as compared to the first example wafer 702A, the second example wafer 704A, and the third example wafer 706 A, respectively, that were not subjected to the ion beam etching.

[0127] Specifically, as shown in Figure 7, the delta LnCD (or CD loss) subsequent the ion beam etching was lowest for the third example wafer 706B at 2.505 (or 2.505 nm CD loss). In comparison to use of a conventional inert gas ion beam etch, the use of oxygen gas results in significantly reduced CD loss. Without wishing to be bound by theory, the use of a lighter element of lower atomic mass may minimize the physical sputtering attained with use of heavier inert gases. This may be evidenced in that when a conventional inert gas such as argon is used (e.g., the first example wafer 702B), it leaves more defects than when oxygen gas (e.g., the third example wafer 706B) is used.

[0128] In some embodiments, typical process conditions of oxygen ion beam include a pressure ranging from about 5 mTorr to about 100 mTorr, an RF power ranging from about 800 W to about 1500 W, a flow of the oxygen gas ranging from about 20 seem to about 30 seem, an ion beam voltage ranging from about 100 V to about 1200 V, an ion beam current ranging from about 220 mA to about 250 mA, and the angle of incidence of about 85 degrees. In one embodiment of the ion beam etching with the oxygen-containing gas, the process conditions include the RF power of about 1200 W, the flow of the oxygen gas of about 22 seem, the ion beam voltage of about 1200 V, the ion beam current of about 220 mA, and the angle of incidence of about 85 degrees.

[0129] Figure 8 depicts power spectral density (PSD) curves over various frequencies illustrating line width reduction, according to some embodiments. Specifically, the PSD curves visually represents how the power of a signal is distributed across different frequencies. Roughness can have high and low frequency components, and these components can be represented using the PSD curve. PSD curves are typically plotted on a log-log plot. The horizontal x-axis represents the spatial frequency of the roughness (which is also the inverse of the wavelength of the roughness, i.e. O.Olnm ¹ = lOOnm), and the vertical axis is the PSD value (nm³), which linearly correlates with LER or LWR. The area under the PSD curve represents the total variance, and ideally should be minimized for any etch process.

[0130] EUV lithography resists post-exposure have two general categories of roughness: low frequency and high frequency. High frequency roughness is characterized by short variations in the resist and may be caused by a variety of factors, including the secondary electron that is emitted inherently in the EUV lithography process. This is the area to the right on the PSD curves, at about 0.1 nm ¹ or higher. Low frequency roughness is longer wavelength variation in the resist, and is shown on the left part of PSD curves, at about 0.01 nm ¹ or lower. One cause of low frequency roughness is compressive stress within the resist. Compressive stress within the resist causes it to buckle and/or bulge, creating low frequency roughness, sometimes referred to as “wiggling.” [0131] PSD curves are depicted in Figure 8 for a first example wafer 802, a second example wafer 804, and a third example wafer 806 both pre-ion beam etching 808 and post-ion beam etching 810. As noted, ion beam etching removes contaminants/defects in spacing. Each of the first example wafer 802, the second example wafer 804, and the third example wafer 806 were exposed to the reactive ion beam including at least one reactive gas. Pure argon gas was used in the first example wafer 802. Argon and oxygen gas was used in the second example wafer 804. Further, pure oxygen gas was used in the third example wafer 806.

[0132] As shown in each of the first example wafer 802, the second example wafer 804, and the third example wafer 806, the PSD was higher pre-ion beam etching 808 as compared to post-ion beam etching 810 at a middle frequency ranging from about 0.01 to about 0.1, indicating that the LWR was higher pre-ion beam etching 808 as compared to post-ion beam etching 810.

[0133] Further, Figure 8 displays the LnCD, the LWR, and the SWR both pre-ion beam etching (e.g., the LnCD 812 and the LWR/SWR 814) and post-ion beam etching (e.g., the LnCD 816 and the LWR/SWR 818) for the first example wafer 802, the second example wafer 804, and the third example wafer 806. As shown, the LnCD 816 and the LWR/SWR 818 are lower than the LnCD 812 and the LWR/SWR 814 for each of the first example wafer 802, the second example wafer 804, and the third example wafer 806.

[0134] Figure 9 depicts STEM images of photopattemed substrates subjected to smoothening, illustrating reduced photoresist material loss, according to some embodiments. Figure 9 depicts an example wafer pre-ion beam etch 902, post-ion beam etch using argon gas 904, and post-ion beam etch using oxygen gas 906. As shown in Figure 9, the LnCD is highest for the example wafer pre- ion beam etch 902, as compared to the example wafer post-ion beam etch using argon gas 904 and the example wafer post-ion beam etch using oxygen gas 906. As shown in Figure 9, an amount of a photoresist 908 remaining and an amount of carbon 910 undercut is highest post-ion beam etch using oxygen gas 906. As such, the STEM images show that post-EUV exposure, the ion beam etching treatments described herein result in less photoresist material loss.

Further Implementations

[0135] The apparatus and processes described herein may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, though not necessarily, such apparatus and processes will be used or conducted together in a common fabrication facility. Lithographic patterning of a film typically includes some or all of the following steps, each step enabled with a number of possible tools: (1) application of photoresist on a work piece, i.e., a substrate, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or UV curing tool; (3) exposing the photoresist to visible or UV or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove resist and thereby pattern it using a tool such as a wet bench; (5) transferring the resist pattern into an underlying film or work piece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.

Definitions

[0136] As used herein, the term “about” is understood to account for minor increases and/or decreases beyond a recited value, which changes do not significantly impact the desired function of the parameter beyond the recited value(s). In some cases, “about” encompasses +/- 10% of any recited value. As used herein, this term modifies any recited value, range of values, or endpoints of one or more ranges.

[0137] As used herein, the terms “top,” “bottom,” “upper,” “lower,” “above,” and “below” are used to provide a relative relationship between structures. The use of these terms does not indicate or require that a particular structure must be located at a particular location in the apparatus.

[0138] The term “carrier gas” may generally represent a gas used various processes to transport a chemical vapor. Suitable carrier gases include inert gases such as nitrogen (N2), argon (Ar), helium (He), neon (Ne), and krypton (Kr).

[0139] The term “chemical vapor deposition” (CVD) may generally represent a process for depositing a film on a substrate by flowing one or more chemicals over the substrate under conditions which cause the chemicals to form a film on the substrate.

[0140] By “deposition” or “vapor deposition” is meant a process in which a metal layer is formed on one or more surfaces of a substrate from vaporized precursor composition(s) including one or more metal containing compounds. The metal-containing compounds are vaporized and directed to and/or contacted with one or more surfaces of a substrate (i.e., semiconductor substrate or semiconductor assembly) placed in a deposition chamber. Typically, the substrate is heated. These metal containing compounds form a non-volatile, thin, uniform metal-containing layer on the surface(s) of the substrate. One operation of the method is one cycle, and the process can be repeated for as many cycles necessary to obtain the desired metal thickness.

[0141] The term “film” may generally represent a layer of material deposited on a substrate.

[0142] As used herein, “metal-containing film” refers to a film only including metal or a film which contains a metal and additional components.

[0143] As used herein, “metal-containing photoresist” includes, but is not limited to a metal photoresist, a metalloid photoresist, a metal oxide photoresist or an organometal oxide photoresist. [0144] The term “processing chamber’’ may generally represent an enclosure in which chemical and/or physical processes are performed on substrates.

[0145] The term “processing gas outlet” may generally represent a structure for injecting a gasphase processing chemical into a processing chamber of a processing tool. A processing gas outlet may include a nozzle or showerhead in various examples. Example processing chemicals include film precursors, reactants, and inert gases.

[0146] The term “processing tool” may generally represent a machine including a processing chamber and other hardware configured to enable processing to be carried out in the processing chamber.

[0147] The term “substrate” may generally represent any object on which a film can be deposited.

[0148] In the present disclosure, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. One of ordinary skill in the art would understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of many stages of integrated circuit fabrication. A wafer or substrate used in the semiconductor device industry typically has a diameter of 200 mm, or 300 mm, or 450 mm. The following detailed description assumes the present disclosure is implemented on a wafer. However, the present disclosure is not so limited. The work piece may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other work pieces that may take advantage of the present disclosure include various articles such as printed circuit boards and the like.

[0149] It is understood that throughout this specification the identifiers “first” and “second” are used solely to aid in distinguishing the various components and/or steps of the disclosed subject matter. The identifiers “first” and “second” are not intended to imply any particular order, amount, preference or importance to the components and/or steps modified by these terms.

Conclusion

[0150] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

CLAIMS What is claimed is:

1. A method for processing a semiconductor substrate, the method comprising: providing, to a processing chamber, a semiconductor substrate comprising a metalcontaining patterned photoresist mask layer disposed thereon; and exposing the semiconductor substrate to a reactive ion beam comprising at least one reactive gas in a direction parallel or substantially parallel to a pattern in the metal-containing patterned photoresist mask layer.

2. The method of claim 1 , wherein a material of the metal-containing patterned photoresist mask layer is a metal-oxide-containing photoresist material.

3. The method of claim 1 , wherein a material of the metal-containing patterned photoresist mask layer is a metal-organic-containing photoresist material.

4. The method of claim 1 , wherein the metal-containing patterned photoresist mask layer comprises an Extreme Ultraviolet (EUV)-sensitive photoresist film.

5. The method of claim 1 , wherein the reactive ion beam is an angled reactive ion beam.

6. The method of claim 5, wherein an angle of incidence of the angled reactive ion beam is from about 5 degrees to about 90 degrees.

7. The method of claim 6, wherein an angle of incidence of the angled reactive ion beam is from about 75 degrees to about 85 degrees.

8. The method of claim 1 , wherein the at least one reactive gas is selected from the group consisting of hydrogen, a halogen-containing gas, a hydrocarbon gas, a nitrogen-containing gas, and an oxy gen-containing gas.

9. The method of claim 8, wherein the at least one reactive gas comprises the oxy gencontaining gas, and wherein the oxygen-containing gas is selected from the group consisting of CO, CO₂, O₂, CH3OH, SO2, and O₃.

10. The method of claim 1, wherein the pattern is a line-space pattern, and wherein the linespace pattern comprises a first photoresist line, a second photoresist line, and a space disposed between the first photoresist line and the second photoresist line.

11. The method of claim 10, wherein at least one defect is located in the space.

12. The method of claim 11, wherein each defect of the at least one defect is selected from the group consisting of scum and a nanobridge.

13. The method of claim 11, wherein the method reduces the at least one defect.

14. The method of claim 10, wherein the method reduces roughness of sidewalls of the first photoresist line and the second photoresist line.

15. The method of claim 1, wherein the method reduces material loss of the metal-containing patterned photoresist mask layer.

16. The method of claim 1 , further comprising dry developing or wet developing the semiconductor substrate to form the metal-containing patterned photoresist mask layer before exposing the semiconductor substrate to the reactive ion beam.

17. A method for smoothing a patterned mask, the method comprising: providing, to a processing chamber, a semiconductor substrate comprising a metalcontaining patterned photoresist mask layer, wherein a pattern of the metal-containing patterned photoresist mask layer is a line-space pattern having a first roughness; and exposing the semiconductor substrate to a reactive ion beam comprising at least one reactive gas in a direction parallel or substantially parallel to the line-space pattern to produce a smoothened metal-containing patterned photoresist mask layer having a second roughness, wherein the second roughness is less than the first roughness.

18. The method of claim 17, wherein the line-space pattern comprises a first photoresist line, a second photoresist line, and a space disposed between the first photoresist line and the second photoresist line.

19. The method of claim 18, wherein at least one defect is located in the space, and wherein each defect of the at least one defect is selected from the group consisting of scum and a nanobridge.

20. The method of claim 19, wherein at least one of: (i) the method reduces the at least one defect; and (ii) the method reduces roughness of sidewalls of the first photoresist line and the second photoresist line.

21. The method of claim 17, wherein the method reduces material loss of the metalcontaining patterned photoresist mask layer.

22. The method of claim 17, wherein: the metal -containing patterned photoresist mask layer comprises a first thickness, the smoothened metal-containing patterned photoresist mask layer comprises a second thickness, and a difference between the first thickness and the second thickness is less than 5 percent.

23. The method of claim 17, wherein the first roughness and the second roughness comprise line width roughness (LWR).

24. The method of claim 17, wherein the first roughness and the second roughness comprise space width roughness (SWR).

25. The method of claim 17, wherein the reactive ion beam is an angled reactive ion beam.

26. The method of claim 25, wherein an angle of incidence of the angled reactive ion beam is from about 5 degrees to about 90 degrees.

27. The method of claim 17, wherein the at least one reactive gas is co-flowed with an inert gas.

28. The method of claim 17, wherein the at least one reactive gas is selected from the group consisting of hydrogen, a halogen-containing gas, a hydrocarbon gas, a nitrogen-containing gas, and an oxygen-containing gas.

29. The method of claim 28, wherein the at least one reactive gas comprises the oxygencontaining gas, and wherein the oxygen-containing gas is selected from the group consisting of CO, CO₂, O₂, CH3OH, H₂O vapor, COS, SO₂, NO, N₂O, NO₂, and O₃.

30. The method of claim 17, wherein a material of the metal-containing patterned photoresist mask layer is a metal-oxide-containing photoresist material, a metal-organic-containing photoresist material, or an organometallic oxide-containing photoresist material.

31. The method of claim 17, wherein the metal-containing patterned photoresist mask layer comprises an Extreme Ultraviolet (EUV)-sensitive photoresist film.

32. The method of claim 17, further comprising dry developing or wet developing the semiconductor substrate to form the metal-containing patterned photoresist mask layer before exposing the semiconductor substrate to the reactive ion beam.

33. A method for polymer deposition on a semiconductor substrate, the method comprising: providing, to a processing chamber, a semiconductor substrate comprising a metalcontaining patterned photoresist mask layer, wherein a pattern of the metal-containing patterned photoresist mask layer is a line-space pattern; and exposing the semiconductor substrate to a reactive ion beam comprising a first reactive gas and a reagent in a direction parallel or substantially parallel to the line-space pattern to deposit a polymer layer over the metal-containing patterned photoresist mask layer to form a protected patterned mask, wherein the first reactive gas is a hydrocarbon gas.

34. The method of claim 33, wherein the hydrocarbon gas is selected from the group consisting of methane, ethane, ethylene, propane, propylene, butane, and butylene, and wherein the reagent comprises hydrogen.

35. The method of claim 33, further comprising: exposing the protected patterned mask to a reactive angled ion beam comprising a second reactive gas, wherein the second reactive gas is an oxygen-containing gas.

36. The method of claim 35, wherein the oxygen-containing gas is selected from the group consisting of CO, CO₂, O₂, CH3OH, H₂O vapor, COS, SO₂, NO, N₂O, NO₂, and O₃.

37. The method of claim 33, wherein the semiconductor substrate further comprises an underlayer disposed beneath the metal-containing patterned photoresist mask layer.

38. The method of claim 37, wherein at least one of the metal-containing patterned photoresist mask layer and the underlayer are protected from loss of material when the protected patterned mask is exposed to the reactive angled ion beam comprising the second reactive gas.

39. A method of processing a semiconductor substrate, the method comprising: providing, to a processing chamber, a semiconductor substrate comprising a metalcontaining patterned photoresist mask layer, wherein a pattern of the metal-containing patterned photoresist mask layer is a line-space pattern; exposing the semiconductor substrate to at least one cycle, wherein each cycle of the at least one cycle comprises:

(i) exposing the semiconductor substrate to a reactive angled ion beam comprising a first reactive gas and a first reagent in a direction parallel or substantially parallel to the line-space pattern to deposit a polymer layer over the metal-containing patterned photoresist mask layer; and

(ii) exposing the semiconductor substrate to the reactive angled ion beam comprising a second reactive gas and a second reagent.

40. The method of claim 39, wherein operations (i) and (ii) are performed sequentially as: (i) and (ii).

41. The method of claim 39, wherein operations (i) and (ii) are performed sequentially as: (ii) and (i).

42. The method of claim 39, wherein each of the first reactive gas and the second reactive gas comprise a hydrocarbon gas.

43. The method of claim 39, wherein each of the first reagent and the second reagent comprise hydrogen or oxygen.

44. An apparatus for processing a semiconductor substrate, the apparatus comprising: a dry development module comprising: one or more process chambers, each process chamber comprising a chuck; one or more gas inlets into the process chambers and associated flow-control hardware; and a controller having at least one processor and a memory; a vacuum transfer module coupled to the dry development module; and a reactive ion beam etch module coupled to the vacuum transfer module, wherein the at least one processor and the memory are communicatively connected with one another, the at least one processor is at least operatively connected with a flow-control hardware, and the memory stores computer-executable instructions for controlling the at least one processor to at least control the flow-control hardware to: dry develop a semiconductor substrate to form a metal-containing patterned photoresist mask layer on the semiconductor substrate; and expose the metal-containing patterned photoresist mask layer to a reactive ion beam comprising a reactive gas in a direction parallel or substantially parallel to a pattern in the metal-containing patterned photoresist mask layer.

45. The apparatus of claim 44, wherein the reactive ion beam etch module is an angled reactive ion beam.

46. A method for processing a semiconductor substrate, the method comprising: providing, to a processing chamber, a semiconductor substrate comprising a metalcontaining patterned photoresist mask layer disposed thereon; and exposing the semiconductor substrate to a reactive ion beam comprising at least one reactive gas at an angle of incidence from about 5 degrees to about 90 degrees, wherein the reactive ion beam is configured to reduce roughness in the metal-containing patterned photoresist mask layer and/or remove at least one defect in the metal-containing patterned photoresist mask layer, and wherein each defect of the at least one defect is selected from a group consisting of: scum and a nanobridge.

47. The method of claim 46, wherein the angle of incidence is from about 75 degrees to about 85 degrees.

48. A method for processing a semiconductor substrate, the method comprising: providing, to a processing chamber, a semiconductor substrate comprising hardmask layer disposed thereon; and exposing the semiconductor substrate to a reactive ion beam comprising at least one reactive gas in a direction parallel or substantially parallel to a pattern in the hardmask layer.

49. The method of claim 48, wherein the hardmask layer comprises an ashable hardmask layer.

50. The method of claim 48, wherein the hardmask layer comprises a spin-on carbon (SOC) hardmask.

51. The method of claim 48, wherein the reactive ion beam is configured to reduce roughness in the hardmask layer and/or remove at least one defect in the hardmask layer, and wherein each defect of the at least one defect is selected from a group consisting of: scum and a nanobridge.