WO2025262963A1 - Receiver - Google Patents

Abstract

This receiver comprises: a first signal source (6) that outputs a first clock signal having a first frequency and a first phase; second through Mth signal sources (16, 26, 36), where M is an integer greater than or equal to 2, that output (M–1) second through Mth clock signals, each of said clock signals having the first frequency and an Mth phase that is different from the first phase; M first through Mth sample-and-hold circuits (2, 12, 22, 32) that use the M first through Mth clock signals to perform undersampling of a reception signal; M first through Mth phase shifters (5, 15, 25, 35) that shift the phases of output signals from the M first through Mth sample-and-hold circuits; and a synthesizer (9, 39) that synthesizes output signals from the M first through Mth phase shifters, wherein in the output from the M first through Mth phase shifters, components of an Nth Nyquist zone are of the same phase as each other, and components of Nyquist zones other than the Nth Nyquist zone are not of the same phase as each other.

Description

Receiver

This disclosure relates to a receiver.

A receiver is a circuit that receives radio waves propagating through space. For example, a receiver is composed of an antenna, a filter, a frequency converter such as a mixer, an ADC (Analog to Digital Converter), and an arithmetic circuit (also called a logic circuit or digital circuit) such as an FPGA (Field Programmable Gate Array).

Patent Document 1, for example, shows a conventional receiver configured with multiple parallel systems each equipped with an antenna, an RF (Radio Frequency) band BPF (Band Pass Filter), an amplifier, and an undersampling ADC. In this receiver, the desired signal, spurious (also known as unwanted waves), or noise received by the antenna are suppressed using a BPF, allowing only the desired signal to pass, and the desired signal is then amplified and converted to a digital signal.

JP 2018-179724 A

However, the receiver in Patent Document 1 requires RF band BPFs to suppress spurious or noise for each system. Because RF band BPFs are large in size and cost, this poses the problem of increasing the size and cost of the receiver.

The present disclosure has been made to solve the above-mentioned problems, and aims to provide a receiver that can suppress spurious or noise without increasing the size or cost of the receiver.

One aspect of a receiver according to an embodiment of the present disclosure includes a first signal source that outputs a first clock signal having a first frequency and a first phase; second to Mth signal sources that output second to Mth (M-1) clock signals, where M is an integer greater than or equal to 2, each having the first frequency and an Mth phase that is different from the first phase; first to Mth sample-and-hold circuits that undersample a received signal using the first to Mth clock signals; first to Mth phase shifters that shift the phases of the output signals of the first to Mth sample-and-hold circuits, respectively; and a combiner that combines the output signals of the first to Mth phase shifters, wherein, in the outputs of the first to Mth phase shifters, components in the Nth (N is an integer greater than or equal to 1) Nyquist zone are in phase, and components in one or more Nyquist zones other than the Nth are not in phase.

The receiver disclosed herein does not require an RF band band filter, so spurious signals or noise can be suppressed without increasing the size or cost of the receiver.

FIG. 1 is a diagram illustrating an example of the configuration of a receiver according to a first embodiment of the present disclosure. FIG. 2 is a diagram showing the frequency spectrum of the output signal of the antenna 1. As shown in FIG. FIG. 3 is a diagram showing the frequency spectrum of the output signal of the filter 3. As shown in FIG. FIG. 4 is a table showing the initial phases of the received signal and noise N001 to N004 at the outputs of filter 3, phase shifter 5, filter 13, and phase shifter 15. FIG. 5 is a diagram illustrating a configuration example of a receiver according to the second embodiment of the present disclosure. FIG. 6 is a table showing the initial phases of the received signal and noises N001 to N004 at the outputs of the phase shifters 5, 15, 25, and 35. In FIG. FIG. 7 is a table in which values are substituted for the initial phases of the received signal and noises N001 to 004 shown in FIG.

Various embodiments of the present disclosure will be described in detail below with reference to the drawings. Note that in the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations of such parts will be omitted. Furthermore, in this disclosure, the term "or" is used to mean an inclusive logical OR unless otherwise specified.

Embodiment 1.
<Configuration>
1 is a diagram illustrating an example of the configuration of a receiver according to the first embodiment of this disclosure. The receiver includes an antenna 1, an S/H circuit 2, a filter 3, a quantizer 4, a phase shifter 5, a signal source 6, a phase control circuit 7, a phase control circuit 8, a combiner 9, an antenna 11, an S/H circuit 12, a filter 13, a quantizer 14, a phase shifter 15, a signal source 16, a phase control circuit 17, and a phase control circuit 18. f _CLK is the frequency of the first and second clock signals, θ _CLK1 is the initial phase of the first clock signal, θ _CLK2 is the initial phase of the second clock signal, f _out is the frequency of the output signals of filter 3 and filter 13, θ _out1 is the initial phase of the output signal of filter 3, θ _out2 is the initial phase of the output signal of filter 13, θ _out3 is the initial phase of the output signal of phase shifter 5, θ _out4 is the initial phase of the output signal of phase shifter 15, θ _PS1 is the amount of phase shift of phase shifter 5, and θ _PS2 is the amount of phase shift of phase shifter 15. Note that the initial phase is defined here as the phase of a signal at a certain time.

Antenna 1 is an antenna that receives signals propagating through space and outputs the received signals to S/H circuit 2. The output terminal of antenna 1 is connected to the RF terminal of S/H circuit 2. For example, antenna 1 can be an antenna such as a dipole antenna or a patch antenna. Of course, an array antenna that combines multiple element antennas can also be used. Any configuration can be used as antenna 1, as long as it can receive signals propagating through space and output the received signals.

S/H circuit 2 is a sample-and-hold (also called track-and-hold) circuit that synchronizes with the first clock signal output by signal source 6, undersamples (also called subsampling) the signal output by antenna 1, and outputs the undersampled signal to filter 3. The RF terminal of S/H circuit 2 is connected to the output terminal of antenna 1, the clock terminal of S/H circuit 2 is connected to the output terminal of signal source 6, and the output terminal of S/H circuit 2 is connected to the input terminal of filter 3. For example, S/H circuit 2 may be a circuit composed of a switch that switches between open and short circuits for the input RF signal (output signal from antenna 1) and a capacitor that stores charge when the line for the input RF signal is open. Any configuration may be used for S/H circuit 2 as long as it can undersample the input RF signal and output the undersampled signal. Here, the undersampled signal refers to the signal generated by undersampling.

Filter 3 has a predetermined passband and passes signals output by S/H circuit 2 that fall within the passband and suppresses signals in frequency bands outside the passband. Filter 3 suppresses signals or unwanted waves that fall outside the passband from the signals output by S/H circuit 2, and outputs the result to quantizer 4. The input terminal of filter 3 is connected to the output terminal of S/H circuit 2, and the output terminal of filter 3 is connected to the input terminal of quantizer 4. For example, filter 3 may be an LPF (Low Pass Filter), HPF (High Pass Filter), or BPF (Band Pass Filter). Filter 3 is implemented using elements such as chip inductors or chip capacitors. It may also be configured using other resonators such as microstrip or coaxial resonators depending on the frequency band to be passed or the required amount of suppression. Here, the passband of filter 3 is a low frequency band, and even if a BPF is used as filter 3, the size or cost is not as large as an RF band BPF.

Quantizer 4 is a circuit that quantizes the input signal and outputs the quantized signal data; it quantizes the signal output by filter 3 and outputs the quantized signal data to phase shifter 5. The input terminal of quantizer 4 is connected to the output terminal of filter 3, and the output terminal of quantizer 4 is connected to the input terminal of phase shifter 5. For example, an ADC can be used for quantizer 4. Note that when an ADC is used for quantizer 4, quantization may be performed in synchronization with an externally input clock signal. Any configuration may be used for quantizer 4 as long as it is able to quantize the input signal and output the quantized signal data.

The phase shifter 5 is a circuit that shifts the phase of an input signal and outputs the phase-shifted signal. Based on a signal indicating θ _PS1 output from the phase control circuit 8, the phase shifter 5 shifts the phase of the signal output by the quantizer 4 and outputs the phase-shifted signal to the combiner 9. The input terminal of the phase shifter 5 is connected to the output terminal of the quantizer 4, the control terminal of the phase shifter 5 is connected to the output terminal of the phase control circuit 8, and the output terminal of the phase shifter 5 is connected to a first input terminal of the combiner 9. For example, an FPGA can be used for the phase shifter 5. In this case, the FPGA shifts the phase of the input signal by changing the initial phase of an NCO (Numerically Controlled Oscillator) in an operation such as a DDC (Digital Down Converter). Alternatively, the FPGA may convert the input signal into a signal in the complex domain and perform a complex number operation to shift the phase. The phase shifter 5 may have any configuration as long as it can shift the phase of an input signal and output the phase-shifted signal.

The signal source 6 is a circuit capable of generating a signal of any signal waveform or any frequency, and generates a first clock signal having a frequency f _CLK and an initial phase θ _CLK1 to be input to the S/H circuit 2 based on a signal indicating θ _CLK1 output from the phase control circuit 7. The control terminal of the signal source 6 is connected to the output terminal of the phase control circuit 7, and the output terminal of the signal source 6 is connected to the clock terminal of the S/H circuit 2. For example, the signal source 6 may be a digital-to-analog converter (DAC), a direct digital synthesizer (DDS), or a phase-locked loop (PLL) circuit. Although not shown in FIG. 1 , the signal source 6 may generate the first clock signal using an externally input control signal or reference signal. Any configuration may be used as the signal source 6 as long as it can generate a signal of any waveform.

The phase control circuit 7 is a circuit that outputs a signal indicating θ _CLK1 to the signal source 6. The output terminal of the phase control circuit 7 is connected to the control terminal of the signal source 6. For example, an FPGA or a memory can be used for the phase control circuit 7. θ _CLK1 may be determined by calculation, or data stored in advance in a memory or the like may be read out. Any configuration may be used for the phase control circuit 7 as long as it can output a signal indicating θ _CLK1 .

The phase control circuit 8 is a circuit that outputs a signal indicating θ _PS1 to the phase shifter 5. The output terminal of the phase control circuit 8 is connected to the control terminal of the phase shifter 5. For example, an FPGA or a memory can be used for the phase control circuit 8. θ _PS1 may be determined by calculation, or data stored in advance in a memory or the like may be read out. Any configuration may be used for the phase control circuit 8 as long as it can output a signal indicating θ _PS1 .

The combiner 9 is a circuit that combines (adds) multiple input signals and outputs the combined signal. It combines the signal output by the phase shifter 5 and the signal output by the phase shifter 15 and outputs the combined signal to the outside. The first input terminal of the combiner 9 is connected to the output terminal of the phase shifter 5, and the second input terminal of the combiner 9 is connected to the output terminal of the phase shifter 15. For example, an FPGA can be used as the combiner 9. The combiner 9 may have any configuration as long as it can combine (add) multiple input signals and output a combined signal.

Antenna 11 is an antenna that receives signals propagating through space and outputs the received signals to S/H circuit 12. The output terminal of antenna 11 is connected to the RF terminal of S/H circuit 12. For example, antennas such as dipole antennas and patch antennas can be used for antenna 11. Of course, an array antenna that combines multiple element antennas can also be used. Antenna 11 can have any configuration as long as it can receive signals propagating through space and output the received signals.

S/H circuit 12 is a sample-and-hold circuit that synchronizes with the second clock signal output by signal source 16, undersamples the signal output by antenna 11, and outputs the undersampled signal to filter 13. The RF terminal of S/H circuit 12 is connected to the output terminal of antenna 11, the clock terminal of S/H circuit 12 is connected to the output terminal of signal source 16, and the output terminal of S/H circuit 12 is connected to the input terminal of filter 13. For example, S/H circuit 12 may be a circuit configured with a switch that switches between open and short circuits for the input RF signal (output signal from antenna 11) and a capacitance that stores charge when the line is open for the input RF signal. Any configuration may be used for S/H circuit 12 as long as it is able to undersample the input RF signal and output the undersampled signal.

Filter 13 has a predetermined passband and passes signals output by S/H circuit 12 that fall within the passband and suppresses signals in frequency bands outside the passband. Filter 13 suppresses signals or unwanted waves that fall outside the passband and outputs the resulting signal to quantizer 14. The input terminal of filter 13 is connected to the output terminal of S/H circuit 12, and the output terminal of filter 13 is connected to the input terminal of quantizer 14. For example, filter 13 may be an LPF, HPF, or BPF. Filter 13 is implemented using elements such as chip inductors or chip capacitors. Depending on the frequency band to be passed or the required amount of suppression, it may also be configured using other resonators such as microstrip or coaxial resonators. Here, the passband of filter 13 is a low-frequency band, and even if a BPF is used as filter 13, it does not require large size or cost, unlike an RF-band BPF.

The quantizer 14 is a circuit that quantizes the input signal and outputs the quantized signal data. It quantizes the signal output by the filter 13 and outputs the quantized signal data to the phase shifter 15. The input terminal of the quantizer 14 is connected to the output terminal of the filter 13, and the output terminal of the quantizer 14 is connected to the input terminal of the phase shifter 15. For example, an ADC can be used for the quantizer 14. Note that when an ADC is used for the quantizer 14, quantization may be performed in synchronization with an externally input clock signal. Any configuration may be used for the quantizer 14 as long as it is able to quantize the input signal and output the quantized signal data.

The phase shifter 15 is a circuit that shifts the phase of an input signal and outputs the phase-shifted signal. Based on a signal indicating θ _PS2 output from the phase control circuit 18, the phase shifter 15 shifts the phase of the signal output by the quantizer 14 and outputs the phase-shifted signal to the combiner 9. The input terminal of the phase shifter 15 is connected to the output terminal of the quantizer 14, the control terminal of the phase shifter 15 is connected to the output terminal of the phase control circuit 18, and the output terminal of the phase shifter 15 is connected to the second input terminal of the combiner 9. For example, an FPGA can be used for the phase shifter 15. In this case, the FPGA shifts the phase of the input signal by changing the initial phase of the NCO in a calculation such as a DDC. Alternatively, the FPGA may convert the input signal into a signal in the complex domain and shift the phase using a complex number calculation. The phase shifter 15 may have any configuration as long as it can shift the phase of an input signal and output a phase-shifted signal.

The signal source 16 is a circuit capable of generating a signal of any signal waveform or any frequency, and generates a second clock signal having a frequency f _CLK and an initial phase θ _CLK2 to be input to the S/H circuit 12 based on a signal indicating θ _CLK2 output from the phase control circuit 17. The control terminal of the signal source 16 is connected to the output terminal of the phase control circuit 17, and the output terminal of the signal source 16 is connected to the clock terminal of the S/H circuit 12. For example, the signal source 16 may be a DAC, a DDS, or a PLL circuit. Although not shown in FIG. 1 , the signal source 16 may generate the second clock signal using an externally input control signal or reference signal. Any configuration may be used as the signal source 16 as long as it can generate a signal of any waveform.

The phase control circuit 17 is a circuit that outputs a signal indicating θ _CLK2 to the signal source 16. The output terminal of the phase control circuit 17 is connected to the control terminal of the signal source 16. For example, an FPGA or a memory can be used for the phase control circuit 17. θ _CLK2 may be determined by calculation, or data stored in advance in a memory or the like may be read out. Any configuration may be used for the phase control circuit 17 as long as it can output a signal indicating θ _CLK2 .

The phase control circuit 18 is a circuit that outputs a signal indicating θ _PS2 to the phase shifter 15. The output terminal of the phase control circuit 18 is connected to the control terminal of the phase shifter 15. For example, an FPGA or a memory can be used for the phase control circuit 18. θ _PS2 may be determined by calculation, or data stored in advance in a memory or the like may be read out. Any configuration may be used for the phase control circuit 18 as long as it can output a signal indicating θ _PS2 .

<Operation>
Next, the operation according to the first embodiment of this disclosure will be described. For simplicity, the received signal input to this receiver is assumed to be 1.1 GHz, with f _CLK =1 GHz, θ _CLK1 =0°, θ _CLK2 =30°, θ _PS1 =0°, and θ _PS2 =30°. LPFs with a passband of 0.5 GHz are used as filters 3 and 13, ADCs are used as quantizers 4 and 14, FPGAs are used as phase shifters 5, 15, and combiner 9, FPGAs and memories are used as phase control circuits 7, 8, 17, and 18, and PLL circuits are used as signal sources 6 and 16. The memories may be internal or external to the FPGA. Phase shifters 5 and 15 convert the input signals into complex domain signals and shift the phases using complex number arithmetic. Both the ADCs used as quantizers 4 and 14 are assumed to perform quantization in synchronization with an externally input clock signal and to be oversampling. Furthermore, it is assumed that there are no spurious signals propagating through space, and that the received signal and noise arrive from the front direction relative to the receiver (the antenna plane formed by antennas 1 and 11). Furthermore, it is assumed that the initial phase of all received signals and noise is 0°.

First, in this receiver, antenna 1 and antenna 11 receive a 1.1 GHz signal and noise propagating through space and output the received signal and noise to S/H circuit 2 and S/H circuit 12. Signal source 6 generates a first clock signal with a frequency of 1 GHz and an initial phase θ _CLK1 and outputs the generated first clock signal to S/H circuit 2. Signal source 16 generates a second clock signal with a frequency of 1 GHz and an initial phase θ _CLK2 and outputs the generated second clock signal to S/H circuit 12. S/H circuit 2 undersamples the received signal and noise output by antenna 1 in synchronization with the first clock signal. S/H circuit 12 undersamples the received signal and noise output by antenna 11 in synchronization with the second clock signal.

FIG. 2 shows the frequency spectrum of the output signal of antenna 1. The horizontal axis represents frequency, and the vertical axis represents power. The solid arrow represents the received signal output by antenna 1, and N001, N002, N003, and N004 represent noise. S/H circuit 2 undersamples the signal output by antenna 1 using the first clock signal output by signal source 6. Due to undersampling, the output spectrum of S/H circuit 2 generates aliasing components at half the frequency of the first clock signal (hereinafter referred to as the Nyquist frequency), i.e., every 0.5 GHz. Here, if p is a positive integer, the frequency region from (p-1) × Nyquist frequency to p × Nyquist frequency is called the pth Nyquist zone. The output signal of S/H circuit 2 has multiple frequency components. If this frequency is f _S/H2 , f _S/H2 is expressed by the following equation (1).

where α is a sign function and takes either +1 or -1 so that the entire right-hand side of equation (1) is positive. f _in is the frequency of the signal and noise input to the S/H circuit 2, and k is an integer equal to or greater than 0. The frequency spectrum of the output signal from antenna 11 is the same as that in Figure 2, so its explanation will be omitted here.

Phase control circuit 7 outputs data indicating θ _CLK1 to signal source 6. Phase control circuit 17 outputs data indicating θ _CLK2 to signal source 16. Although not shown in FIG. 1 , θ _CLK1 and θ _CLK2 may be calculated by phase control circuits 7 and 17, or the results of calculations performed outside the receiver may be input to and stored in phase control circuits 7 and 17.

Since the clock signals input to S/H circuit 2 and S/H circuit 12 have the same frequency but different phases (θ _CLK1 ≠ θ _CLK2 ), the output signals of S/H circuit 2 and S/H circuit 12 have different phases. That is, the output signals of filter 3 and filter 13 have the same frequency but different phases. If the initial phases of the output signals of S/H circuit 2 and S/H circuit 12 are θ _S/H2 and θ _S/H12 , respectively, θ _S/H2 and θ _S/H12 are expressed by the following equations (2) and (3), respectively.

where θ _in is the initial phase of the signal and noise input to S/H circuit 2. Filters 3 and 13 pass components within the first Nyquist zone among the many frequency components contained in the output signals of S/H circuit 2 and S/H circuit 12. Figure 3 shows the frequency spectrum of the output signal of filter 3. The horizontal axis represents frequency, and the vertical axis represents power. Due to aliasing caused by undersampling in S/H circuit 2, all of the received signal and noise are frequency-converted to the first Nyquist zone. At this time, the spectrum of the received signal or noise that existed in the even-order Nyquist zone is inverted. Filter 3 suppresses the received signal and noise that exist in the second Nyquist zone or higher Nyquist zones. The frequency spectrum of the output signal of filter 13 is the same as that shown in Figure 3, so a description thereof will be omitted here.

Because noise N001 is in the first Nyquist zone, the frequency does not change between the antenna 1 output and the outputs of filters 3 and 13. That is, according to equation (1), α = 1 and k = 0. If the initial phase of noise N001 in the filter 3 output is θ _{out1_N001} , the initial phase of noise N001 in the filter 13 output is θ _{out2_N001} , and the initial phase of noise N001 in the antenna 1 output is θ _{in_N001} , then according to equations (2) and (3), α = 1 and k = 0, and therefore θ _{out1_N001} and θ _{out2_N001} are expressed by the following equations (4) and (5), respectively.

The noise N002 is frequency converted to the first Nyquist zone by undersampling. In this case, if the frequency of the noise N002 at the outputs of filters 3 and 13 is f _{out_N002} and the frequency of the noise N002 at the output of antenna 1 is f _{in_N002} , then from equation (1), f _{out_N002} can be expressed by the following equation (6).

From equation (6), α = -1 and k = -1. If the initial phase of noise N002 in the filter 3 output is θ _{out1_N002} , the initial phase of noise N002 in the filter 13 output is θ _{out2_N002} , and the initial phase of noise N002 in the antenna 1 output is θ _{in_N002} , then from equations (2) and (3), θ _{out1_N002} and θ _{out2_N002} are expressed by the following equations (7) and (8), respectively.

The received signal is frequency converted to the first Nyquist zone by undersampling. In this case, if the frequency of the received signal at the output of filter 3 and filter 13 is f _{out_S} and the frequency of the received signal at the output of antenna 1 is f _{in_S} , then from equation (1), f _{out_S} can be expressed by the following equation (9).

From equation (9), α = +1 and k = -1. If the initial phase of the received signal at the filter 3 output is θ _{out1_S} , the initial phase of the received signal at the filter 13 output is θ _{out2_S} , and the initial phase of the received signal at the antenna 1 output is θ _{in_S} , then from equations (2) and (3), θ _{out1_S} and θ _{out2_S} are expressed by the following equations (10) and (11), respectively.

The noise N003 is frequency converted to the first Nyquist zone by undersampling. In this case, if the frequency of the noise N003 at the outputs of filters 3 and 13 is f _{out_N003} and the frequency of the noise N003 at the output of antenna 1 is f _{in_N003} , then from equation (1), f _{out_N003} can be expressed by the following equation (12).

From equation (12), α = -1 and k = -2. If the initial phase of noise N003 in the filter 3 output is θ _{OUT1_N003} , the initial phase of noise N003 in the filter 13 output is θ _{OUT2_N003} , and the initial phase of noise N003 in the antenna 1 output is θ _{IN_N003} , then from equations (2) and (3), θ _{OUT1_N003} and θ _{OUT2_N003} are expressed by the following equations (13) and (14), respectively.

The noise N004 is frequency converted to the first Nyquist zone by undersampling. In this case, if the frequency of the noise N004 at the outputs of filters 3 and 13 is f _{out_N004} and the frequency of the noise N004 at the output of antenna 1 is f _{in_N004} , then from equation (1), f _{out_N004} can be expressed by the following equation (15).

From equation (15), α = +1 and k = -2. If the initial phase of noise N004 in the filter 3 output is θ _{OUT1_N004} , the initial phase of noise N004 in the filter 13 output is θ _{OUT2_N004} , and the initial phase of noise N004 in the antenna 1 output is θ _{IN_N004} , then from equations (2) and (3), θ _{OUT1_N004} and θ _{OUT2_N004} are expressed by the following equations (16) and (17), respectively.

Filters 3 and 13 are provided to prevent malfunctions caused by the input of a large number of frequency components to quantizers 4 and 14, or failures caused by the input of high-power frequency components. Because the output signals of S/H circuits 2 and 12 contain frequency components in the second or higher Nyquist zone, the filter passband or implementation method is determined so that the components in the second or higher Nyquist zones can be sufficiently suppressed. Furthermore, if the frequency components in the second or higher Nyquist zones contained in the output signals of S/H circuits 2 and 12 are outside the operable frequencies of quantizers 4 and 14, or if the power of these frequency components is low, and no malfunction or failure will occur in quantizers 4 and 14, filters 3 and 13 may be omitted and replaced with through circuits.

Quantizers 4 and 14 quantize the analog signals output by filters 3 and 13, respectively, and output the quantized signal data as digital signals to phase shifters 5 and 15, respectively. Phase shifter 5 converts the signal data output by quantizer 4 into a complex domain signal and shifts the initial phase of the signal by θ _PS1 using complex number calculations. Phase shifter 15 converts the signal data output by quantizer 14 into a complex domain signal and shifts the initial phase of the signal by θ _PS2 using complex number calculations.

Phase control circuit 8 outputs data indicating θ _PS1 to phase shifter 5. Phase control circuit 18 outputs data indicating θ _PS2 to phase shifter 15. Although not shown in FIG. 1 , θ _PS1 and θ _PS2 may be calculated by phase control circuits 8 and 18, or the results of calculations performed outside the receiver may be input to and stored in phase control circuits 8 and 18.

In this case, θ _out3 and θ _out4 are expressed by the following equations (18) and (19), respectively.

Here, if the initial phase of noise N001 at the output of phase shifter 5 is θ _{out3_N001} and the initial phase of noise N001 at the output of phase shifter 15 is θ _{out4_N001} , then from equations (4), (5), (18), and (19), θ _{out3_N001} and θ _{out4_N001} are expressed by the following equations (20) and (21), respectively.

If the initial phase of the noise N002 in the output of the phase shifter 5 is θ _{out3 — N002} and the initial phase of the noise N002 in the output of the phase shifter 15 is θ _{out4 — N002} , then from equations (7), (8), (18), and (19), θ _{out3 — N002} and θ _{out4 — N002} are expressed by the following equations (22) and (23), respectively.

If the initial phase of the received signal at the output of phase shifter 5 is θ _{out3_S} and the initial phase of the received signal at the output of phase shifter 15 is θ _{out4_S} , then from equations (10), (11), (18), and (19), θ _{out3_S} and θ _{out4_S} are expressed by the following equations (24) and (25), respectively.

If the initial phase of noise N003 in the output of phase shifter 5 is θ _{out3 — N003} and the initial phase of noise N003 in the output of phase shifter 15 is θ _{out4 — N003} , then from equations (13), (14), (18), and (19), θ _{out3 — N003} and θ _{out4 — N003} are expressed by the following equations (26) and (27), respectively.

If the initial phase of noise N004 in the output of phase shifter 5 is θ _{out3 — N004} and the initial phase of noise N004 in the output of phase shifter 15 is θ _{out4 — N004} , then from equations (16), (17), (18), and (19), θ _{out3 — N004} and θ _{out4 — N004} are expressed by the following equations (28) and (29), respectively.

Combiner 9 combines (adds) the signal and noise output by phase shifter 5 with the signal and noise output by phase shifter 15, and outputs the combined signal to the outside of the receiver. Figure 4 is a table showing the initial phases of the received signal and noise N001-004 at the outputs of filter 3, phase shifter 5, filter 13, and phase shifter 15. Note that these values were calculated by substituting θ _CLK1 = 0°, θ _CLK2 = 30°, θ _PS1 = 0°, and θ _PS2 = 30° into the equations obtained so far, and substituting an initial phase of 0° for all received signals and noise (i.e., θ _{in_S} = θ _{in_N001} = θ _{in_N002} = θ _{in_N003} = θ _{in_N004} = 0°). Figure 4 shows that the received signal output by phase shifter 5 and the received signal output by phase shifter 15 have the same initial phase. When the received signals are combined, they are combined with the same amplitude and phase, so the amplitude of the combined signal is doubled compared to before combining, i.e., the power is increased by 6 dB. Meanwhile, the noise signals N001 to N004 output by phase shifter 5 and the noise signals N001 to N004 output by phase shifter 15 have different initial phases. When the noise signals N001 to N004 are combined, they are not combined with the same phase, so the amplitude of the combined signal is less than doubled compared to before combining, i.e., the power is increased by less than 6 dB. Although not shown in Figure 4, if the initial phases of the noise signals were opposite, they would cancel out when combined. In this case, the received signal in the third Nyquist zone has a power increase of 6 dB at the output of combiner 9, while the power of the noise signals in the other Nyquist zones is increased by less than 6 dB at the output of combiner 9, resulting in a relative noise suppression relative to the received signal. Although not shown in FIG. 2, if there is noise in the same Nyquist zone as the received signal, the power of the noise increases by 6 dB at the output of the combiner 9, and therefore relative suppression cannot be achieved.

As described above, according to embodiment 1, a received signal containing noise or spurious is undersampled using two S/H circuits to which clock signals with the same frequency but different phases are input. Furthermore, the output signals of the two S/H circuits are phase-shifted using phase shifters so that the received signals after undersampling are in phase but the noise or spurious signals after undersampling are not in phase. When the output signals of the two phase shifters are combined, the received signal is combined in phase and the power is significantly increased, but the noise or spurious signals are not combined in phase and the power does not increase as much as the signal. This makes it possible to provide a receiver that can suppress noise or spurious signals in the Nyquist zone where there are no high-frequency band received signals, without the need for an RF band BPF and without increasing size or cost.

In embodiment 1, the phase is shifted after quantization, but quantization may also be performed after phase shifting. Also, while the explanation has been given for a case in which there are two systems consisting of an antenna, S/H circuit, filter, quantizer, phase shifter, signal source, and two phase control circuits, there may be three or more systems as long as the received signals after undersampling in each system are in phase and the noise or spurious signals after undersampling are not in phase.

Here, filters 3 and 13 are used to pass the signal with the lowest frequency component out of the signals output by S/H circuits 2 and 12, but signals with other frequency components may also be passed. As long as the Nyquist zone in which the received signal exists differs from the frequency components passed by filters 3 and 13, signals with frequency components existing outside the first Nyquist zone may also be passed.

Here, we have described the case where digital signals are combined using combiner 9, but analog signals may also be combined. In this case, no quantizer is used, and the filter output signals (analog signals) are combined after being phase-shifted using a phase shifter, and the combined analog signal is output from the receiver. Also, in this embodiment, we have described the case where there is noise in addition to the received signal, but it is also possible that there is spurious signals in addition to noise, or there is no noise and only spurious signals.

In embodiment 1, we described a case where the phases of noise in the four Nyquist zones of the first, second, fourth, and fifth orders are not in phase, but the number of Nyquist zones where the phases are not in phase may be three or less, or five or more.

Embodiment 2.
<Configuration>
In the first embodiment, the amount of suppression of noise or spurious signals outside the Nyquist zone where the received signals are located is small. In the second embodiment, the received signals are in phase and the noise or spurious signals are in opposite phase, thereby canceling out the noise or spurious signals and achieving a large amount of suppression of the noise or spurious signals.

5 is a configuration diagram showing an example of the configuration of a receiver according to a second embodiment of the present disclosure. In FIG. 5, the same reference numerals as in FIG. 1 denote the same or corresponding parts, and their description will be omitted. θ _CLK3 is the initial phase of the third clock signal, θ _CLK4 is the initial phase of the fourth clock signal, θ _out5 is the initial phase of the output signal of filter 23, θ _out6 is the initial phase of the output signal of filter 33, θ _out7 is the initial phase of the output signal of phase shifter 25, θ _out8 is the initial phase of the output signal of phase shifter 35, θ _PS3 is the phase shift amount of phase shifter 25, and θ _PS4 is the phase shift amount of phase shifter 35.

Antenna 21 is an antenna that receives signals propagating through space and outputs the received signals to S/H circuit 22. The output terminal of antenna 21 is connected to the RF terminal of S/H circuit 22. For example, antennas such as dipole antennas and patch antennas can be used for antenna 21. Of course, an array antenna combining multiple element antennas can also be used. Any configuration can be used for antenna 21 as long as it can receive signals propagating through space and output the received signals.

The S/H circuit 22 is a sample-and-hold circuit that synchronizes with the third clock signal output by the signal source 26, undersamples the signal output by the antenna 21, and outputs the undersampled signal to the filter 23. The RF terminal of the S/H circuit 22 is connected to the output terminal of the antenna 21, the clock terminal of the S/H circuit 22 is connected to the output terminal of the signal source 26, and the output terminal of the S/H circuit 22 is connected to the input terminal of the filter 23. For example, the S/H circuit 22 may be a circuit configured with a switch that switches between open and short circuits for the input RF signal (output signal from the antenna 21) and a capacitance that stores charge when the line for the input RF signal is open. Any configuration may be used for the S/H circuit 22 as long as it can undersample the input RF signal and output the undersampled signal. Here, the undersampled signal refers to the signal generated by undersampling.

The filter 23 has a predetermined passband and passes signals output by the S/H circuit 22 that fall within the passband and suppresses signals in frequency bands outside the passband. The filter 23 suppresses signals or unwanted waves that fall outside the passband from the signals output by the S/H circuit 22, and outputs the resulting signal to the quantizer 24. The input terminal of the filter 23 is connected to the output terminal of the S/H circuit 22, and the output terminal of the filter 23 is connected to the input terminal of the quantizer 24. For example, the filter 23 may be an LPF, HPF, or BPF. The filter 23 is implemented using elements such as chip inductors or chip capacitors. Depending on the frequency band to be passed or the required amount of suppression, it may also be configured using other resonators such as microstrip or coaxial resonators. Here, the passband of the filter 23 is a low-frequency band, and even if a BPF is used as the filter 23, it does not require large size or cost, unlike an RF-band BPF.

The quantizer 24 is a circuit that quantizes the input signal and outputs the quantized signal data. It quantizes the signal output by the filter 3 and outputs the quantized signal data to the phase shifter 25. The input terminal of the quantizer 24 is connected to the output terminal of the filter 23, and the output terminal of the quantizer 24 is connected to the input terminal of the phase shifter 25. For example, an ADC can be used for the quantizer 24. Note that when an ADC is used for the quantizer 24, quantization may be performed in synchronization with an externally input clock signal. Any configuration may be used for the quantizer 24 as long as it is able to quantize the input signal and output the quantized signal data.

The phase shifter 25 is a circuit that shifts the phase of an input signal and outputs the phase-shifted signal. Based on a signal indicating θ _PS3 output from the phase control circuit 28, the phase shifter 25 shifts the phase of the signal output by the quantizer 24 and outputs the phase-shifted signal to the combiner 39. The input terminal of the phase shifter 25 is connected to the output terminal of the quantizer 24, the control terminal of the phase shifter 25 is connected to the output terminal of the phase control circuit 28, and the output terminal of the phase shifter 25 is connected to a first input terminal of the combiner 39. For example, an FPGA can be used for the phase shifter 25. In this case, the FPGA shifts the phase of the input signal by changing the initial phase of the NCO in a calculation such as a DDC. Alternatively, the FPGA may convert the input signal into a signal in the complex domain and shift the phase using a complex number calculation. The phase shifter 25 may have any configuration as long as it can shift the phase of an input signal and output a phase-shifted signal.

The signal source 26 is a circuit capable of generating a signal of any signal waveform or any frequency, and generates a third clock signal having a frequency f _CLK and an initial phase θ _CLK3 to be input to the S/H circuit 22 based on a signal indicating θ _CLK3 output from the phase control circuit 27. The control terminal of the signal source 26 is connected to the output terminal of the phase control circuit 27, and the output terminal of the signal source 26 is connected to the clock terminal of the S/H circuit 22. For example, the signal source 26 may be a DAC, a DDS, or a PLL circuit. Although not shown in FIG. 5 , the signal source 26 may generate the third clock signal using an externally input control signal or reference signal. Any configuration may be used for the signal source 26 as long as it can generate a signal of any waveform.

The phase control circuit 27 is a circuit that outputs a signal indicating θ _CLK3 to the signal source 26. The output terminal of the phase control circuit 27 is connected to the control terminal of the signal source 26. For example, an FPGA or a memory can be used for the phase control circuit 27. θ _CLK3 may be determined by calculation, or data stored in advance in a memory or the like may be read out. Any configuration may be used for the phase control circuit 27 as long as it can output a signal indicating θ _CLK3 .

The phase control circuit 28 is a circuit that outputs a signal indicating θ _PS3 to the phase shifter 25. The output terminal of the phase control circuit 28 is connected to the control terminal of the phase shifter 25. For example, an FPGA or a memory can be used for the phase control circuit 28. θ _PS3 may be determined by calculation, or data stored in advance in a memory or the like may be read out. Any configuration may be used for the phase control circuit 28 as long as it can output a signal indicating θ _PS3 .

Antenna 31 is an antenna that receives signals propagating through space and outputs the received signals to S/H circuit 32. The output terminal of antenna 31 is connected to the RF terminal of S/H circuit 32. For example, antennas such as dipole antennas and patch antennas can be used for antenna 31. Of course, an array antenna combining multiple element antennas can also be used. Antenna 31 can have any configuration as long as it can receive signals propagating through space and output the received signals.

S/H circuit 32 is a sample-and-hold circuit that synchronizes with the fourth clock signal output by signal source 36, undersamples the signal output by antenna 31, and outputs the undersampled signal to filter 33. The RF terminal of S/H circuit 32 is connected to the output terminal of antenna 31, the clock terminal of S/H circuit 32 is connected to the output terminal of signal source 36, and the output terminal of S/H circuit 32 is connected to the input terminal of filter 33. For example, S/H circuit 32 may be a circuit configured with a switch that switches between open and short circuits for the input RF signal (output signal from antenna 31) and a capacitance that stores charge when the line is open for the input RF signal. Any configuration may be used for S/H circuit 32 as long as it is able to undersample the input RF signal and output the undersampled signal.

Filter 33 has a predetermined passband and passes signals output by S/H circuit 32 that fall within the passband and suppresses signals in frequency bands outside the passband. Filter 33 suppresses signals or unwanted waves that fall outside the passband from the signals output by S/H circuit 32, and outputs the result to quantizer 34. The input terminal of filter 33 is connected to the output terminal of S/H circuit 32, and the output terminal of filter 33 is connected to the input terminal of quantizer 34. For example, filter 33 may be an LPF, HPF, or BPF. Filter 33 is implemented using elements such as chip inductors or chip capacitors. Depending on the frequency band to be passed or the required amount of suppression, it may also be configured using other resonators such as microstrip or coaxial resonators. Here, the passband of filter 33 is a low-frequency band, and even if a BPF is used as filter 33, it does not require large size or cost, unlike an RF-band BPF.

The quantizer 34 is a circuit that quantizes the input signal and outputs the quantized signal data. It quantizes the signal output by the filter 33 and outputs the quantized signal data to the phase shifter 35. The input terminal of the quantizer 34 is connected to the output terminal of the filter 33, and the output terminal of the quantizer 34 is connected to the input terminal of the phase shifter 35. For example, an ADC can be used for the quantizer 34. Note that when an ADC is used for the quantizer 34, quantization may be performed in synchronization with an externally input clock signal. Any configuration may be used for the quantizer 34 as long as it is able to quantize the input signal and output the quantized signal data.

The phase shifter 35 is a circuit that shifts the phase of an input signal and outputs the phase-shifted signal. Based on a signal indicating θ _PS4 output from the phase control circuit 38, the phase shifter 35 shifts the phase of the signal output by the quantizer 34 and outputs the phase-shifted signal to the combiner 39. The input terminal of the phase shifter 35 is connected to the output terminal of the quantizer 34, the control terminal of the phase shifter 35 is connected to the output terminal of the phase control circuit 38, and the output terminal of the phase shifter 35 is connected to the fourth input terminal of the combiner 39. For example, an FPGA can be used for the phase shifter 35. In this case, the FPGA shifts the phase of the input signal by changing the initial phase of the NCO in a calculation such as a DDC. Alternatively, the FPGA may convert the input signal into a signal in the complex domain and shift the phase using a complex number calculation. The phase shifter 35 may have any configuration as long as it can shift the phase of an input signal and output a phase-shifted signal.

The signal source 36 is a circuit capable of generating a signal of any signal waveform or any frequency, and generates a fourth clock signal having a frequency f _CLK and an initial phase θ _CLK4 to be input to the S/H circuit 32 based on a signal indicating θ _CLK4 output from the phase control circuit 37. The control terminal of the signal source 36 is connected to the output terminal of the phase control circuit 37, and the output terminal of the signal source 36 is connected to the clock terminal of the S/H circuit 32. For example, a DAC, a DDS, or a PLL circuit may be used as the signal source 36. Although not shown in FIG. 5 , the signal source 36 may generate the fourth clock signal using an externally input control signal or reference signal. Any configuration may be used as the signal source 36 as long as it can generate a signal of any waveform.

The phase control circuit 37 is a circuit that outputs a signal indicating θ _CLK4 to the signal source 36. The output terminal of the phase control circuit 37 is connected to the control terminal of the signal source 36. For example, an FPGA or a memory can be used for the phase control circuit 37. θ _CLK4 may be determined by calculation, or data stored in advance in a memory or the like may be read out. Any configuration may be used for the phase control circuit 37 as long as it can output a signal indicating θ _CLK4 .

The phase control circuit 38 is a circuit that outputs a signal indicating θ _PS4 to the phase shifter 35. The output terminal of the phase control circuit 38 is connected to the control terminal of the phase shifter 35. For example, an FPGA or a memory can be used for the phase control circuit 38. θ _PS4 may be calculated by calculation, or data stored in advance in a memory or the like may be read out. Any configuration may be used for the phase control circuit 38 as long as it can output a signal indicating θ _PS4 .

The combiner 39 is a circuit that combines (adds) multiple input signals and outputs the combined signal. It combines the signals output by phase shifter 5, phase shifter 15, phase shifter 25, and phase shifter 35, and outputs the combined signal to the outside. The first input terminal of the combiner 39 is connected to the output terminal of phase shifter 5, the second input terminal of the combiner 39 is connected to the output terminal of phase shifter 15, the third input terminal of the combiner 39 is connected to the output terminal of phase shifter 25, and the fourth input terminal of the combiner 39 is connected to the output terminal of phase shifter 35. For example, an FPGA can be used as the combiner 39. The combiner 39 may have any configuration as long as it can combine (add) multiple input signals and output a combined signal.

<Operation>
Next, the operation of the receiver according to the second embodiment of this disclosure will be described. For simplicity, the received signal input to this receiver is assumed to be 1.1 GHz, with f _CLK =1 GHz, θ _CLK1 =0°, θ _CLK2 =90°, θ _CLK3 =180°, θ _CLK4 =-90°, θ _PS1 =0°, θ _PS2 =90°, θ _PS3 =180°, and θ _PS4 =-90°. Each phase is expressed in the range of -180 to 180°. LPFs with a passband of 0.5 GHz are used as filters 3, 13, 23, and 33; ADCs are used as quantizers 4, 14, 24, and 34; FPGAs are used as phase shifters 5, 15, 25, 35, and combiner 39; FPGAs and memories are used as phase control circuits 7, 8, 17, 18, 27, 28, 37, and 38; and PLL circuits are used as signal sources 6, 16, 26, and 36. The memories may be internal or external to the FPGA. Phase shifters 5, 15, 25, and 35 convert input signals into complex domain signals and shift the phases using complex number operations. The ADCs used as quantizers 4, 14, 24, and 34 are assumed to perform quantization in synchronization with an externally input clock signal and to be oversampling. Furthermore, it is assumed that there are no spurious signals propagating through space, and that the received signal and noise arrive from the front direction relative to the receiver (the antenna plane formed by antennas 1, 11, 21, and 31). Furthermore, it is assumed that the initial phase of all received signals and noise is 0°. The frequency spectrum of the output signals from antennas 1, 11, 21, and 31 is the same as that shown in FIG. 2. Note that a description of components that operate in the same manner as the receiver according to embodiment 1 will be omitted here.

First, in this receiver, antennas 21 and 31 receive a 1.1 GHz signal and noise propagating through space and output the received signal and noise to S/H circuits 22 and 32. Signal source 26 generates a third clock signal with a frequency of 1 GHz and an initial phase θ _CLK3 and outputs the generated third clock signal to S/H circuit 22. Signal source 36 generates a fourth clock signal with a frequency of 1 GHz and an initial phase θ _CLK4 and outputs the generated fourth clock signal to S/H circuit 32. S/H circuit 22 undersamples the received signal and noise output by antenna 21 in synchronization with the third clock signal. S/H circuit 32 undersamples the received signal and noise output by antenna 31 in synchronization with the fourth clock signal.

S/H circuit 22 undersamples the signal output by antenna 21 using the third clock signal output by signal source 26. S/H circuit 32 undersamples the signal output by antenna 31 using the fourth clock signal output by signal source 36. Due to undersampling, the output spectra of S/H circuit 22 and S/H circuit 32 produce aliasing components at each Nyquist frequency (0.5 GHz). The output signal of S/H circuit 22 has multiple frequency components. Because the frequency of the clock signal input to S/H circuit 2, S/H circuit 12, S/H circuit 22, and S/H circuit 32 is the same, the frequency of the output signal of S/H circuit 22 or S/H circuit 32 is the same as equation (1). The frequencies of the received signal and noise N001 to N004 were explained in embodiment 1 and are therefore omitted here.

Phase control circuit 27 outputs data indicating θ _CLK3 to signal source 26. Phase control circuit 37 outputs data indicating θ _CLK4 to signal source 36. Although not shown in Fig. 5, θ _CLK3 and θ _CLK4 may be calculated by phase control circuit 27 and phase control circuit 37, or the results of calculations performed outside the receiver may be input to and stored in phase control circuit 27 and phase control circuit 37.

Since the clock signals input to S/H circuits 22 and 32 have the same frequency but different phases (θ _CLK3 ≠ θ _CLK4 ), the output signals of S/H circuits 22 and 32 have different phases. That is, the output signals of filters 23 and 33 have the same frequency but different phases. If the initial phases of the output signals of S/H circuits 22 and 32 are θ _S/H22 and θ S _/H32 , respectively, then θ _S/H22 and θ _S/H32 are expressed by the following equations (31) and (32), respectively.

However, filters 23 and 33 pass the components within the first Nyquist zone among the many frequency components contained in the output signals of S/H circuits 22 and 32. The frequency spectrum of the output signals of filters 23 and 33 is the same as that shown in Figure 3, so a description of it will be omitted here.

Because noise N001 is in the first Nyquist zone, the frequency does not change between the output of antenna 21 and the outputs of filter 23 and filter 33. That is, according to equation (1), α = 1 and k = 0. If the initial phase of noise N001 in the output of filter 23 is θ _{out5_N001} and the initial phase of noise N001 in the output of filter 33 is θ _{out6_N001} , then according to equations (31) and (32), α = 1 and k = 0, and therefore θ _{out5_N001} and θ _{out6_N001} are expressed by the following equations (33) and (34), respectively.

For the noise N002, from equation (6), α = -1 and k = -1. If the initial phase of the noise N002 in the output of the filter 23 is θ _{out5_N002} and the initial phase of the noise N002 in the output of the filter 33 is θ _{out6_N002} , then θ _{out5_N002} and θ _{out6_N002} are expressed by the following equations (35) and (36), respectively.

For the received signal, from equation (9), α = +1 and k = -1. If the initial phase of the received signal at the output of filter 23 is θ _{out5_S} and the initial phase of the received signal at the output of filter 33 is θ _{out6_S} , then θ _{out5_S} and θ _{out6_S} are expressed by the following equations (37) and (38), respectively.

For noise N003, α = -1 and k = -2 according to equation (12). If the initial phase of noise N003 in the output of filter 23 is θ _{out5_N003} and the initial phase of noise N003 in the output of filter 33 is θ _{out6_N003} , then θ _{out5_N003} and θ _{out6_N003} are expressed by the following equations (39) and (40), respectively.

For noise N004, α = +1 and k = -2 according to equation (12). If the initial phase of noise N004 in the output of filter 23 is θ _{OUT5_N004} and the initial phase of noise N004 in the output of filter 33 is θ _{OUT6_N004} , then θ _{OUT5_N004} and θ _{OUT6_N004} are expressed by equations (41) and (42), respectively.

Filters 23 and 33 are provided to prevent malfunctions caused by the input of a large number of frequency components to quantizers 24 and 34, or failures caused by the input of high-power frequency components. Because the output signals of S/H circuits 22 and 32 contain frequency components in the second or higher Nyquist zone, the filter passband or implementation method is determined so that the components in the second or higher Nyquist zone can be sufficiently suppressed. Furthermore, if the frequency components in the second or higher Nyquist zone contained in the output signals of S/H circuits 22 and 32 are outside the operable frequencies of quantizers 24 and 34, or if the power of these frequency components is low, and no malfunction or failure occurs in quantizers 24 and 34, filters 23 and 33 may be omitted and replaced with through circuits.

Quantizer 24 and quantizer 34 quantize the analog signals output by filter 23 and filter 33, respectively, and output the quantized signal data as digital signals to phase shifter 25 and phase shifter 35, respectively. Phase shifter 25 converts the signal data output by quantizer 24 into a complex domain signal and shifts the initial phase of the signal by θ _PS3 using complex number calculations. Phase shifter 35 converts the signal data output by quantizer 34 into a complex domain signal and shifts the initial phase of the signal by θ _PS4 using complex number calculations.

Phase control circuit 28 outputs data indicating θ _PS3 to phase shifter 25. Phase control circuit 38 outputs data indicating θ _PS4 to phase shifter 35. Although not shown in Fig. 5, θ _PS3 and θ _PS4 may be calculated by phase control circuits 28 and 38, or the results of calculations performed outside the receiver may be input to and stored in phase control circuits 28 and 38.

In this case, θ _out7 and θ _out8 are expressed by the following equations (43) and (44), respectively.

Here, if the initial phase of the noise N001 in the output of the phase shifter 25 is θ _{out7 — N001} and the initial phase of the noise N001 in the output of the phase shifter 35 is θ _{out8 — N001} , then θ _{out7 — N001} and θ _{out8 — N001} are respectively expressed by the following equations (45) and (46).

If the initial phase of the noise N002 in the output of the phase shifter 25 is θ _{out7 — N002} and the initial phase of the noise N002 in the output of the phase shifter 35 is θ _{out8 — N002} , then θ _{out7 —} N002 and θ _{out8 — N002} are expressed by the following equations (47) and (48), respectively.

If the initial phase of the received signal at the output of phase shifter 25 is θ _{out7_S} and the initial phase of the received signal at the output of phase shifter 35 is θ _{out8_S} , then θ _{out7_S} and θ _{out8_S} are expressed by the following equations (49) and (50), respectively.

If the initial phase of the noise N003 in the output of the phase shifter 25 is θ _{out7 — N003} and the initial phase of the noise N003 in the output of the phase shifter 35 is θ _{out8 — N003} , then θ _{out7 —} N003 and θ _{out8 — N003} are respectively expressed by the following equations (51) and (52).

If the initial phase of the noise N004 in the output of the phase shifter 25 is θ _{out7 — N004} and the initial phase of the noise N004 in the output of the phase shifter 35 is θ _{out8 — N004} , then θ _{out7 —} N004 and θ _{out8 — N004} are expressed by the following equations (53) and (54), respectively.

6 is a table showing the initial phases of the received signal and noise N001 to 004 at the outputs of phase shifter 5, phase shifter 15, phase shifter 25, and phase shifter 35. If the passing phase of the received signal and noise in the mth (m is an integer of 1 or more) Nyquist zone is θ _{m_i} , then θ _{m_i} can be expressed by the following equation (55).

where i = 1, 2, 3, or 4. The passing phase indicates the amount by which the received signal and noise are phase-shifted from the output terminal of each of antenna 1, antenna 11, antenna 21, or antenna 31 to the output terminal of each of phase shifters 5, 15, 25, or 35. Combiner 39 combines (adds) the signals and noise output by phase shifters 5, 15, 25, and 35, and outputs the combined signal to the outside of the receiver. Here, when the received signals in the third Nyquist zone output by phase shifters 5, 15, 25, and 35 are combined in phase, the following equation (56) holds true from equation (55) and m = 3.

where n = 1, 2, or 3. When the noises output from phase shifter 5, phase shifter 15, phase shifter 25, and phase shifter 35 that are in the first, second, fourth, or fifth Nyquist zone are combined in antiphase, the following equation (57) holds true from equation (55).

where l = 1, 2, 4, or 5, and t is a positive integer. Figure 7 is a table in which values are substituted for the initial phases of the received signal and noise N001 to N004 shown in Figure 6. Here, θ _CLK1 = 0°, θ _CLK2 = 90°, θ _CLK3 = 180°, θ _CLK4 = -90°, θ _PS1 = 0°, θ _PS2 = 90°, θ _PS3 = 180°, and θ _PS4 = -90°, and 0° is substituted as the initial phase for all received signals and noise. As can be seen from Figure 7, the received signals output by phase shifter 5, phase shifter 15, phase shifter 25, and phase shifter 35 all have the same initial phase. When the received signals are combined, they are combined with the same amplitude and phase, so the combined signal has four times the amplitude, i.e., a 12 dB increase in power, compared to before combination. On the other hand, the noises N001 to N004 output by phase shifter 5, phase shifter 15, phase shifter 25, and phase shifter 35 are in opposite phases (for example, the noise N001 output by phase shifter 5 and the noise N001 output by phase shifter 25 are in opposite phases, and the noise N001 output by phase shifter 15 and the noise N001 output by phase shifter 35 are in opposite phases). Therefore, when noises N001 to N004 are combined, they are canceled out in opposite phases. The received signal in the third Nyquist zone has its power increased by 12 dB at the output of combiner 39, but the noise in the other Nyquist zones is canceled out and disappears, so theoretically, an infinite amount of suppression can be achieved. Note that, although not shown in FIG. 2, if there is noise in the same Nyquist zone as the received signal, the power of that noise will increase by 12 dB at the output of combiner 39, and therefore relative suppression cannot be achieved.

As described above, according to embodiment 2, the same effect as the receiver of embodiment 1 can be obtained. In addition, by canceling out the received signals by making them in phase and the noise or spurious signals out of phase, a greater amount of suppression can be obtained than in embodiment 1.

In the second embodiment, the phase is shifted after quantization, but quantization may also be performed after phase shifting. Also, while the description has been given of a case in which there are four systems consisting of an antenna, S/H circuit, filter, quantizer, phase shifter, signal source, and two phase control circuits, the number of systems may be less than four or five or more, as long as the received signals after undersampling in each system are in phase and the noise or spurious signals after undersampling are in opposite phase.

Here, we have described a case where the received signals are in phase and the noise or spurious signals are in anti-phase relationship, but the received signals do not have to be in anti-phase relationship, and the noise or spurious signals may be in anti-phase relationship.

Here, filters 3, 13, 23, and 33 are used to pass the signal with the lowest frequency component out of the signals output by S/H circuit 2, S/H circuit 12, S/H circuit 22, and S/H circuit 32, but signals with other frequency components may also be passed. As long as the Nyquist zone in which the received signal exists differs from the frequency components passed by filters 3, 13, 23, and 33, signals with frequency components existing outside the first Nyquist zone may also be passed.

Here, we have described the case where digital signals are combined using combiner 39, but analog signals may also be combined. In this case, no quantizer is used, and the filter output signals (analog signals) are combined after being phase-shifted using a phase shifter, and the combined analog signal is output externally to the receiver. Also, in this embodiment, we have described the case where there is noise in addition to the received signal, but it is also possible that there is spurious signals in addition to noise, or there is no noise and only spurious signals.

In the second embodiment, we have described a case where noise in the four Nyquist zones of the first, second, fourth, and fifth orders is out of phase, but the number of Nyquist zones in which noise is out of phase may be three or less, or five or more.

It is possible to combine embodiments, and to modify or omit each embodiment as appropriate.

The receiver disclosed herein can be used as a device for receiving radio waves.

1. Antenna, 2. S/H circuit, 3. Filter, 4. Quantizer, 5. Phase shifter, 6. Signal source, 7. Phase control circuit, 8. Phase control circuit, 9. Combiner, 11. Antenna, 12. S/H circuit, 13. Filter, 14. Quantizer, 15. Phase shifter, 16. Signal source, 17. Phase control circuit, 18. Phase control circuit, 21. Antenna, 22. S/H circuit, 23. Filter, 24. Quantizer, 25. Phase shifter, 26. Signal source, 27. Phase control circuit, 28. Phase control circuit, 31. Antenna, 32. S/H circuit, 33. Filter, 34. Quantizer, 35. Phase shifter, 36. Signal source, 37. Phase control circuit, 38. Phase control circuit, 39. Combiner.

Claims (4)

a first signal source that outputs a first clock signal having a first frequency and a first phase;
second to M-th signal sources outputting second to M-th (M-1) clock signals, where M is an integer equal to or greater than 2, each clock signal having the first frequency and an M-th phase different from the first phase;
M sample-and-hold circuits (first to Mth) that undersample the received signal using the M clock signals (first to Mth), respectively;
first to M-th phase shifters for shifting the phases of output signals from the first to M-th sample-and-hold circuits, respectively;
a combiner that combines output signals from the first to M phase shifters,
In the outputs of the first to M phase shifters, components in the Nth (N is an integer of 1 or more) Nyquist zone are in phase with each other, and components in one or more Nyquist zones other than the Nth Nyquist zone are not in phase with each other. The receiver described in claim 1, characterized in that, in the outputs of the first to M phase shifters, the components of the Nth Nyquist zone are not out of phase with each other, and the components of one or more Nyquist zones other than the Nth Nyquist zone are out of phase with each other. The receiver described in either claim 1 or 2, characterized in that the components of the Nth Nyquist zone are in phase with each other in the outputs of the first to Mth phase shifters. When the first phase of the first clock signal is θ _CLK1 , the Mth phase of the Mth clock signal is θ _CLKM , the phase shift amount of the first phase shifter is θ _PS1 , and the phase shift amount of the Mth phase shifter is θ _PSM , the passing phase θ _{m_M} of the component in the mth (m is an integer of 1 or more) Nyquist zone can be expressed by the following equation:


And, l is an integer from 1 to M other than N, t is an integer, i=1,...,M, and the following two formulas are satisfied:

θ _{N_1} =・・・=θ _{N_M}


4. The receiver according to claim 1, wherein the following holds true: