WO2025261062A1 - Display substrate and display apparatus - Google Patents

Abstract

A display substrate and a display apparatus. The display substrate includes first sub-pixels (110), second sub-pixels (120), and third sub-pixels (130). The display substrate includes a plurality of sub-pixel groups (10). Each sub-pixel group (10) includes at least two first sub-pixels (110), at least two second sub-pixels (120), and at least two third sub-pixels (130), wherein the third sub-pixels (130) are arranged in a first direction, and light-emitting regions of the at least two third sub-pixels (130) are configured to correspond to the same mask opening; in the sub-pixel group (10), the included angle between two sides or the included angle between extension lines of the two sides connected by at least one contour corner of light-emitting regions of two third sub-pixels (130) located at the outermost edge in the first direction is 100-170 degrees; and adjacent sub-pixel groups (10) arranged in the first direction include a first sub-pixel group (11) and a second sub-pixel group (12), and third sub-pixels (130) in the first sub-pixel group (11) and third sub-pixels (130) in the second sub-pixel group (12) are staggered in a second direction. Thus, the difficulty of a mask manufacturing process is reduced while increasing a pixel aperture ratio.

Description

Display substrate and display device

This application claims priority to Chinese Patent Application No. 202410813636.1, filed on June 21, 2024, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

This disclosure relates to a display substrate and a display device.

Background Technology

The advent of cathode ray tubes ushered in the field of flat panel displays in the last century. With the development of technology, various displays have come into view, such as liquid crystal displays (LCDs), field emission displays (FEDs), plasma displays, electroluminescent displays (ELs), and organic light-emitting diode displays.

Organic light-emitting diodes (OLEDs) are self-emissive devices. Unlike traditional light-emitting devices, they do not require a backlight. OLEDs are injection-type light-emitting devices, and their basic structure consists of an organic thin film layer sandwiched between two electrodes (at least one of which is transparent) to form a sandwich structure. Due to their self-emissive nature, OLED displays offer faster response times, superior color purity and brightness, higher contrast, and wider viewing angles.

Summary of the Invention

This disclosure provides a display substrate and a display device.

This disclosure provides a display substrate, including a substrate and a plurality of sub-pixels located on the substrate. The plurality of sub-pixels includes a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels, wherein the area of the light-emitting region of each first sub-pixel and the area of the light-emitting region of each second sub-pixel are not greater than the area of the light-emitting region of each third sub-pixel. The plurality of sub-pixels includes a plurality of sub-pixel groups, each sub-pixel group including at least two first sub-pixels, at least two second sub-pixels, and at least two third sub-pixels. The at least two third sub-pixels are arranged along a first direction, and the light-emitting areas of the at least two third sub-pixels are configured to correspond to the same mask opening. In at least one sub-pixel group, the included angle between the two sides connected by at least one contour angle of the light-emitting areas of the two outermost third sub-pixels located in the first direction, or the included angle between the extensions of the two sides, is 100 to 170 degrees. At least two adjacent sub-pixel groups arranged in the first direction include a first sub-pixel group and a second sub-pixel group. The third sub-pixels in the first sub-pixel group and the third sub-pixels in the second sub-pixel group are staggered in a second direction, and the second direction intersects the first direction.

For example, according to an embodiment of this disclosure, the plurality of sub-pixel groups are arranged in an array along the first direction and the second direction, and in each sub-pixel group, the number of the first sub-pixel, the number of the second sub-pixel, and the number of the third sub-pixel are all equal; in the same sub-pixel group, the first sub-pixel and the second sub-pixel are arranged along the first direction, and the first sub-pixel and the third sub-pixel are arranged along the second direction; the third sub-pixel in the first sub-pixel group and the first sub-pixel in the second sub-pixel group are arranged along the first direction.

For example, according to an embodiment of this disclosure, the distance between the light-emitting areas of the two closest third sub-pixels located in the first sub-pixel group and the second sub-pixel group is a first distance, and the distance between the light-emitting areas of the first sub-pixel and the second sub-pixel located in the first sub-pixel group and the second sub-pixel group is a second distance, wherein the first distance is not less than the second distance.

For example, according to an embodiment of this disclosure, the included angle between two sides or the included angle between the extensions of at least one of the contour angles of the two closest third sub-pixels located in the first sub-pixel group and the second sub-pixel group respectively is 100 to 170 degrees.

For example, according to an embodiment of this disclosure, the display substrate further includes: a plurality of gate lines, wherein the angle between the extension direction of at least one gate line and the first direction is not greater than 3 degrees.

For example, according to an embodiment of this disclosure, the display substrate further includes: a plurality of gate lines, wherein the extension direction of at least one gate line forms an angle of 30 to 60 degrees with the first direction.

For example, according to an embodiment of this disclosure, the size of the light-emitting area of the first sub-pixel and the light-emitting area of the second sub-pixel in the first direction is smaller than the size of the light-emitting area of the third sub-pixel in the first direction; the first sub-pixel and the third sub-pixel are arranged alternately along the second direction.

For example, according to an embodiment of this disclosure, the light-emitting areas of sub-pixels in two adjacent sub-pixel groups arranged along the second direction are symmetrically distributed with respect to a first dividing line located between the two adjacent sub-pixel groups and extending along the first direction, and at least four third sub-pixels in two adjacent sub-pixel groups arranged along the second direction that are located on both sides of the first dividing line and are adjacent to it are configured to correspond to the same mask opening.

For example, according to an embodiment of this disclosure, the same sub-pixel group includes N third sub-pixels, and the N/2th third sub-pixel arranged along the first direction and the (N/2+1)th third sub-pixel are separated by a second dividing line extending along the second direction, where N is an even number; in the same sub-pixel group, the light-emitting areas of the sub-pixels are symmetrically distributed with respect to the second dividing line.

For example, according to an embodiment of this disclosure, the light-emitting area of the third sub-pixel includes at least one first side extending along the first direction, and the extension directions of the sides adjacent to the first side in both the light-emitting areas of the first sub-pixel and the light-emitting areas of the second sub-pixel intersect with the first direction.

For example, according to an embodiment of this disclosure, the light-emitting area of the third sub-pixel includes at least one first side extending along the first direction, and in the same sub-pixel group, the distance between the first side of the light-emitting area of at least two adjacent third sub-pixels and the center line extending along the first direction in the light-emitting area of the first sub-pixel is different.

For example, according to an embodiment of this disclosure, in the same sub-pixel group, the extension directions of the edges adjacent to the first edge in the light-emitting areas of the first sub-pixel and the light-emitting areas of the second sub-pixel both intersect with the extension direction of the first edge.

For example, according to an embodiment of this disclosure, in the same sub-pixel group, the first side of one of the at least two adjacent third sub-pixels is close to the first sub-pixel and the second sub-pixel in its sub-pixel group, and the first side of the other of the at least two adjacent third sub-pixels is far away from the first sub-pixel and the second sub-pixel in its sub-pixel group.

For example, according to an embodiment of this disclosure, the light-emitting area of the third sub-pixel further includes a second side and a third side connected to each other, the angle between the second side and the side of the light-emitting area of the first sub-pixel adjacent to it is no greater than 5 degrees, the angle between the third side and the side of the light-emitting area of the second sub-pixel adjacent to it is no greater than 5 degrees, and the first side and the second side are located on both sides of the center of the light-emitting area of the third sub-pixel in the second direction.

For example, according to an embodiment of this disclosure, at least some sub-pixels include a light-emitting functional layer, a first electrode, a second electrode, and a pixel circuit. The first electrode is located between the light-emitting functional layer and the substrate and is electrically connected to the pixel circuit. The second electrode is located on the side of the light-emitting functional layer away from the first electrode. In two adjacent sub-pixel groups arranged along the second direction, the first electrode of the third sub-pixel is symmetrically distributed with respect to the first dividing line.

For example, according to an embodiment of this disclosure, in two adjacent sub-pixel groups arranged along the second direction, the first electrode of at least one of the first sub-pixel and the second sub-pixel is symmetrically distributed with respect to the first dividing line.

For example, according to an embodiment of this disclosure, the first electrode includes a main electrode and a connecting electrode connected to each other. Along a direction perpendicular to the substrate, the connecting electrode does not overlap with the light-emitting area of the sub-pixel. In the same sub-pixel group, the connecting electrode of the third sub-pixel is located between its main electrode and the main electrode of the second sub-pixel, the connecting electrode of the second sub-pixel is located between its main electrode and the main electrode of the first sub-pixel, and the connecting electrode of the first sub-pixel is located between its main electrode and the main electrode of the third sub-pixel.

For example, according to embodiments of this disclosure, in the same sub-pixel group, at least two first sub-pixels and at least two second sub-pixels correspond to the same mask opening.

For example, according to an embodiment of this disclosure, in two adjacent sub-pixel groups arranged along the second direction, at least two first sub-pixels located on both sides of the first dividing line and adjacent to it are configured to correspond to the same mask opening, and at least two second sub-pixels located on both sides of the first dividing line and adjacent to it are configured to correspond to the same mask opening.

Another embodiment of this disclosure provides a display device including any of the above-described display substrates.

Attached Figure Description

To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

Figure 1 is a schematic diagram of a pixel arrangement structure and its metal mask opening.

Figure 2 is a schematic diagram of a partial pixel arrangement structure in a display substrate provided according to an example of an embodiment of the present disclosure.

Figure 3 is a schematic diagram of the mask used to form the pixel arrangement structure shown in Figure 2.

Figure 4 is a schematic diagram of the light-emitting area of the third sub-pixel in another example of the display substrate shown in Figure 2.

Figures 5 to 7 show pixel arrangement structures provided according to different examples of embodiments of the present disclosure.

Figure 8 shows a pixel arrangement structure provided according to another example of an embodiment of the present disclosure.

Figure 9 is a schematic diagram of a mask template for forming the pixel arrangement structure shown in Figure 8.

Figure 10 is a schematic diagram of another mask template for forming the pixel arrangement structure shown in Figure 8.

Figure 11 shows a pixel arrangement structure provided according to another example of an embodiment of the present disclosure.

Figure 12 is a schematic diagram of a mask template for forming the pixel arrangement structure shown in Figure 11.

Figure 13 is a schematic diagram of another mask template for forming the pixel arrangement structure shown in Figure 11.

Figure 14 shows a pixel arrangement structure provided according to another example of an embodiment of the present disclosure.

Figure 15 is a schematic diagram of a mask template for forming the pixel arrangement structure shown in Figure 14.

Figure 16 is a schematic diagram of the equivalent circuit of a pixel circuit.

Figures 17A to 17F are schematic diagrams of different film layers in a display substrate.

Figure 17G is a structural diagram of the stacked first electrode layer and the fourth conductive pattern layer.

Figure 18 is a schematic diagram of a partial cross-sectional structure of a display substrate provided according to an embodiment of the present disclosure.

Figures 19A and 19B are schematic diagrams of a fourth conductive pattern layer and a first electrode layer provided according to an example of an embodiment of the present disclosure.

Figure 19C is a stack-up diagram of the fourth conductive pattern layer and the first electrode layer shown in Figures 19A and 19B.

Figures 20A and 20B are schematic diagrams of a fourth conductive pattern layer and a first electrode layer provided according to an example of an embodiment of the present disclosure.

Figure 20C is a stack-up diagram of the fourth conductive pattern layer and the first electrode layer shown in Figures 20A and 20B.

Figures 21A and 21B are schematic diagrams of partial layer structures of a display substrate provided according to another example of an embodiment of the present disclosure.

Figure 22 is a schematic block diagram of a display device provided according to another embodiment of the present disclosure.

Detailed Implementation

To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

The features such as "parallel," "perpendicular," and "identical" used in the embodiments of this disclosure include features in the strict sense of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include a certain degree of error. Taking into account measurement and errors associated with the measurement of a specific quantity (e.g., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of said value. Unless otherwise specified in the following embodiments of this disclosure, the quantity of a component is implied to mean that the component can be one or more, or can be understood as at least one. "At least one" means one or more, and "more" means at least two.

The light-emitting mechanism of organic light-emitting diode (OLED) devices can be divided into five steps. The first step is carrier injection: under the action of an electric field, electrons and holes are injected from the cathode and anode into the light-emitting functional layer sandwiched between the two electrodes, respectively. The second step is carrier transport: the injected electrons and holes are injected from the electron transport layer and hole transport layer into the light-emitting layer, respectively. The third step is carrier recombination: electron-hole recombination generates excitons. The fourth step is exciton migration: excitons migrate under the action of an electric field, transfer energy to the light-emitting layer, and excite electrons to transition from the ground state to the excited state. The fifth step is electroluminescence: the energy of the excited state transitions through radiation, generating photons and releasing energy.

Organic light-emitting diodes (OLEDs), such as subpixels in display devices, are formed by depositing organic materials onto an array substrate. The organic material is deposited onto the anode within an opening in the pixel limiting layer (PDL) on the array substrate. The opening in the PDL defines the actual light-emitting area of the subpixel. For RGB pixel structures, such as Strip RGB pixel structures, where red and green subpixels are arranged in one column and blue subpixels in another, the PDL gap is typically reduced to increase the pixel opening area to improve the lifespan of blue subpixels, given their larger light-emitting area. However, if the PDL gap is too small, it can cause color mixing and other defects, resulting in yield loss. For high-resolution products, reducing the PDL gap and the size of the PDL openings increases the difficulty of fabricating the fine metal mask (FMM). Therefore, adjusting the pixel arrangement can improve the aperture ratio.

In their research, the inventors of this application discovered that fabricating an organic light-emitting diode (OLED) display substrate involves fabricating sub-pixels arranged in a matrix on a substrate. These matrix-arranged sub-pixels form a pixel arrangement, such as a pixel arrangement comprising multiple pixel units, each pixel unit including three sub-pixels, such as a blue sub-pixel, a green sub-pixel, and a red sub-pixel. Each blue sub-pixel is fabricated using an opening in a photomask, such as a 1-in-1 arrangement. The area of the light-emitting region of the blue sub-pixel is larger than the areas of the light-emitting regions of the red and green sub-pixels, and the red and green sub-pixels are on the same side, while the blue sub-pixel occupies a separate side. This pixel arrangement has a very low lifetime and aperture ratio, making it difficult to meet the current development trend of the display industry, which demands increasingly higher display resolutions.

Figure 1 is a schematic diagram of a pixel arrangement structure and its metal mask opening.

As shown in Figure 1, the pixel arrangement structure includes a pixel-limited opening 001 corresponding to a red subpixel, a pixel-limited opening 002 corresponding to a green subpixel, and a pixel-limited opening 003 corresponding to a blue subpixel. The emitting area of one red subpixel corresponds to one mask opening 004, the emitting area of one green subpixel corresponds to one mask opening 005, and the emitting area of one blue subpixel corresponds to one mask opening 006. The distances PG1 between pixel-limited openings 001 and 002, PG2 between pixel-limited openings 001 and 003, and PG3 between pixel-limited openings 002 and 003 are approximately equal and can all be referred to as the pixel gap (PDL Gap). The larger the pixel-limited opening, the smaller the pixel gap, and the higher the risk of color mixing.

As shown in Figure 1, the minimum distance Rib1 between adjacent mask openings 006 is limited by the size of the mask strip, which is constrained by the mask manufacturing process and cannot be too small; it is generally greater than 25 micrometers. Therefore, Rib1 limits the size of the mask openings. The pixel arrangement structure shown in Figure 1, due to the limitations of the mask opening size and mask strip size, struggles to meet the high resolution and long lifespan requirements of display devices.

A pixel arrangement that forms the light-emitting areas of two sub-pixels by using the same opening of a photomask, such as forming the light-emitting areas of two blue sub-pixels, such as using a 2B in 1 pixel arrangement, is beneficial to increasing the area of the pixel-defined opening to improve the lifespan of the display substrate.

For example, in the pixel arrangement structure of the display substrate shown in Figure 1, after setting the blue sub-pixels to a 2-in-1 pixel arrangement, the PDL Gap is 20 micrometers, the pixel pitch is 100 micrometers, the Rib1 is 25 micrometers, and the aperture ratio of the red, green, and blue sub-pixels is 1:1.7:2.15. The aperture ratio of the red sub-pixels is 8.04%, the aperture ratio of the green sub-pixels is 13.66%, the aperture ratio of the blue sub-pixels is 17.28%, and the total aperture ratio is 38.98%. The above aperture ratio refers to the ratio of the area of the light-emitting area (such as the effective light-emitting area defined by the pixel-defined aperture) to the area of the display area.

This disclosure provides a display substrate and a display device. The display substrate includes a substrate and a plurality of sub-pixels located on the substrate. The plurality of sub-pixels includes a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels, wherein the area of the light-emitting region of each first sub-pixel and the area of the light-emitting region of each second sub-pixel are not greater than the area of the light-emitting region of each third sub-pixel. The plurality of sub-pixels includes a plurality of sub-pixel groups, each sub-pixel group including at least two first sub-pixels, at least two second sub-pixels, and at least two third sub-pixels, wherein the at least two third sub-pixels are arranged along a first direction and the light-emitting regions of the at least two third sub-pixels are configured to correspond to the same mask opening; in at least one sub-pixel group, the included angle between the two sides connecting at least one contour angle of the light-emitting regions of the two outermost third sub-pixels located in the first direction, or the included angle between the extensions of the two sides, is 100 to 170 degrees; at least two adjacent sub-pixel groups arranged in the first direction include a first sub-pixel group and a second sub-pixel group, wherein the third sub-pixels in the first sub-pixel group and the third sub-pixels in the second sub-pixel group are staggered in a second direction, and the second direction intersects the first direction.

By setting the light-emitting areas of at least two third sub-pixels to correspond to the same mask opening so that the at least two third sub-pixels form a light-emitting layer from the same mask opening, while the third sub-pixels in different sub-pixel groups are staggered and the contour angle of the light-emitting area of the third sub-pixels is set, the mask opening size is increased to increase the pixel aperture ratio, while the mask strip width of the mask is not reduced, thus reducing the manufacturing difficulty of the mask, reducing the risk of color mixing, and improving the image quality. This can meet the requirements of high resolution and long lifespan.

The display substrate and display device provided in the embodiments of this disclosure are described below with reference to the accompanying drawings.

Figure 2 is a schematic diagram of a partial pixel arrangement structure in a display substrate according to an example embodiment of the present disclosure. Figure 3 is a schematic diagram of a mask forming the pixel arrangement structure shown in Figure 2.

As shown in Figure 2, the display substrate includes a substrate 01 and a plurality of sub-pixels 100 located on the substrate 01. The plurality of sub-pixels 100 includes a plurality of first sub-pixels 110, a plurality of second sub-pixels 120, and a plurality of third sub-pixels 130. The area of the light-emitting region of each first sub-pixel 110 and the area of the light-emitting region of each second sub-pixel 120 are not greater than the area of the light-emitting region of each third sub-pixel 130. For example, the first sub-pixels 110, second sub-pixels 120, and third sub-pixels 130 may be sub-pixels 100 that emit different colors of light. For example, the third sub-pixel 130 may be a blue sub-pixel that emits blue light, one of the first sub-pixels 110 and second sub-pixels 120 may be a red sub-pixel that emits red light, and the other of the first sub-pixels 110 and second sub-pixels 120 may be a green sub-pixel that emits green light. The areas of the light-emitting regions of the red and green sub-pixels are both smaller than the area of the light-emitting region of the blue sub-pixel. For example, the first sub-pixel 110 may be a red sub-pixel, and the second sub-pixel 120 may be a green sub-pixel. However, this is not the only limitation; the colors of the first sub-pixel 110 and the second sub-pixel 120 can be interchanged. The aforementioned light-emitting area can be a region defined by an opening in a pixel-defining layer (PDL as shown in Figure 18), in which a light-emitting layer is formed, and electrodes located on both sides of the light-emitting layer drive the portion of the light-emitting layer located within the light-emitting area to emit light.

As shown in Figures 2 and 3, the plurality of sub-pixels 100 includes a plurality of sub-pixel groups 10, such as the plurality of sub-pixels 100 arranged in an array of sub-pixel groups 10. Each sub-pixel group 10 includes at least two first sub-pixels 110, at least two second sub-pixels 120, and at least two third sub-pixels 130, the at least two third sub-pixels 130 being arranged along a first direction and the light-emitting areas of the at least two third sub-pixels 130 being configured to correspond to the same mask opening. For example, the first direction can be the X direction shown in the figures.

For example, as shown in Figures 2 and 3, in the same sub-pixel group 10, multiple third sub-pixels 130 arranged along the first direction form a light-emitting layer using the same mask opening 530. Figures 2 and 3 schematically show that the same sub-pixel group 10 includes two third sub-pixels 130 arranged along the first direction, such as the two third sub-pixels 130 forming a light-emitting layer using the same mask opening 530, such as forming the light-emitting layer of the blue sub-pixel 100 using a 2-bin-1 method, but it is not limited to this. The same sub-pixel group 10 may also include three third sub-pixels 130, four third sub-pixels 130, or more third sub-pixels 130 arranged along the first direction.

By setting the light-emitting areas of at least two third sub-pixels to correspond to the same mask opening, so that the at least two third sub-pixels form a light-emitting layer by the same mask opening, it is beneficial to increase the mask opening size to increase the pixel aperture ratio, thereby meeting the requirements of higher pixel density, such as higher pixels per inch (PPI), high resolution, and long lifespan.

For example, as shown in Figures 2 and 3, in the same sub-pixel group 10, each first sub-pixel 110 uses a mask opening 510 to form a light-emitting layer, and each second sub-pixel 120 uses a mask opening 520 to form a light-emitting layer.

As shown in Figure 2, in at least one sub-pixel group 10, the included angle α between the two sides connecting the at least two outermost contour angles of the light-emitting areas of the two outermost third sub-pixels 130 in the first direction, or the included angle α between the extensions of the two sides, is 100 to 170 degrees. For example, the aforementioned contour angle can be referred to as a chamfer, such as a straight chamfer or a rounded chamfer.

For example, as shown in Figure 2, when the above-mentioned contour angle is a straight chamfer, the contour angle is formed by two straight sides, and the size of the contour angle is the included angle α between the two straight sides. For example, it can be 120 to 150 degrees, or 110 to 140 degrees, or 130 to 160 degrees, or 132 to 137 degrees, or 135 degrees. The embodiments disclosed herein will not be listed one by one. The included angle α can be any angle between 100 and 170 degrees.

For example, as shown in Figure 2, taking a subpixel group 10 comprising two third subpixels 130 as an example, the two third subpixels 130 located at the outermost edge in the first direction are these two subpixels 100. Taking the direction pointed to by the arrow in the X direction as upward, the aforementioned "at least one contour angle that is far away from each other" can refer to the angle at which the upper third subpixel 130 is far away from the light-emitting area of the lower third subpixel 130, and/or the angle at which the lower third subpixel 130 is far away from the light-emitting area of the upper third subpixel 130. For example, the light-emitting area of the same third subpixel 130 may include one chamfer, or may include two or more chamfers. For example, the light-emitting area of at least some of the third subpixels 130 in at least some subpixel groups 10 includes at least one chamfer. For example, the light-emitting area of each third subpixel 130 in each subpixel group 10 includes two chamfers.

Of course, the embodiments disclosed herein are not limited to this. When a subpixel group includes at least three third subpixels 130, the two third subpixels 130 located at the outermost edge are the uppermost third subpixel 130 and the lowermost third subpixel 130. The light-emitting area of the third subpixel 130 located on the non-edge may include a chamfer or may not include a chamfer.

Figure 4 is a schematic diagram of the light-emitting area of the third sub-pixel in another example of the display substrate shown in Figure 2.

For example, as shown in Figure 4, the outline angle of the light-emitting area of the third sub-pixel 130 can be a rounded chamfer. The included angle α between the extension lines of the two sides forming the rounded chamfer in the light-emitting area is 100 to 170 degrees, such as 120 to 150 degrees, or 110 to 140 degrees, or 130 to 160 degrees, or 132 to 137 degrees, or 135 degrees. The embodiments disclosed herein will not be listed one by one. The included angle α can be any angle between 100 and 170 degrees.

As shown in Figure 2, at least two adjacent sub-pixel groups 10 arranged in the first direction include a first sub-pixel group 11 and a second sub-pixel group 12. The third sub-pixel 130 in the first sub-pixel group 11 and the third sub-pixel 130 in the second sub-pixel group 12 are staggered in the second direction, and the second direction intersects with the first direction.

For example, as shown in Figure 2, the second direction can be the Y direction shown in the figure. For example, the angle between the first and second directions can be 80 to 100 degrees, such as when the first and second directions are perpendicular. For example, the first and second directions can be interchanged.

For example, as shown in Figure 2, the sub-pixel group 10 arranged along the first direction can be called a column of sub-pixel groups or a row of sub-pixel groups. In the same column of sub-pixel groups or the same row of sub-pixel groups, only some of the sub-pixel groups 10 are arranged adjacently, including the first sub-pixel group 11 and the second sub-pixel group 12, or any adjacent sub-pixel groups 10 include the first sub-pixel group 11 and the second sub-pixel group 12, such as the first sub-pixel group 11 and the second sub-pixel group 12 being arranged alternately in the first direction.

For example, as shown in FIG2, at least a portion of the orthographic projection of the light-emitting area of the third sub-pixel 130 in the first sub-pixel group 11 onto a straight line extending along the Y direction does not overlap with the orthographic projection of the light-emitting area of the third sub-pixel 130 in the second sub-pixel group 12 onto the same straight line. For example, a straight line extending along the X direction and passing through the light-emitting area of the third sub-pixel 130 in the first sub-pixel group 11 does not pass through the light-emitting area of the third sub-pixel 130 in the second sub-pixel group 12.

For example, as shown in FIG3, since the third sub-pixel 130 in the first sub-pixel group 11 and the third sub-pixel 130 in the second sub-pixel group 12 are staggered in the second direction, the width Rib of the mask strip between two adjacent mask openings in the mask template used to form the third sub-pixel 130 is such that the direction of the minimum width of the mask strip intersects with the first direction. Compared with the case where the mask openings used to form two adjacent third sub-pixels 130 are arranged along the first direction, i.e., as shown in FIG1, the mask openings used to form two adjacent third sub-pixels 130 in the display substrate provided in this disclosure are staggered in the second direction. The limiting direction of the minimum width Rib of the mask strip can be set to oblique rather than longitudinal or transverse (such as one of the first direction and the second direction being transverse and the other being longitudinal), which is beneficial to increase the size of Rib.

By staggering the third subpixels in different subpixel groups and setting the edge contour angle of the light-emitting area of the outermost third subpixel in the same subpixel group, the mask strip width (Rib) of the mask template can be maintained. Maintaining or increasing the mask strip width helps reduce the manufacturing difficulty of the mask, lowers the risk of color mixing, prevents color shift, and improves display quality. The mask strip width (Rib) meets the minimum manufacturing requirements and can even be larger, while also being suitable for mesh stretching.

For example, as shown in Figures 2 and 3, by setting the edge contour angle of the third sub-pixel 130 located at the edge of the sub-pixel group 10 to a chamfer, and by staggering the distribution of the third sub-pixel 130 located in the adjacent first sub-pixel group 11 and second sub-pixel group 12, the size of the mask opening 530 used to form the third sub-pixel 130 in the first direction can be increased, thereby further increasing the aperture ratio of the sub-pixel 100.

For example, in the pixel arrangement structure of the display substrate shown in Figure 2, with a PDL gap of 20 micrometers, a pixel pitch of 100 micrometers, and a Rib of 26.9 micrometers, the aperture ratio of the first sub-pixel 110 is 8.49%, the aperture ratio of the second sub-pixel 120 is 14.44%, the aperture ratio of the third sub-pixel 130 is 18.26%, and the total aperture ratio is 41.19%. The pixel arrangement structure shown in Figure 2 has an increased aperture ratio of 5.67% compared to the pixel arrangement structure shown in Figure 1. Compared to the pixel arrangement structure shown in Figure 1, where the same mask opening is used to form the light-emitting layers of two blue sub-pixels, the pixel arrangement structure shown in Figure 2, without changing the pixel pitch and PDL gap, allows for the increase of Rib and the size of the mask opening. This is achieved by setting the contour angle of the mask opening used to form the light-emitting area of the third sub-pixel 130 to a chamfer, such as a straight chamfer or a rounded chamfer, while simultaneously staggering the distribution of mask openings in adjacent rows or columns. This increases the overall aperture ratio of sub-pixel 100, which not only facilitates the realization of high PPI products and improves product lifespan but also reduces the manufacturing difficulty of the mask template.

For example, as shown in Figure 2, the ratio of the aperture ratio of the first sub-pixel 110, the second sub-pixel 120, and the third sub-pixel 130 can be 1:(1.2~1.8):(2.3~2.8). For instance, the size of the light-emitting area of the first sub-pixel 110 in the X and Y directions can be 22.22 μm and 37.41 μm, respectively; the size of the light-emitting area of the second sub-pixel 120 in the X and Y directions can be 37.78 μm and 37.41 μm, respectively; and the size of the light-emitting area of the third sub-pixel 130 in the X and Y directions can be 85 μm and 22.59 μm, respectively.

In some examples, as shown in Figure 2, multiple sub-pixel groups 10 are arranged in an array along a first direction and a second direction. In each sub-pixel group 10, the number of first sub-pixels 110, the number of second sub-pixels 120, and the number of third sub-pixels 130 are all equal. For example, in each sub-pixel group 10, the number of first sub-pixels 110, second sub-pixels 120, and third sub-pixels 130 can all be two, but it is not limited to this; it can also be three or more, depending on product requirements.

In some examples, as shown in Figure 2, within the same sub-pixel group 10, the first sub-pixel 110 and the second sub-pixel 120 are arranged along a first direction, and the first sub-pixel 110 and the third sub-pixel 130 are arranged along a second direction. For example, the second sub-pixel 120 and the third sub-pixel 130 are arranged along the second direction.

In some examples, as shown in Figure 2, the third sub-pixel 130 in the first sub-pixel group 11 and the first sub-pixel 110 in the second sub-pixel group 12 are arranged along a first direction. For example, the orthographic projection of the light-emitting area of the third sub-pixel 130 in the first sub-pixel group 11 onto a straight line extending along the Y direction overlaps with the orthographic projection of the light-emitting area of the first sub-pixel 110 in the second sub-pixel group 12 onto the same straight line. For example, the same straight line extending along the X direction passes through the light-emitting areas of the third sub-pixel 130 in the first sub-pixel group 11 and the light-emitting areas of the first sub-pixel 110 and the second sub-pixel 120 in the second sub-pixel group 12.

In some examples, as shown in Figure 2, the dimensions of the light-emitting areas of the first sub-pixel 110 and the second sub-pixel 120 in the first direction are both smaller than the dimension of the light-emitting area of the third sub-pixel 130 in the first direction; the first sub-pixel 110 and the third sub-pixel 130 are arranged alternately along the second direction. For example, the second sub-pixel 120 and the third sub-pixel 130 are arranged alternately along the second direction. For example, the sum of the dimension of the light-emitting area of the first sub-pixel 110 in the first direction, the dimension of the light-emitting area of the second sub-pixel 120 in the first direction, and the dimension of the interval between them can be greater than the dimension of the light-emitting area of the third sub-pixel 130 in the first direction.

For example, as shown in Figure 2, if the sub-pixel group 10 arranged along the Y direction is a row of sub-pixel groups, then the relative positional relationship of different sub-pixels 100 in the same row of sub-pixel groups is the same.

In some examples, as shown in Figure 2, the distance between the light-emitting areas of the two closest third sub-pixels 130 located in the first sub-pixel group 11 and the second sub-pixel group 12 is the first distance D1, and the distance between the light-emitting areas of the closest first sub-pixel 110 and the second sub-pixel 120 located in the first sub-pixel group 11 and the second sub-pixel group 12 is the second distance D2. The first distance D1 is not less than the second distance D2. For example, the first distance D1 is greater than the second distance D2.

For example, as shown in Figure 2, the distance between the light-emitting areas refers to the minimum distance between the edges of the two light-emitting areas that are close to each other. For example, the two third sub-pixels 130 that are located in the two sub-pixel groups 10 and are closest to each other refer to the two third sub-pixels 130 that have no other third sub-pixels 130 between them, or even no other sub-pixels 100. For example, the two third sub-pixels 130 can be the bottom third sub-pixel 130 in the first sub-pixel group 11 and the top third sub-pixel 130 in the second sub-pixel group 12. For example, the phrase "the first sub-pixel 110 and the second sub-pixel 120 that are closest to each other" can refer to the two sub-pixels 100 that have no other first sub-pixels 110 and the second sub-pixel 120 between them, or even no other sub-pixels 100. For example, the phrase "the first sub-pixel 110 and the second sub-pixel 120 that are closest to each other" can refer to the first sub-pixel 110 in the first sub-pixel group 11 and the second sub-pixel 120 in the second sub-pixel group 12, or the second sub-pixel 120 in the first sub-pixel group 11 and the first sub-pixel 110 in the second sub-pixel group 12.

By setting the relationship between the distance between the light-emitting areas of two adjacent third sub-pixels located in different sub-pixel groups and the distance between the light-emitting areas of adjacent first and second sub-pixels, it is beneficial to ensure that the mask strip width Rib in the mask used to form the light-emitting layer of the third sub-pixel can meet the minimum process manufacturing requirements, or even be larger, and adapt to mesh stretching.

For example, as shown in Figure 2, the two contour edges E1 and E2 of the light-emitting areas of the two closest third sub-pixels 130 located in the first sub-pixel group 11 and the second sub-pixel group 12 are opposite to each other and parallel to each other, which is beneficial to the uniformity of the mask strip width and the stability of the mesh.

In some examples, as shown in Figure 2, the included angle between the two sides connecting at least one of the contour angles of the two closest third sub-pixels 130 located in the first sub-pixel group 11 and the second sub-pixel group 12, or the included angle between the extensions of the two sides, is 100 to 170 degrees. By setting at least one contour angle of the two closest third sub-pixels 130 located in the two sub-pixel groups 10 to be chamfered, it is beneficial to ensure that the mask strip width Rib in the mask used to form the light-emitting layer of the third sub-pixel 130 meets the minimum process fabrication requirements, or even has a larger size, and is suitable for mesh stretching.

For example, as shown in Figure 2, the two closest contour angles α1 and α2 of the two third sub-pixels 130 located in the first sub-pixel group 11 and the second sub-pixel group 12, respectively, are both chamfered. For example, both contour angles α1 and α2 are between 100 and 170 degrees. For example, the two contour angles α1 and α2 may not be equal. For example, the difference between the two contour angles α1 and α2 is no greater than 10 degrees. For example, the two contour angles α1 and α2 may be equal.

For example, as shown in Figure 2, the shape of the light-emitting area of the first sub-pixel 110 and the second sub-pixel 120 can both be a standard rectangle or a rounded rectangle, and the shape of the light-emitting area of the third sub-pixel 130 can be a hexagon.

For example, as shown in Figure 2, the area of the light-emitting region of the first sub-pixel 110 can be larger than the area of the light-emitting region of the second sub-pixel 120, but it is not limited thereto; the area of the light-emitting region of the first sub-pixel 110 can also be smaller than the area of the light-emitting region of the second sub-pixel 120.

For example, as shown in Figure 2, the distance between the vertex of the chamfer α of the third sub-pixel 130 or the intersection of the two extended lines forming the chamfer α and the light-emitting area of the nearest sub-pixel 100 located at the outermost edge of the sub-pixel group 10 is the first sub-distance, and the distance between the other non-chamfered corners of the third sub-pixel 130 and the light-emitting area of the nearest sub-pixel 100 is the second sub-distance. The first sub-distance is greater than the second sub-distance.

For example, as shown in Figure 2, the distance between the third sub-pixel 130 and the second sub-pixel 120, which are located in adjacent first sub-pixel groups 11 and 12 respectively, is less than the first distance D1. For example, the distance between the third sub-pixel 130 and the second sub-pixel 120, which are located in adjacent first sub-pixel groups 11 and 12 respectively, is not greater than the second distance D2.

Figures 5 to 7 show pixel arrangement structures provided according to different examples of embodiments of the present disclosure.

For example, Figure 5 schematically shows a 6-row, 4-column subpixel group 10, with first subpixel groups 11 in rows 1 and 4, and second subpixel groups 12 in rows 2, 3, 5, and 6. Both first subpixel groups 11 and 12 have two third subpixels 130. However, it is not limited to this; Figure 5 can also be viewed as including a 4-row, 4-column subpixel group 10, with first subpixel groups 11 in rows 1 and 3, each including two third subpixels 130, and second subpixel groups 12 in rows 2 and 4, each including four third subpixels 130.

For example, Figure 6 schematically shows four rows of subpixel groups 10. The first and third rows contain first subpixel groups 11, and the second and fourth rows contain second subpixel groups 12. Both the first and second subpixel groups 11 and 12 include four third subpixels 130. Figure 6 schematically shows that the light-emitting area of each third subpixel 130 in each subpixel group includes a chamfer α, but this is not a limitation; it is also possible that only the uppermost and lowermost third subpixels 130 in each subpixel group have light-emitting areas with a chamfer α. For example, the four third subpixels 130 in each subpixel group 10 can form a light-emitting layer using the same mask opening.

For example, Figure 7 schematically shows four rows of subpixel groups 10. The first and third rows have second subpixel groups 12, and the second and fourth rows have first subpixel groups 11. Both the first and second subpixel groups 11 and 12 include three third subpixels 130. In each subpixel group, only the uppermost and lowermost third subpixels 130 have a chamfered α in their light-emitting areas. For example, the three third subpixels 130 in each subpixel group form a light-emitting layer using the same mask opening.

For example, as shown in Figures 5 to 7, among the sub-pixels 100 arranged along the second direction, at most two third sub-pixels 130 are adjacent, such as having at most two third sub-pixels 130 between two adjacent first sub-pixels 110. Similarly, among the sub-pixels 100 arranged along the second direction, at most two first sub-pixels 110 are adjacent, such as having at most two first sub-pixels 110 between two adjacent third sub-pixels 130. Likewise, among the sub-pixels 100 arranged along the second direction, at most two second sub-pixels 120 are adjacent, such as having at most two second sub-pixels 120 between two adjacent third sub-pixels 130.

Figure 8 shows a pixel arrangement structure provided according to another example of an embodiment of the present disclosure. Figure 9 is a schematic diagram of a mask for forming the pixel arrangement structure shown in Figure 8.

In some examples, as shown in Figures 8 and 9, the light-emitting areas of sub-pixels 100 in two adjacent sub-pixel groups 10 arranged along the second direction are symmetrically distributed with respect to the first dividing line LB1 located between the two adjacent sub-pixel groups 10 and extending along the first direction. Furthermore, at least four third sub-pixels 130 located on both sides of and adjacent to the first dividing line LB1 in the two adjacent sub-pixel groups 10 arranged along the second direction are configured to correspond to the same mask opening. The pixel arrangement structure shown in Figure 8 differs from the pixel arrangement structure shown in Figure 2 in that the two adjacent columns of sub-pixel groups 10 arranged along the first direction are mirror images of each other with respect to the first dividing line.

For example, as shown in Figures 8 and 9, in a pixel arrangement structure with a PDL gap of 20 micrometers, a pixel pitch of 100 micrometers, and a Rib of 32.9 micrometers, the aperture ratio of the first sub-pixel 110 is 9.92%, the aperture ratio of the second sub-pixel 120 is 16.86%, the aperture ratio of the third sub-pixel 130 is 21.32%, and the total aperture ratio is 48.09%. The pixel arrangement structure shown in Figure 8 has an increased aperture ratio of 23.37% compared to the pixel arrangement structure shown in Figure 1.

Compared to the pixel arrangement structure shown in Figure 1, where the same mask opening is used to form the light-emitting layers of two blue sub-pixels, the pixel arrangement structure shown in Figure 8, without changing the pixel pitch and PDL gap, allows for the following improvements: by setting the contour angle of the mask opening used to form the light-emitting area of the third sub-pixel 130 to a chamfer, such as a straight chamfer or a rounded chamfer, while simultaneously staggering the distribution of mask openings in adjacent rows or columns, and mirroring the sub-pixels 100 in adjacent sub-pixel groups 10 arranged along the second direction, it is beneficial to increase the Rib and the size of the mask opening, thereby increasing the overall aperture ratio of the sub-pixels 100. This not only facilitates the realization of higher PPI products and improves product lifespan but also further reduces the manufacturing difficulty of the mask template.

For example, as shown in Figure 8, the ratio of the aperture ratio of the first sub-pixel 110, the second sub-pixel 120, and the third sub-pixel 130 can be 1:(1.2~1.8):(2.3~2.8). For example, the dimensions of the light-emitting area of the first sub-pixel 110 in the X and Y directions can be 22.22 μm and 37.41 μm, respectively; the dimensions of the light-emitting area of the second sub-pixel 120 in the X and Y directions can be 37.78 μm and 37.41 μm, respectively; and the dimensions of the light-emitting area of the third sub-pixel 130 in the X and Y directions can be 85 μm and 22.59 μm, respectively.

For example, as shown in Figure 8, the first sub-pixel 110 in two adjacent sub-pixel groups 10 arranged along the second direction is symmetrically distributed with respect to the first dividing line. For example, the second sub-pixel 120 in two adjacent sub-pixel groups 10 arranged along the second direction is symmetrically distributed with respect to the first dividing line. For example, the third sub-pixel 130 in two adjacent sub-pixel groups 10 arranged along the second direction is symmetrically distributed with respect to the first dividing line.

For example, Figure 8 schematically shows that the contour angles of the light-emitting areas of two adjacent third sub-pixels 130 arranged along the second direction (no other sub-pixels 100 are set between the two adjacent third sub-pixels 130) are chamfered when they are close to each other. However, it is not limited to this. The light-emitting areas of the two adjacent third sub-pixels 130 may only have chamfered contour angles when they are far apart from each other, and the contour angles when they are close to each other may be angles less than 100 degrees, such as right angles.

For example, as shown in Figure 8, the contour angles of the light-emitting areas of four adjacent third sub-pixels 130 that are close to each other can all be set to less than 100 degrees, such as right angles. For example, the contour angles of the light-emitting areas of four adjacent third sub-pixels 130 that are located at the outermost edge in both the first and second directions can be set to chamfers of 100 to 170 degrees.

For example, Figure 9 schematically shows that the light-emitting layer of each first sub-pixel 110 is formed using a mask opening 510, the light-emitting layer of each second sub-pixel 120 is formed using a mask opening 520, and the light-emitting layers of the four third sub-pixels 130 are formed using a mask opening 530.

Figure 10 is a schematic diagram of another mask template for forming the pixel arrangement structure shown in Figure 8.

In some examples, as shown in Figures 8 and 10, in two adjacent sub-pixel groups 10 arranged along the second direction, at least two first sub-pixels 110 located on both sides of the first dividing line and adjacent to it are configured to correspond to the same mask opening 510, and at least two second sub-pixels 120 located on both sides of the first dividing line and adjacent to it are configured to correspond to the same mask opening 520.

By setting four third sub-pixels to correspond to the same mask opening, setting at least two first sub-pixels to correspond to the same mask opening, and setting at least two second sub-pixels to correspond to the same mask opening, it is beneficial to further improve the overall aperture ratio of the display device, reduce the manufacturing difficulty of forming the mask template corresponding to each color sub-pixel, and adapt to mesh printing.

Figure 11 shows a pixel arrangement structure according to another example of an embodiment of the present disclosure. Figure 12 is a schematic diagram of a mask for forming the pixel arrangement structure shown in Figure 11.

In some examples, as shown in Figures 11 and 12, the light-emitting areas of sub-pixels 100 in two adjacent sub-pixel groups 10 arranged along the second direction are symmetrically distributed with respect to a first dividing line LB1 located between the two adjacent sub-pixel groups 10 and extending along the first direction. At least four third sub-pixels 130 located on both sides of and adjacent to the first dividing line in two adjacent sub-pixel groups 10 arranged along the second direction are configured to correspond to the same mask opening. Each sub-pixel group 10 includes N third sub-pixels 130, and a second dividing line LB2 extending along the second direction is included between the N/2th third sub-pixel 130 and the (N/2+1)th third sub-pixel 130 arranged along the first direction. In the same sub-pixel group 10, the light-emitting areas of sub-pixels 100 are symmetrically distributed with respect to the second dividing line LB2, and N is an even number. Figure 11 schematically shows N as 2, but is not limited to this; N can be 4, 6, or other even numbers.

The pixel arrangement structure shown in Figure 11 differs from that shown in Figure 8 in that the light-emitting areas of the sub-pixels 100 arranged along the second direction are mirror images of the second dividing line. For example, the light-emitting areas of two adjacent sub-pixel groups 10 arranged along the first direction are symmetrically distributed along the first dividing line and the second dividing line.

For example, as shown in Figures 11 and 12, in the pixel arrangement structure with a PDL gap of 20 micrometers, a pixel pitch of 100 micrometers, and a Rib of 26.2 micrometers, the aperture ratio of the first sub-pixel 110 is 10.88%, the aperture ratio of the second sub-pixel 120 is 18.49%, the aperture ratio of the third sub-pixel 130 is 23.39%, and the total aperture ratio is 52.75%. The pixel arrangement structure shown in Figure 11 has an aperture ratio that is 35.33% higher than that shown in Figure 1. Compared to the pixel arrangement structure shown in Figure 8, the pixel arrangement structure shown in Figure 11 has a smaller mask strip width Rib for the mask used to form the light-emitting layer of the third sub-pixel 130, which is beneficial for increasing the aperture ratio of the sub-pixel 100 without affecting the mask fabrication process.

Compared to the pixel arrangement structure shown in Figure 1, where the same mask opening is used to form the light-emitting layers of two blue sub-pixels, the pixel arrangement structure shown in Figure 11, without changing the pixel pitch and PDL gap, achieves a different result. By setting the contour angle of the mask opening used to form the light-emitting area of the third sub-pixel 130 to a chamfer, such as a straight chamfer or a rounded chamfer, while staggering the distribution of mask openings in adjacent rows or columns, and mirroring the sub-pixels 100 in adjacent sub-pixel groups 10 arranged in the second direction, while mirroring the sub-pixels 100 in the same sub-pixel group 10 along the first direction, it is beneficial to increase the size of the mask opening, thereby increasing the overall aperture ratio of the sub-pixels 100. This not only facilitates the realization of higher PPI products and improves product lifespan, but also further reduces the manufacturing difficulty of the mask template.

For example, as shown in Figure 11, the ratio of the aperture ratio of the first sub-pixel 110, the second sub-pixel 120, and the third sub-pixel 130 can be 1:(1.2~1.8):(2.3~2.8). For example, the size of the light-emitting area of the first sub-pixel 110 in the X and Y directions can be 22.22 μm and 37.41 μm, respectively; the size of the light-emitting area of the second sub-pixel 120 in the X and Y directions can be 37.78 μm and 37.41 μm, respectively; and the size of the light-emitting area of the third sub-pixel 130 in the X and Y directions can be 85 μm and 22.59 μm, respectively.

For example, as shown in Figure 11, in the same sub-pixel group 10, the light-emitting area of the first sub-pixel 110 arranged along the first direction is symmetrically distributed with respect to the second dividing line, the light-emitting area of the second sub-pixel 120 arranged along the first direction is symmetrically distributed with respect to the second dividing line, and the light-emitting area of the third sub-pixel 130 arranged along the first direction is symmetrically distributed with respect to the second dividing line.

For example, Figure 11 schematically shows that the contour angles of the light-emitting areas of two adjacent third sub-pixels 130 arranged along the second direction (no other sub-pixels 100 are set between the two adjacent third sub-pixels 130) are chamfered when they are close to each other. However, it is not limited to this. The light-emitting areas of the two adjacent third sub-pixels 130 may only have chamfered contour angles when they are far apart from each other, and the contour angles when they are close to each other may be angles less than 100 degrees, such as right angles.

For example, as shown in Figure 11, the contour angles of the light-emitting areas of four adjacent third sub-pixels 130 that are close to each other can all be set to less than 100 degrees, such as right angles. For example, the contour angles of the light-emitting areas of four adjacent third sub-pixels 130 that are located at the outermost edge in both the first and second directions can be set to chamfers of 100 to 170 degrees.

For example, Figure 12 schematically shows that the light-emitting layer of each first sub-pixel 110 is formed using a mask opening 510, the light-emitting layer of each second sub-pixel 120 is formed using a mask opening 520, and the light-emitting layers of the four third sub-pixels 130 are formed using a mask opening 530.

Figure 13 is a schematic diagram of another mask template for forming the pixel arrangement structure shown in Figure 11.

In some examples, as shown in Figures 11 and 13, in the same sub-pixel group 10, at least two first sub-pixels 110 and at least two second sub-pixels 120 correspond to the same mask opening.

For example, as shown in Figures 11 and 13, in the same sub-pixel group 10, two first sub-pixels 110 correspond to the same mask opening or two second sub-pixels 120 correspond to the same mask opening.

For example, as shown in Figures 11 and 13, in a plurality of sub-pixel groups 10 arranged along the second direction, four first sub-pixels 110 correspond to the same mask opening, and two second sub-pixels 120 correspond to the same mask opening; or, two first sub-pixels 110 correspond to the same mask opening, and four second sub-pixels 120 correspond to the same mask opening. For example, in two adjacent sub-pixel groups 10 arranged along the second direction, two first sub-pixels 110 or two second sub-pixels 120 correspond to the same mask opening, and four third sub-pixels 130 correspond to the same mask opening. For example, in two adjacent sub-pixel groups 10 arranged along the second direction, two first sub-pixels 110 correspond to the same mask opening, and four second sub-pixels 120 correspond to the same mask opening; or two second sub-pixels 120 correspond to the same mask opening, and four first sub-pixels 110 correspond to the same mask opening.

By setting four third sub-pixels to correspond to the same mask opening, setting at least two first sub-pixels to correspond to the same mask opening, and setting at least two second sub-pixels to correspond to the same mask opening, it is beneficial to further improve the overall aperture ratio of the display device, reduce the manufacturing difficulty of forming the mask template corresponding to each color sub-pixel, and adapt to mesh printing.

Figure 14 shows a pixel arrangement structure according to another example of an embodiment of the present disclosure. Figure 15 is a schematic diagram of a mask for forming the pixel arrangement structure shown in Figure 14. The main difference between the pixel arrangement structure shown in Figure 14 and the pixel arrangement structure shown in Figure 2 is that the shape of the light-emitting area of each sub-pixel 100 is different.

In some examples, as shown in Figure 14, the light-emitting area of the third sub-pixel 130 includes at least one first side 1011 extending along a first direction, and the extension directions of the sides 1021 and 1031 adjacent to the first side 1011 in the light-emitting areas of the first sub-pixel 110 and the second sub-pixel 120 both intersect with the first direction. For example, Figure 14 schematically shows that the light-emitting area of the third sub-pixel 130 includes one first side 1011 extending along the first direction, but it is not limited to this. The light-emitting area of the third sub-pixel 130 may also include two or three first sides 1011 extending along the first direction, etc., which can be set according to product requirements.

By setting the extension direction of the edge of the light-emitting area of the third sub-pixel and the edge of the light-emitting area of the adjacent first sub-pixel and the third sub-pixel, it is beneficial to improve color mixing, prevent color shift, increase ambient light contrast ratio (ACR), prevent reflection, and thus improve display quality.

In some examples, as shown in Figure 14, in the same sub-pixel group 10, the extension directions of the edge 1021 in the light-emitting area of the first sub-pixel 110 that is adjacent to the first edge 1011 and the edge 1031 in the light-emitting area of the second sub-pixel 120 that is adjacent to the first edge 1011 both intersect with the extension direction of the first edge.

For example, as shown in Figure 14, spacers (PS) can be provided between the first edge 1011 of the light-emitting area of the third sub-pixel 130 and the edge 1021 of the light-emitting area of the adjacent first sub-pixel 110 and the edge 1031 of the light-emitting area of the second sub-pixel 120 to support the fine metal mask.

In some examples, as shown in FIG14, the light-emitting area of the third sub-pixel 130 includes at least one first side 1011 extending along the first direction. In the same sub-pixel group 10, the distance between the first side 1011 of the light-emitting area of at least two adjacent third sub-pixels 130 and the center line extending along the first direction in the light-emitting area of the first sub-pixel 110 is different.

By setting the position of the first side in the light-emitting area of different third sub-pixels within the same sub-pixel, it is beneficial to improve the problem of uneven display.

For example, as shown in Figure 14, the same sub-pixel group 10 includes two third sub-pixels 130. The straight line containing the first side 1011 in the light-emitting area of one third sub-pixel 130 does not pass through the first side 1011 in the light-emitting area of the other third sub-pixel 130. Of course, the embodiments of this disclosure are not limited to the same sub-pixel group 10 including two third sub-pixels 130. For example, it may include three or more third sub-pixels 130, wherein the first side 1011 of two adjacent third sub-pixels 130 can be set in the manner described above.

In some examples, as shown in Figure 14, in the same sub-pixel group 10, the first side 1011 of one of at least two adjacent third sub-pixels 130 is close to the first sub-pixel 110 and the second sub-pixel 120 in its sub-pixel group 10, while the first side 1011 of the other of the aforementioned at least two adjacent third sub-pixels 130 is far away from the first sub-pixel 110 and the second sub-pixel 120 in its sub-pixel group 10.

For example, as shown in Figure 14, the same sub-pixel group 10 includes two third sub-pixels 130. The first side 1011 of the light-emitting area of one of the two third sub-pixels 130 is close to the light-emitting area of the first sub-pixel 110 in the sub-pixel group 10 to which it belongs. The first side 1011 of the light-emitting area of the other of the two third sub-pixels 130 is close to the light-emitting area of the first sub-pixel 110 in the adjacent sub-pixel group 10.

In some examples, as shown in Figure 14, the light-emitting area of the third sub-pixel 130 also includes a second side 1012 and a third side 1013 connected to each other. The angle between the second side 1012 and the edge of the light-emitting area of the first sub-pixel 110 adjacent to it is no greater than 5 degrees, and the angle between the third side 1013 and the edge of the light-emitting area of the second sub-pixel 120 adjacent to it is no greater than 5 degrees. The first side 1011 and the second side 1012 are located on both sides of the center of the light-emitting area of the third sub-pixel 130 in the second direction.

By setting the extension direction of the edge of the light-emitting area of the third sub-pixel and the edge of the light-emitting area of its adjacent first sub-pixel, it is beneficial to improve color mixing and prevent color shift.

For example, as shown in Figure 14, the second side 1012 of the light-emitting area of the third sub-pixel 130 is parallel to the side of the light-emitting area of the first sub-pixel 110 that is adjacent to it, and the third side 1013 of the light-emitting area of the third sub-pixel 130 is parallel to the side of the light-emitting area of the second sub-pixel 120 that is adjacent to it.

For example, as shown in Figure 14, the light-emitting area of the third sub-pixel 130 also includes a fourth side 1014 and a fifth side 1015 connected to both ends of the first side 1011, respectively. The angle between the fourth side 1014 and the edge of the light-emitting area of the adjacent first sub-pixel 110 is no greater than 5 degrees, and the angle between the fifth side 1015 and the edge of the light-emitting area of the adjacent second sub-pixel 120 is no greater than 5 degrees. For example, the fourth side 1014 is parallel to the edge of the light-emitting area of the adjacent first sub-pixel 110, and the fifth side 1015 is parallel to the edge of the light-emitting area of the adjacent second sub-pixel 120.

For example, as shown in Figure 15, in the same sub-pixel group 10, the light-emitting layers of the two third sub-pixels 130 are formed by the same mask opening 530, the light-emitting layers of the two first sub-pixels 110 are formed by two mask openings 510, and the light-emitting layers of the two second sub-pixels 120 are formed by two mask openings 520.

For example, the aperture ratio of the pixel arrangement structure shown in Figure 14 is greater than 60%, which is beneficial to improving product lifespan.

For example, as shown in Figure 14, the ratio of the aperture ratio of the first sub-pixel 110, the second sub-pixel 120, and the third sub-pixel 130 can be 1:(1.2~1.8):(2.3~2.8). For example, the size of the light-emitting area of the first sub-pixel 110 in the X and Y directions can be 53.81 micrometers and 50 micrometers, respectively; the size of the light-emitting area of the second sub-pixel 120 in the X and Y directions can be 60 micrometers and 53.81 micrometers, respectively; and the size of the light-emitting area of the third sub-pixel 130 in the X and Y directions can be 137.58 micrometers and 91.96 micrometers, respectively.

Figure 14 schematically shows the same pixel arrangement as that shown in Figure 2, but it is not limited to this. The pixel arrangement shown in Figure 14 can also adopt the pixel arrangement shown in Figures 5 to 7, Figure 8 or Figure 11 to further increase the aperture ratio and improve the product life.

Figure 16 is an equivalent circuit diagram of a pixel circuit. As shown in Figure 16, the pixel circuit may include eight transistors (first transistor T1 to eighth transistor T8) and one storage capacitor C. The pixel circuit is connected to nine signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, light emission signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA, and first power supply line VDD).

For example, a pixel circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. For example, the first node N1 is connected to the second terminal of the first transistor T1, the first terminal of the second transistor T2, the gate electrode of the third transistor T3, and the first terminal of the storage capacitor C, respectively; the second node N2 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, the second terminal of the fifth transistor T5, and the second terminal of the eighth transistor T8, respectively; the third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, and the first terminal of the sixth transistor T6, respectively; and the fourth node N4 is connected to the second terminal of the sixth transistor T6 and the second terminal of the seventh transistor T7, respectively.

For example, the first end of the storage capacitor C is connected to the first node N1, and the second end of the storage capacitor C is connected to the first power line VDD.

For example, the first transistor T1 can be called the first initialization transistor. The gate electrode of the first transistor T1 is connected to the third scan signal line S3, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the first node N1.

For example, the second transistor T2 can be called a compensation transistor. The gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3.

For example, the third transistor T3 can be called the driving transistor. The gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

For example, the fourth transistor T4 can be called a data writing transistor. The gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2.

For example, the fifth transistor T5 can be called the first light-emitting control transistor. The gate electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.

For example, the sixth transistor T6 can be called the second light-emitting control transistor. The gate electrode of the sixth transistor T6 is connected to the light-emitting signal line EM. The first electrode of the sixth transistor T6 is connected to the third node N3. The second electrode of the sixth transistor T6 is connected to the fourth node N4.

For example, the seventh transistor T7 can be called the second initialization transistor. The gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

For example, the eighth transistor T8 can be called the third initialization transistor. The gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, the first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is connected to the second node N2.

For example, the first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

For example, the signal of the first power line VDD is a continuously supplied high-level signal, and the signal of the second power line VSS is a continuously supplied low-level signal.

For example, transistors T1 through T8 can be either P-type or N-type transistors. Using the same type of transistor in the pixel circuit simplifies the manufacturing process, reduces the complexity of the display panel manufacturing, and improves product yield. In some possible implementations, transistors T1 through T8 may include both P-type and N-type transistors.

For example, transistors T1 through T8 can be low-temperature polycrystalline silicon (LTPS) transistors, oxide transistors, or a combination of both. The active layer of the LTPS transistor is made of LTPS, while the active layer of the oxide transistor is made of oxide. LTPS transistors offer advantages such as high mobility and fast charging, while oxide transistors offer advantages such as low leakage current. Integrating LTPS and oxide transistors onto a single display substrate forms a low-temperature polycrystalline oxide (LTPO) display substrate. This leverages the advantages of both to achieve low-frequency driving, thereby reducing power consumption and improving display quality.

Figures 17A to 17F are schematic diagrams of different film layers in a display substrate.

For example, as shown in Figure 17A, the semiconductor layer includes the active layers of the first transistor T1 to the eighth transistor T8 and the first initial signal line 041. The active layers of the first transistor T1 to the seventh transistor T7 and the first initial signal line 041 are interconnected as a single structure, while the active layer of the eighth transistor T8 can be disposed separately. The circled positions of the first transistor T1 to the eighth transistor T8 in Figure 17A indicate the positions where the semiconductor layer and the gate metal layer are stacked.

For example, as shown in FIG17B, the first conductive pattern layer includes a first gate electrode 021, a second gate electrode 022, a fourth gate electrode 024, a second scan signal line 032, a light emission signal line 034, and a first electrode 081 of a storage capacitor. For example, the first conductive pattern layer is located on the side of the semiconductor layer away from the substrate, and an insulating layer is disposed between the first conductive pattern layer and the semiconductor layer.

For example, as shown in FIG17B, the orthographic projection of the first electrode 081 on the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor T3 on the substrate. For example, the first electrode 081 can simultaneously serve as an electrode of a storage capacitor and a gate electrode of the third transistor T3. For example, the orthographic projection of the first gate electrode 021 on the substrate at least partially overlaps with the orthographic projection of the active layer of the first transistor on the substrate, and the region where the first gate electrode 021 overlaps with the active layer of the first transistor can serve as the gate electrode of the first transistor T1 in a dual-gate structure. In an exemplary embodiment, the first gate electrode 21 is configured to be connected to a subsequently formed third scan signal line.

For example, as shown in FIG17B, the orthographic projection of the second gate electrode 022 on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor on the substrate. The region where the second gate electrode 022 overlaps with the active layer of the second transistor can serve as the gate electrode of the second transistor T2 with a dual-gate structure. For example, the second gate electrode 022 is configured to be connected to a subsequently formed first scan signal line.

For example, as shown in FIG17B, the orthographic projection of the fourth gate electrode 024 on the substrate at least partially overlaps with the orthographic projection of the active layer of the fourth transistor on the substrate. The region where the fourth gate electrode 024 overlaps with the active layer of the fourth transistor can serve as the gate electrode of the fourth transistor T4. For example, the fourth gate electrode 024 is configured to be connected to a subsequently formed first scan signal line.

For example, as shown in Figure 17B, the region where the second scan signal line 032 overlaps with the active layer of the seventh transistor can be used as the gate electrode of the seventh transistor T7, and the region where the second scan signal line 032 overlaps with the active layer of the eighth transistor can be used as the gate electrode of the eighth transistor T8.

For example, as shown in Figure 17B, the light-emitting signal line 034 can be located between the first electrode plate 081 and the second scan signal line 032. The area where the light-emitting signal line 034 overlaps with the active layer of the fifth transistor can be used as the gate electrode of the fifth transistor T5. The area where the light-emitting signal line 034 overlaps with the active layer of the sixth transistor can be used as the gate electrode of the sixth transistor T6.

For example, as shown in FIG17C, the second conductive pattern layer includes a second electrode 082 for a storage capacitor and a shielding electrode 035. For example, the second conductive pattern layer is located on the side of the first conductive pattern layer away from the semiconductor layer, and an insulating layer is disposed between the second conductive pattern layer and the first conductive pattern layer.

For example, as shown in Figures 17B and 17C, the orthographic projection of the second electrode plate 082 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 081 on the substrate. The second electrode plate 082 can serve as another electrode plate of a storage capacitor, and the first electrode plate 081 and the second electrode plate 082 constitute the storage capacitor of the pixel circuit. For example, the second electrode plate 082 can be provided with a board-level connecting strip 083. Since the second electrode plate 082 in each circuit unit is connected to the subsequently formed first power line, by connecting the second electrode plates 082 of adjacent circuit units to each other, the second electrode plate 082 and the board-level connecting strip 083 can be multiplexed as power signal lines. This ensures that multiple second electrode plates in a unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects in the display substrate, and ensuring the display effect of the display substrate.

For example, as shown in FIG17C, the second electrode plate 082 is provided with an opening 084, the opening 084 exposes the insulating layer covering the first electrode plate 081, and the orthographic projection of the first electrode plate 081 on the substrate includes the orthographic projection of the opening 084 on the substrate. The opening 084 is configured to accommodate a via formed subsequently. The via is located in the opening 084 and exposes the first electrode plate 081, so that the connecting electrode 312 formed subsequently is connected to the first electrode plate 081.

For example, as shown in Figure 17C, the orthographic projection of the shielding electrode 035 on the substrate at least partially overlaps with the orthographic projection of the active layer (the node between the two gate electrodes) of the second transistor T2 on the substrate. For example, the shielding electrode 035 is configured to shield the effects of data voltage transitions on the first transistor T1 and the second transistor T2, preventing data voltage transitions from affecting the normal operation of the pixel circuit and improving the display effect.

For example, as shown in Figure 17D, the third conductive pattern layer includes a first scan signal line 031, a third scan signal line 033, a second initial signal line 042, a third initial signal line 043, a power connection line 044, an auxiliary scan signal line 045, a first connecting electrode 051, a second connecting electrode 052, a third connecting electrode 053, a fourth connecting electrode 054, and a fifth connecting electrode 055. For example, the third conductive pattern layer is located on the side of the second conductive pattern layer away from the first conductive pattern layer, and an insulating layer is provided between the third conductive pattern layer and the second conductive pattern layer.

For example, as shown in Figure 17D, the first scan signal line 031 is connected to the second gate electrode 022 (also the fourth gate electrode 024) in each circuit unit through a via in each circuit unit, so that the first scan signal line 031 writes the first scan signal into the gate electrode of the second transistor T2 and the gate electrode of the fourth transistor T4 respectively.

For example, as shown in Figure 17D, the third scan signal line 033 can be located on the side of the first scan signal line 031 away from the second electrode plate 082. The third scan signal line 033 is connected to the first gate electrode 021 in each circuit unit through a via in each circuit unit, thereby realizing that the third scan signal line 033 writes the third scan signal to the gate electrode of the first transistor T1.

For example, as shown in Figure 17D, the second initial signal line 042 can be located on one side of the second electrode plate 082. The second initial signal line 042 is connected to the first region of the active layer of the seventh transistor in each circuit unit through a via in each circuit unit, thereby realizing that the second initial signal line 042 writes the second initial signal into the first electrode of the seventh transistor T7.

For example, as shown in Figure 17D, the third initial signal line 043 can be located on the side of the second initial signal line 042 away from the second electrode plate 082. The third initial signal line 043 is connected to the first region of the active layer of the eighth transistor in each circuit unit through a via in each circuit unit, thereby realizing that the third initial signal line 043 writes the third initial signal into the first electrode of the eighth transistor.

For example, as shown in Figure 17D, the power connection line 044 can be located between the first scan signal line 031 and the light emission signal line 034. The orthographic projection of the power connection line 044 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 082 on the substrate. The power connection line 044 is connected to the second electrode plate 082 in each circuit unit through a via in each circuit unit. Since the power connection line 044 is configured to connect to the subsequently formed first power line, the first power line writes the first power signal into the second electrode plate 082 of the storage capacitor.

For example, as shown in Figure 17D, the orthographic projection of the auxiliary scanning signal line 045 on the substrate and the orthographic projection of the second scanning signal line 032 on the substrate at least partially overlap. The auxiliary scanning signal line 045 is connected to the second scanning connection block through a via, and then connected to the second scanning signal line 032. Therefore, the second scanning signal line 032 and the auxiliary scanning signal line 045 constitute a double-layer structure of scanning signal lines, which can effectively reduce the resistance of the scanning signal lines and reduce the voltage drop of the scanning signal.

For example, as shown in Figure 17D, the first end of the first connecting electrode 051 is connected to the second region of the active layer of the first transistor (which is also the first region of the second active layer) through a via, and the second end of the first connecting electrode 051 is connected to the first electrode plate 081 through a via. For example, since the first electrode plate 081 also serves as the gate electrode of the third transistor T3, the first connecting electrode 051 makes the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 081 have the same potential, forming the first node N1 of the pixel circuit.

For example, as shown in Figure 17D, the first end of the second connection electrode 052 is connected to the first region of the active layer of the third transistor (which is also the second region of the active layer of the fourth transistor and the second region of the active layer of the fifth transistor) through a via, and the second end of the second connection electrode 052 is connected to the second region of the active layer of the eighth transistor through a via. For example, the second connection electrode 052 makes the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 have the same potential, forming the second node N2 of the pixel circuit.

For example, as shown in Figure 17D, the third connection electrode 053 is configured to connect to a subsequently formed data signal line. For example, the third connection electrode 053 can be referred to as a data connection electrode.

For example, as shown in Figure 17E, the fourth conductive pattern layer includes a data line 061, an anode connection electrode 312062, and a first power line 071. For example, the fourth conductive pattern layer is located on the side of the third conductive pattern layer away from the second conductive pattern layer, and an insulating layer is provided between the fourth conductive pattern layer and the third conductive pattern layer.

For example, as shown in Figures 17D and 17E, data line 061 is connected to the third connection electrode 053, which serves as a data connection electrode, via a via. Since the third connection electrode 053 is connected to the first region of the active layer of the fourth transistor, data line 061 can write data signals to the first electrode of the fourth transistor T4.

For example, as shown in Figure 17E, the anode connection electrode 062 is configured to be connected to the subsequently formed anode, that is, the anode connection electrode 062 is electrically connected to the first electrode 310 of the sub-pixel 100.

For example, as shown in Figures 17D and 17E, the first power line 071 is electrically connected to the power connection line 044 to form a mesh-like interconnected structure on the display substrate for transmitting the first power signal. This not only effectively reduces the resistance of the first power line 071 and reduces the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, thereby improving display uniformity and enhancing display quality.

For example, as shown in Figure 17F, the first electrode layer includes the anode of each sub-pixel 100, such as the first electrode 310 of the first sub-pixel 110, the second electrode 320 of the second sub-pixel 120, and the first electrode 310 of the third sub-pixel 130. For example, the first electrode 310 layer is located on the side of the fourth conductive pattern layer away from the second conductive pattern layer, and an insulating layer is provided between the first electrode 310 layer and the fourth conductive pattern layer. The first electrode 310 is electrically connected to the anode connection electrode 312 in the fourth conductive layer. The arrangement pattern of the sub-pixels 100 shown in Figure 17F can be the same as the arrangement pattern of the sub-pixels 100 shown in Figures 2 to 6.

Figure 17G is a structural diagram showing the stacking of the first electrode layer and the fourth conductive pattern layer. Figure 18 is a partial cross-sectional structural diagram of a display substrate provided according to an embodiment of the present disclosure.

In some examples, as shown in FIG18, at least a portion of the sub-pixel 100 includes a light-emitting functional layer 330, a first electrode 310, a second electrode 320, and a pixel circuit. The first electrode 310 is located between the light-emitting functional layer 330 and the substrate 01 and is electrically connected to the pixel circuit. The second electrode 320 is located on the side of the light-emitting functional layer 330 away from the first electrode 310. The pixel circuit can be the pixel circuit shown in FIG16 to FIG17G.

For example, as shown in Figure 18, the light-emitting functional layer 330 may include a light-emitting layer and functional layers, such as a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). For example, the first electrode 310 may be an anode, and the second electrode 320 may be a cathode. For example, the cathode may be formed of a material with high conductivity and low work function; for example, the cathode may be made of a metallic material. For example, the anode may be formed of a transparent conductive material with a high work function.

For example, Figure 18 does not show the specific film layer between the anode connection electrode 062 and the substrate 01, but uses film layer 006 for general illustration. Film layer 006 includes the aforementioned semiconductor layer, first conductive pattern layer, second conductive pattern layer, third conductive pattern layer, and insulating layer between adjacent layers. For example, a planarization layer PLN is provided between the fourth conductive pattern layer and the first electrode 310. For example, other film layers (not shown), such as encapsulation layers, are also provided on the side of the second electrode 310 away from the substrate 01.

For example, as shown in Figures 17F, 17G, and 18, the first electrode 310 includes a main electrode 311 and a connecting electrode 312 connected to each other. Along a direction perpendicular to the substrate 01, the connecting electrode 312 does not overlap with the light-emitting area of the sub-pixel 100. For example, the main electrode 311 overlaps with the light-emitting area and has a shape substantially the same as the light-emitting area, while the connecting electrode 312 is used for electrical connection to the pixel circuit. For example, the main electrode 311 and the connecting electrode 312 are integrally formed. For example, the main electrode 311 of the first sub-pixel 110 and the second sub-pixel 120 is quadrilateral in shape, such as a rectangle, while the main electrode 311 of the third sub-pixel 130 is hexagonal in shape. For example, the connecting electrode 312 of each sub-pixel 100 is quadrilateral in shape. However, this is not a limitation; the shapes of the main electrode 311 and the connecting electrode 312 can be set according to product requirements.

For example, as shown in Figure 17G, the display substrate includes multiple data lines 061, and the angle between the extension direction of at least one data line 061 and a first direction, such as the X direction, is 87 to 93 degrees. For example, the angle between each data line 061 and the first direction is 87 to 93 degrees. For example, the angle between each data line 061 and the first direction is 89 to 91 degrees. For example, the angle between each data line 061 and the first direction is 90 degrees, that is, the data line 061 is perpendicular to the first direction.

In some examples, as shown in Figures 17D to 17G, gate line 031, i.e., the first scan signal line 031, has an angle between its extension direction and the first direction of at least one gate line 031 not exceeding 3 degrees. For example, the angle between the extension direction of gate line 031 and the first direction is not greater than 2 degrees. For example, the angle between the extension direction of gate line 031 and the first direction is not greater than 1 degree. For example, the extension direction of gate line 031 is parallel to the first direction.

For example, as shown in FIG17F, in the same sub-pixel group 10, the connecting electrode 312 of the third sub-pixel 130 is located between its main electrode 311 and the main electrode 311 of the second sub-pixel 120, the connecting electrode 312 of the second sub-pixel 120 is located between its main electrode 311 and the main electrode 311 of the first sub-pixel 110, the connecting electrode 312 of the first sub-pixel 110 is located between its main electrode 311 and the main electrode 311 of the third sub-pixel 130, and the distance between the connecting electrode 312 of the second sub-pixel 120 and the main electrode 311 of the third sub-pixel 130 is greater than the size of the main electrode 311 of the second sub-pixel 120 in the second direction.

For example, as shown in FIG17F, the first electrode 310 of the third sub-pixel 130 located in the same sub-pixel group 10 has a different shape. For example, the first electrode 310 of each first sub-pixel 110 has the same shape. For example, the first electrode 310 of each second sub-pixel 120 has the same shape.

For example, as shown in Figure 17F, the edge of the main electrode 311 of the third sub-pixel 130 in the first sub-pixel group 11 that is far from the connecting electrode 312 and extends along the X direction is the first electrode edge E01. The edge of the main electrode 311 of the first sub-pixel 110 in the second sub-pixel group 12 that is far from the connecting electrode 312 and extends along the X direction is the second electrode edge E02. The edge of the main electrode 311 of the second sub-pixel 120 in the second sub-pixel group 12 that is far from the connecting electrode 312 and extends along the X direction is the third electrode edge E03. The first electrode edge E01, the second electrode edge E02, and the third electrode edge E03 are located on the same straight line. For example, in the second sub-pixel group 12, the edge of the main electrode 311 of the third sub-pixel 130 extending away from the connecting electrode 312 and along the X direction is the fourth electrode edge E04; in the first sub-pixel group 11, the edge of the main electrode 311 of the first sub-pixel 110 extending away from the connecting electrode 312 and along the X direction is the fifth electrode edge E05; and in the first sub-pixel group 11, the edge of the main electrode 311 of the second sub-pixel 120 extending close to the connecting electrode 312 and along the X direction is the sixth electrode edge E06. The fourth electrode edge E04, the fifth electrode edge E05, and the sixth electrode edge E06 are located on the same straight line. By setting the phase position relationship of the first electrode 310 in the first sub-pixel group 11 and the second sub-pixel group 12, it is beneficial to increase the pixel aperture ratio.

For example, as shown in Figure 17G, the length of the anode connection electrode 062 connected to the first electrode 310 of different first sub-pixels 110 can be the same or different. For example, the length of the anode connection electrode 062 connected to the first electrode 310 of different second sub-pixels 120 can be the same or different. For example, the length of the anode connection electrode 062 connected to the first electrode 310 of different third sub-pixels 130 can be the same or different. The length and position of the anode connection electrode 062 are jointly determined by the positions of the first electrode 310 of the sub-pixel 100 and the transistor.

For example, as shown in Figure 17G, the length of the anode connecting electrode 062 connected to the first electrode 310 of the first sub-pixel 110 in the first sub-pixel group 11 is different from the length of the anode connecting electrode 062 connected to the first electrode 310 of the first sub-pixel 110 in the second sub-pixel group 12. For example, the length of the anode connecting electrode 062 connected to the first electrode 310 of the second sub-pixel 120 in the first sub-pixel group 11 is different from the length of the anode connecting electrode 062 connected to the first electrode 310 of the second sub-pixel 120 in the second sub-pixel group 12. For example, the length of the anode connecting electrode 062 connected to the first electrode 310 of the third sub-pixel 130 in the first sub-pixel group 11 is different from the length of the anode connecting electrode 062 connected to the first electrode 310 of the third sub-pixel 130 in the second sub-pixel group 12.

Figures 19A and 19B are schematic diagrams of a fourth conductive pattern layer and a first electrode layer provided according to an example of an embodiment of the present disclosure. Figure 19C is a stack-up diagram of the fourth conductive pattern layer and the first electrode layer shown in Figures 19A and 19B. The structural layers preceding the fourth conductive pattern layer in the display substrate shown in Figures 19A to 19C may have the same features as the corresponding structural layers shown in Figures 17A to 17G, and will not be described again here.

The difference between Figure 19B and Figure 17F lies in their pixel arrangement structure. Similarly, the difference between the fourth conductive pattern layer shown in Figure 19A and the fourth conductive pattern layer shown in Figure 17E lies in the length and shape of the anode connecting electrode. The length of the anode connecting electrode is related to the pixel arrangement structure. The arrangement pattern of sub-pixels 100 shown in Figure 19B can be the same as that shown in Figure 8.

For example, as shown in FIG19B, the first electrode 310 of the second sub-pixel 120 located in the same sub-pixel group 10 has the same shape. For example, the first electrode 310 of the second sub-pixel 120 located in the first sub-pixel group 11 has a different shape than the first electrode 310 of the second sub-pixel 120 located in the second sub-pixel group 12. For example, the first electrode 310 of the first sub-pixel 110 located in the same sub-pixel group 10 has the same shape. For example, the first electrode 310 of the first sub-pixel 110 located in different sub-pixel groups 10 has the same shape. For example, the first electrode 310 of the third sub-pixel 130 located in the same sub-pixel group 10 has a different shape.

In some examples, as shown in FIG19B, in the same sub-pixel group 10, the connection electrode 312 of the third sub-pixel 130 is located between its main electrode 311 and the main electrode 311 of the second sub-pixel 120, the connection electrode 312 of the second sub-pixel 120 is located between its main electrode 311 and the main electrode 311 of the first sub-pixel 110, and the connection electrode 312 of the first sub-pixel 110 is located between its main electrode 311 and the main electrode 311 of the third sub-pixel 130.

In some examples, as shown in Figure 19B, in two adjacent sub-pixel groups 10 arranged along a second direction, such as the Y direction, the first electrode 310 of the third sub-pixel 130 is symmetrically distributed with respect to the first dividing line LB1.

In some examples, as shown in FIG19B, in two adjacent sub-pixel groups 10 arranged along a second direction, such as the Y direction, the first electrode 310 of at least one of the first sub-pixel 110 and the second sub-pixel 120 is symmetrically distributed with respect to the first dividing line LB1. For example, in two adjacent sub-pixel groups 10 arranged along the second direction, the first electrode 310 of the first sub-pixel 110 is symmetrically distributed with respect to the first dividing line LB1.

For example, as shown in FIG19B, in the same sub-pixel group 10, the connection electrode 312 of the third sub-pixel 130 is located between its main electrode 311 and the main electrode 311 of the second sub-pixel 120, and the connection electrode 312 of the first sub-pixel 110 is located between its main electrode 311 and the main electrode 311 of the third sub-pixel 130.

For example, as shown in FIG19C, the length of the anode connecting electrode 062 connected to the first electrode 310 of the first sub-pixel 110 in the first sub-pixel group 11 is different from the length of the anode connecting electrode 062 connected to the first electrode 310 of the first sub-pixel 110 in the second sub-pixel group 12. For example, the length of the anode connecting electrode 062 connected to the first electrode 310 of the second sub-pixel 120 in the first sub-pixel group 11 is different from the length of the anode connecting electrode 062 connected to the first electrode 310 of the second sub-pixel 120 in the second sub-pixel group 12. For example, the length of the anode connecting electrode 062 connected to the first electrode 310 of the third sub-pixel 130 in the first sub-pixel group 11 is different from the length of the anode connecting electrode 062 connected to the first electrode 310 of the third sub-pixel 130 in the second sub-pixel group 12.

Figures 20A and 20B are schematic diagrams of a fourth conductive pattern layer and a first electrode layer provided according to an example of an embodiment of the present disclosure. Figure 20C is a stack-up diagram of the fourth conductive pattern layer and the first electrode layer shown in Figures 20A and 20B. The structural layers preceding the fourth conductive pattern layer in the display substrate shown in Figures 20A to 20C may have the same features as the corresponding structural layers shown in Figures 17A to 17G, and will not be described again here.

The difference between Figure 20B and Figure 17F lies in their pixel arrangement structure. The difference between the fourth conductive pattern layer shown in Figure 20A and the fourth conductive pattern layer shown in Figure 17E lies in the length and shape of the anode connecting electrode. The length of the anode connecting electrode 062 is related to the pixel arrangement structure. The arrangement pattern of sub-pixels 100 shown in Figure 20B can be the same as that of sub-pixels 100 shown in Figure 11.

For example, as shown in Figure 20B, in two adjacent sub-pixel groups 10 arranged along the second direction, the first electrodes 310 of the four third sub-pixels 130 are symmetrically distributed with respect to the first dividing line LB1, and the first electrodes 310 of the four first sub-pixels 110 are symmetrically distributed with respect to the first dividing line LB1.

For example, as shown in Figure 20B, in the first sub-pixel group 11, the distance between the connecting electrodes 312 of two third sub-pixels 130 is smaller than the dimension of the main electrode 311 of the third sub-pixel 130 in the first direction. For example, in the same sub-pixel group 10, the connecting electrode 312 of one second sub-pixel 120 is located between its main electrode 311 and the main electrode 311 of the first sub-pixel 110, and the connecting electrode 312 of another second sub-pixel 120 is located between its main electrode 311 and the main electrode 311 of the third sub-pixel 130. By arranging the positions of the connecting electrodes 312 of different sub-pixels 100, a larger aperture ratio can be achieved while preventing interference between the first electrodes 310 of different sub-pixels 100.

For example, as shown in Figure 20B, in the first sub-pixel group 11, two first sub-pixels 110 are located between two second sub-pixels 120, and the two connecting electrodes 312 of the two third sub-pixels 130 are provided between the two connecting electrodes 312 of the first sub-pixels 110 and the two connecting electrodes 312 of the second sub-pixels 120; in the second sub-pixel group 12, two second sub-pixels 120 are located between two first sub-pixels 110, and the two connecting electrodes 312 of the two third sub-pixels 130 are located between the two connecting electrodes 312 of the two first sub-pixels 110.

For example, as shown in Figure 20B, the shape of the first electrode 310 of the third sub-pixel 130 in the first sub-pixel group 11 is different from the shape of the first electrode 310 of the third sub-pixel 130 in the second sub-pixel group 12.

For example, as shown in FIG20C, the length of the anode connecting electrode connected to the first electrode 310 of the first sub-pixel 110 in the first sub-pixel group 11 is different from the length of the anode connecting electrode connected to the first electrode 310 of the first sub-pixel 110 in the second sub-pixel group 12. For example, the length of the anode connecting electrode connected to the first electrode 310 of the second sub-pixel 120 in the first sub-pixel group 11 is different from the length of the anode connecting electrode connected to the first electrode 310 of the second sub-pixel 120 in the second sub-pixel group 12. For example, the length of the anode connecting electrode connected to the first electrode 310 of the third sub-pixel 130 in the first sub-pixel group 11 is different from the length of the anode connecting electrode connected to the first electrode 310 of the third sub-pixel 130 in the second sub-pixel group 12.

For example, as shown in Figure 20C, the shapes of the anode connection electrodes connected to the first electrodes 310 of different second sub-pixels 120 are different in the same sub-pixel group.

Figures 21A and 21B are schematic diagrams of partial layer structures of a display substrate provided according to another example of an embodiment of the present disclosure. Figure 21A is a stack-up diagram of the fourth conductive pattern layer and the first electrode layer. Figure 21B is a stack-up diagram of the third conductive pattern layer and the first electrode layer.

In some examples, as shown in Figures 21A and 21B, the display substrate includes multiple gate lines 031, namely first scan signal lines 031. At least one gate line 031 extends at an angle of 30 to 60 degrees to the first direction. For example, the angle between the extension direction of each gate line 031 and the first direction is 30 to 60 degrees. For example, the angle between the extension direction of the gate line 031 and the first direction is 45 degrees. For example, the angle between the extension direction of the gate line 031 and the first direction is 35 to 55 degrees. For example, the angle between the extension direction of the gate line 031 and the first direction is 37 to 50 degrees. The angle between the extension direction of the gate line and the first direction can also be other angles besides the above-mentioned angles within the range of 30 to 60 degrees, which will not be listed here.

The X direction shown in Figures 21A and 21B is the first direction, and the W direction is the X direction shown in Figures 2 to 3, Figures 5 to 15, Figures 17A to 17G, and Figures 19A to 20C.

The film layer between the fourth conductive pattern layer and the substrate in the display substrate shown in Figures 21A and 21B can have the same characteristics as the corresponding film layers shown in Figures 17A to 17G, and will not be described again here.

In the display substrate shown in Figures 21A and 21B, taking the extension direction of the gate line as the horizontal direction and the extension direction of the light-emitting area of the third sub-pixel 130 as the first direction, the opening of the sub-pixel 100 in the display substrate is set at an angle, which is beneficial to improve the oblique jaggedness, so as to optimize the image quality and improve the image quality uniformity of the display substrate.

For example, as shown in Figure 21A, the angle between the extension direction of data line 061 and the first direction is 89 to 91 degrees, such as when the extension direction of data line 061 is perpendicular to the first direction. For example, the angle between the extension direction of data line 061 and the extension direction of the gate line is 30 to 60 degrees.

For example, as shown in Figures 21A and 21B, the ratio of the aperture ratio of the first sub-pixel 110, the second sub-pixel 120, and the third sub-pixel 130 can be 1:(1.2~1.8):(2.3~2.8). For example, the size of the light-emitting area of the first sub-pixel 110 in the X and Y directions can be 50 micrometers and 53.81 micrometers, respectively; the size of the light-emitting area of the second sub-pixel 120 in the X and Y directions can be 60 micrometers and 53.81 micrometers, respectively; and the size of the light-emitting area of the third sub-pixel 130 in the X and Y directions can be 137.58 micrometers and 91.96 micrometers, respectively.

Figure 21A schematically shows that the pixel arrangement structure can be the same as that shown in Figure 17F, but with a different orientation. This example is not limited to this; the tilted pixel arrangement structure can adopt the pixel arrangement structure shown in any of the examples in Figures 2 to 15.

Figure 22 is a schematic block diagram of a display device according to another embodiment of the present disclosure. As shown in Figure 22, a display device provided in an embodiment of the present disclosure includes any of the above-described display substrates.

For example, the display substrate provided in this embodiment can be an organic light-emitting diode (OLED) display substrate. For example, the display substrate may or may not have a color filter layer.

For example, the display device also includes a cover plate located on the light-emitting side of the display substrate.

For example, the display device can be an organic light-emitting diode display device or other display device, as well as any product or component with display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigator that includes the display device. This embodiment is not limited to this.

The following points need to be explained:

(1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

(2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims (20)

A display substrate, comprising: Substrate; Multiple sub-pixels are located on the substrate. The multiple sub-pixels include multiple first sub-pixels, multiple second sub-pixels, and multiple third sub-pixels. The area of the light-emitting region of each first sub-pixel and the area of the light-emitting region of each second sub-pixel are not greater than the area of the light-emitting region of each third sub-pixel. The plurality of sub-pixels include a plurality of sub-pixel groups, each sub-pixel group including at least two first sub-pixels, at least two second sub-pixels and at least two third sub-pixels, wherein the at least two third sub-pixels are arranged along a first direction and the light-emitting areas of the at least two third sub-pixels are configured to correspond to the same mask opening; In at least one sub-pixel group, the included angle between the two sides connecting the two contour angles of the light-emitting areas of the two outermost third sub-pixels in the first direction, or the included angle between the extensions of the two sides, is 100 to 170 degrees. At least two adjacent sub-pixel groups arranged in the first direction include a first sub-pixel group and a second sub-pixel group, wherein the third sub-pixel in the first sub-pixel group and the third sub-pixel in the second sub-pixel group are staggered in the second direction, and the second direction intersects the first direction. According to the display substrate of claim 1, the plurality of sub-pixel groups are arranged in an array along the first direction and the second direction, and in each sub-pixel group, the number of the first sub-pixel, the number of the second sub-pixel, and the number of the third sub-pixel are all equal; In the same sub-pixel group, the first sub-pixel and the second sub-pixel are arranged along the first direction, and the first sub-pixel and the third sub-pixel are arranged along the second direction; The third sub-pixel in the first sub-pixel group and the first sub-pixel in the second sub-pixel group are arranged along the first direction. According to claim 1 or 2, the distance between the light-emitting areas of the two closest third sub-pixels located in the first sub-pixel group and the second sub-pixel group is a first distance, and the distance between the light-emitting areas of the first sub-pixel and the second sub-pixel located in the first sub-pixel group and the second sub-pixel group is a second distance, wherein the first distance is not less than the second distance. The display substrate according to any one of claims 1-3, wherein the included angle between two sides or the included angle between the extensions of at least one of the contour angles of the two closest third sub-pixels located in the first sub-pixel group and the second sub-pixel group respectively is 100 to 170 degrees. The display substrate according to any one of claims 1-4 further comprises: Multiple grid lines Wherein, the angle between the extension direction of at least one grid line and the first direction is no greater than 3 degrees. The display substrate according to any one of claims 1-4 further comprises: Multiple grid lines In this case, the angle between the extension direction of at least one grid line and the first direction is 30 to 60 degrees. According to claim 2, the size of the light-emitting area of the first sub-pixel and the light-emitting area of the second sub-pixel in the first direction is smaller than the size of the light-emitting area of the third sub-pixel in the first direction. The first sub-pixel and the third sub-pixel are arranged alternately along the second direction. According to claim 2, the light-emitting areas of the sub-pixels in two adjacent sub-pixel groups arranged along the second direction are symmetrically distributed with respect to a first dividing line located between the two adjacent sub-pixel groups and extending along the first direction, and at least four third sub-pixels in two adjacent sub-pixel groups arranged along the second direction, located on both sides of the first dividing line and adjacent to it, are configured to correspond to the same mask opening. According to claim 8, the display substrate includes N third sub-pixels in the same sub-pixel group, and the N/2th third sub-pixel and the (N/2+1)th third sub-pixel arranged along the first direction are separated by a second dividing line extending along the second direction, where N is an even number; Within the same sub-pixel group, the light-emitting areas of the sub-pixels are symmetrically distributed relative to the second dividing line. According to any one of claims 1-9, the light-emitting area of the third sub-pixel includes at least one first side extending along the first direction, and the extending directions of the sides adjacent to the first side in both the light-emitting areas of the first sub-pixel and the light-emitting areas of the second sub-pixel intersect with the first direction. The display substrate according to any one of claims 1-8, wherein the light-emitting area of the third sub-pixel includes at least one first side extending along the first direction, and in the same sub-pixel group, the distance between the first side of the light-emitting area of at least two adjacent third sub-pixels and the center line extending along the first direction in the light-emitting area of the first sub-pixel is different. According to the display substrate of claim 11, in the same sub-pixel group, the extending directions of the edges adjacent to the first edge in the light-emitting areas of the first sub-pixel and the light-emitting areas of the second sub-pixel all intersect with the extending direction of the first edge. The display substrate according to claim 11 or 12, wherein, in the same sub-pixel group, the first side of one of the at least two adjacent third sub-pixels is close to the first sub-pixel and the second sub-pixel in its sub-pixel group, and the first side of the other of the at least two adjacent third sub-pixels is far away from the first sub-pixel and the second sub-pixel in its sub-pixel group. According to any one of claims 11-13, the light-emitting area of the third sub-pixel further includes a second side and a third side connected to each other, the angle between the second side and the side of the light-emitting area of the first sub-pixel adjacent to it is not greater than 5 degrees, the angle between the third side and the side of the light-emitting area of the second sub-pixel adjacent to it is not greater than 5 degrees, and the first side and the second side are located on both sides of the center of the light-emitting area of the third sub-pixel in the second direction. According to claim 8, the display substrate, wherein at least a portion of the sub-pixels include a light-emitting functional layer, a first electrode, a second electrode, and a pixel circuit, wherein the first electrode is located between the light-emitting functional layer and the substrate and is electrically connected to the pixel circuit, and the second electrode is located on the side of the light-emitting functional layer away from the first electrode. In two adjacent sub-pixel groups arranged along the second direction, the first electrode of the third sub-pixel is symmetrically distributed with respect to the first dividing line. According to the display substrate of claim 15, in two adjacent sub-pixel groups arranged along the second direction, the first electrode of at least one of the first sub-pixel and the second sub-pixel is symmetrically distributed with respect to the first dividing line. According to the display substrate of claim 15 or 16, the first electrode includes a main electrode and a connecting electrode connected to each other, and the connecting electrode does not overlap with the light-emitting area of the sub-pixel in a direction perpendicular to the substrate. In the same sub-pixel group, the connection electrode of the third sub-pixel is located between its main electrode and the main electrode of the second sub-pixel, the connection electrode of the second sub-pixel is located between its main electrode and the main electrode of the first sub-pixel, and the connection electrode of the first sub-pixel is located between its main electrode and the main electrode of the third sub-pixel. According to claim 2, in the same sub-pixel group, at least two first sub-pixels and at least two second sub-pixels correspond to the same mask opening. According to claim 9, in the display substrate, in two adjacent sub-pixel groups arranged along the second direction, at least two first sub-pixels located on both sides of the first dividing line and adjacent to it are configured to correspond to the same mask opening, and at least two second sub-pixels located on both sides of the first dividing line and adjacent to it are configured to correspond to the same mask opening. A display device comprising the display substrate as described in any one of claims 1-19.