WO2025258552A1 - Semiconductor module and method for manufacturing semiconductor module - Google Patents

Abstract

This semiconductor module comprises: a first substrate including a first surface parallel to each of a first direction and a second direction intersecting the first direction; a frame body disposed on the first surface along a third direction intersecting each of the first direction and the second direction; and a first cube chip attached to the frame body, disposed on the first surface along the third direction, and including a plurality of stacked IC chips.

Description

Semiconductor module and method for manufacturing the same

One embodiment of the present invention relates to a semiconductor module and a method for manufacturing a semiconductor module.

In recent years, electronic computers used in data centers and other locations include semiconductor modules that mount multiple stacked memory chips, multiple IC (Integrated Circuit) chips including processing circuits, and multiple IC chips including image processing circuits on a single package substrate. These semiconductor modules enable electronic computers to increase memory capacity and process large volumes of data during data communications between each IC chip and each memory chip.

For example, Patent Documents 1 to 4 and Non-Patent Document 1 disclose examples of stacked chips in which multiple chips are stacked, or methods for mounting stacked chips. Patent Documents 2 and 3 also disclose technology for contactless communication between two chips. Furthermore, Patent Documents 1 to 4 and Non-Patent Documents 1 to 3 disclose technology for forming wiring on the sidewalls of stacked chips as an example of a method for mounting stacked chips.

Special Publication No. 3-501428 International Publication No. 2021/095083 International Publication No. 2021/199447 JP 2012-156478 A

A. Agnesina et al. , “A Novel 3D DRAM Memory Cube Architecture for Space Applications,” 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 2018, pp. 1-6, doi: 10.1109/DAC. 2018.8465911. R. W. Johnson, “3-D Packaging: A Technology Review,” pp. 1-70, 23 Jun 2005. https://nepp. nasa. gov/doculoads/EA7E7EA1-BD30-4DA4-BD615FEA1A7F5AE9/3D%20Packaging%20Report%20071805. pdf R. M. Lea et al. , “3-D Stacked Chip Packaging Solution for Miniat urized Massively Parallel Processing,” IEEE Trans. Adv Packag. , 22 (3), Aug 1999.

For example, the semiconductor module uses multiple through electrodes, multiple bumps, etc. to mount a stacked memory chip in which multiple memory chips are stacked, multiple IC chips including an arithmetic processing circuit, and multiple IC chips including an image processing circuit on a single package substrate.

For example, because this semiconductor module includes multiple IC chips mounted on a single package substrate, if a stacked memory chip fails, it is difficult to replace only the stacked memory chip. Furthermore, when multiple IC chips are mounted on a single package substrate, the package substrate may warp. If the package substrate warps, poor connection may occur between the multiple IC chips and the package substrate, or between the package substrate and the motherboard. This reduces the long-term reliability of the semiconductor module. Furthermore, the techniques for forming wiring on the sidewalls of stacked chips disclosed in Patent Documents 1 to 4 and Non-Patent Documents 1 to 3 include a new process for forming wiring on the sidewalls of the stacked chips. Therefore, Patent Documents 1 to 4 and Non-Patent Documents 1 to 3 increase the manufacturing costs of the semiconductor module due to the additional process. Furthermore, the techniques described in Patent Documents 2 and 3 include a new process for forming wiring for contactless communication (e.g., wireless communication, inductor communication) on the sidewalls of the stacked chips or the bottom surface of the stacked memory chips. Therefore, the techniques described in Patent Documents 2 and 3 increase the manufacturing costs due to the additional process for wireless communication.

In light of these problems, one embodiment of the present invention aims to provide a semiconductor module that can suppress a decline in long-term reliability. Furthermore, one embodiment of the present invention aims to provide a semiconductor module that can suppress manufacturing costs.

A semiconductor module according to one embodiment of the present invention includes a first substrate including a first surface parallel to a first direction and a second direction intersecting the first direction, a frame body arranged on the first surface along a third direction intersecting the first direction and the second direction, and a first cube chip attached to the frame body, arranged on the first surface along the third direction, and including a plurality of stacked IC chips.

The first substrate may include a first inductor arranged parallel to and spaced apart from the first surface, and the IC chip may include a second inductor arranged parallel to and spaced apart from the first surface, and the first inductor may communicate with the second inductor in a non-contact manner.

The IC chip may include a plurality of memory cell arrays electrically connected to the second inductor.

The frame body may include a first inclined portion, the first cube chip may include a second inclined portion, and the angle between the first surface and the first inclined portion may be the same as the angle between the first surface and the second inclined portion.

The first cube chip includes a stacked memory chip including the plurality of IC chips, a first electrode electrically connected to the stacked memory chip, and a structure, and the stacked memory chip includes at least a first outermost surface, which are the two outermost surfaces in the third direction, and a second outermost surface opposite the first outermost surface, and a third outermost surface, which are parallel to the third direction and the first direction and are the two outermost surfaces in the second direction, and a fourth outermost surface opposite the third outermost surface, and the first electrode is electrically connected to the third outermost surface, and the structure includes the second inclined portion and may be provided so as to contact the third outermost surface other than the surface to which the first electrode is connected.

The first electrode may be electrically connected to a power supply unit including a plurality of terminals to which a power supply voltage is supplied.

The first cube chip may include a second electrode electrically connected to the second outermost surface, and a ground voltage may be supplied to the second electrode.

The device may further include a heat spreader, which is electrically connected to the second electrode and supplies the ground voltage to the second electrode.

The structure may include resin or metal.

The frame body may be configured by combining a first frame body, a second frame body, a third frame body, and a fourth frame body in a rectangular shape.

The frame body may include a first L-shaped frame body, a second L-shaped frame body, a third L-shaped frame body, and a fourth L-shaped frame body spaced apart from one another and provided at the four corners of a rectangle.

The frame body may include a first L-shaped frame body and a second L-shaped frame body spaced apart from each other and located at two diagonal corners of a rectangle.

Further comprising: a second cube chip attached to the frame, disposed on the first surface, adjacent to the first cube chip, and stacked with a plurality of IC chips different from the plurality of IC chips; and a connecting member connecting the first cube chip and the second cube chip, wherein each of the first cube chip and the second cube chip has a first outermost surface and a second outermost surface opposite the first outermost surface, which are the two outermost surfaces in the third direction, and two outermost surfaces parallel to the third direction and the first direction and in the second direction. The cube chip may include a third outermost surface and a fourth outermost surface opposite the third outermost surface, which are outer surfaces, and a fifth outermost surface and a sixth outermost surface opposite the fifth outermost surface, which are two outermost surfaces parallel to the third direction and the second direction and in the first direction, and the fifth outermost surface of the first cube chip may be in contact with the sixth outermost surface of the second cube chip, and the connecting member may be in contact with at least the sixth outermost surface, the third outermost surface, and the fourth outermost surface of the first cube chip, and the third outermost surface and the fourth outermost surface of the second cube chip.

Each of the first cube chip and the second cube chip may include a first electrode in contact with the third outermost surface and a second electrode in contact with the fourth outermost surface, and the connection member may be in contact with the first electrode and the second electrode and supply a power supply voltage to the first electrode and the second electrode.

The first cube chip includes an electrode provided on a surface that is pressed against the first surface and a surface different from the surface that is pressed against the first surface, and the surface that is pressed against the first surface is disposed at a predetermined position on the first substrate via the frame, and the first cube chip is not electrically or mechanically connected to the first substrate, but may be electrically connected to an external circuit via the electrode.

One embodiment of the present invention is a method for manufacturing a semiconductor module including a first substrate including a first surface parallel to a first direction and a second direction intersecting the first direction; a frame body arranged on the first surface along a third direction intersecting the first direction and the second direction; and a cube chip including a plurality of stacked IC chips attached to the frame body and arranged on the first surface along the third direction, the manufacturing method including forming the frame body on the first surface, and rotating the cube chip to place it on the frame body and the first surface so that a first inclined portion included in the frame body and a second inclined portion included in the cube chip are fitted together.

The method may further include vibrating the first substrate to position the cube chip on the frame and the first surface.

1 is a perspective view showing a configuration of a semiconductor module according to a first embodiment of the present invention; 2 is an end view showing the cross-sectional structure of the end portion of the semiconductor module taken along line A1-A2 shown in FIG. 1; 2 is an end view showing the cross-sectional structure of the end portion of the semiconductor module taken along line B1-B2 shown in FIG. 1 is a block diagram showing a configuration of a semiconductor module according to a first embodiment of the present invention; FIG. 2 is a perspective view showing a plurality of inductors included in the cube chip and a plurality of inductors included in the first substrate according to the first embodiment of the present invention. 1 is an end view showing an enlarged view of a part of the end cross-sectional structure of an IC chip according to a first embodiment of the present invention. 1 is a block diagram showing a configuration of stacked memory chips according to a first embodiment of the present invention; 10 is a flowchart showing an example of a method for manufacturing a frame body according to a second embodiment of the present invention. FIG. 10 is a perspective view illustrating an example of a method for manufacturing a frame body according to a second embodiment of the present invention. FIG. 10 is a perspective view illustrating an example of a method for manufacturing a frame body according to a second embodiment of the present invention. FIG. 10 is a perspective view illustrating an example of a method for manufacturing a frame body according to a second embodiment of the present invention. FIG. 10 is a perspective view illustrating an example of a method for manufacturing a frame body according to a second embodiment of the present invention. FIG. 10 is a perspective view showing the configuration of a frame body according to a third embodiment of the present invention. FIG. 10 is a perspective view showing the configuration of a frame body according to a third embodiment of the present invention. FIG. 10 is an end view showing an enlarged view of a part of the end cross-sectional structure of the configuration of a semiconductor module according to a fourth embodiment of the present invention. FIG. 10 is an end view showing an enlarged view of a part of the end cross-sectional structure of the configuration of a semiconductor module according to a fourth embodiment of the present invention. 13 is a flowchart showing an example of a method for forming electrodes included in a cube chip according to a fifth embodiment of the present invention. FIG. 13 is a perspective view illustrating an example of a method for forming an electrode according to a fifth embodiment of the present invention. 13A to 13C are plan views illustrating an example of a method for forming an electrode according to a fifth embodiment of the present invention. FIG. 13 is a perspective view illustrating an example of a method for forming an electrode according to a fifth embodiment of the present invention. FIG. 13 is a perspective view illustrating an example of a method for forming an electrode according to a fifth embodiment of the present invention. 13 is a flowchart showing an example of a method for forming electrodes included in a cube chip according to a sixth embodiment of the present invention. FIG. 13 is a perspective view illustrating an example of a method for forming an electrode according to a sixth embodiment of the present invention. FIG. 13 is a plan view illustrating an example of a method for forming an electrode according to a sixth embodiment of the present invention. FIG. 13 is a perspective view illustrating an example of a method for forming an electrode according to a sixth embodiment of the present invention. 13 is a flowchart illustrating an example of a method for manufacturing a semiconductor module according to a seventh embodiment of the present invention. 13 is a flowchart illustrating an example of a method for manufacturing a semiconductor module according to a seventh embodiment of the present invention. FIG. 13 is a plan view showing an example of the configuration of a semiconductor module according to an eighth embodiment of the present invention. FIG. 13 is a plan view showing an example of the configuration of a semiconductor module according to a ninth embodiment of the present invention. 30 is an end view showing the cross-sectional structure of the end portion of the semiconductor module taken along line C1-C2 shown in FIG. 29. FIG. 22 is a plan view showing an example of the configuration of a semiconductor module according to a tenth embodiment of the present invention. 33 is an end view showing the cross-sectional structure of the end portion of the semiconductor module taken along line E1-E2 shown in FIG. 32. 20 is a flowchart illustrating an example of a method for manufacturing a semiconductor module according to a tenth embodiment of the present invention. 13A and 13B are end views for explaining an example of a method for manufacturing a semiconductor module according to a tenth embodiment of the present invention. 13A and 13B are end views for explaining an example of a method for manufacturing a semiconductor module according to a tenth embodiment of the present invention. 13A and 13B are end views for explaining an example of a method for manufacturing a semiconductor module according to a tenth embodiment of the present invention. 13A and 13B are end views for explaining an example of a method for manufacturing a semiconductor module according to a tenth embodiment of the present invention. 13A and 13B are end views for explaining an example of a method for manufacturing a semiconductor module according to a tenth embodiment of the present invention. FIG. 23 is an end view showing the cross-sectional structure of an end portion of a semiconductor module according to an eleventh embodiment of the present invention. 22 is a flowchart showing an example of a method for manufacturing a semiconductor module according to an eleventh embodiment of the present invention. 12A to 12C are end views for explaining an example of a method for manufacturing a semiconductor module according to an eleventh embodiment of the present invention. 12A to 12C are end views for explaining an example of a method for manufacturing a semiconductor module according to an eleventh embodiment of the present invention. FIG. 23 is an end view showing the cross-sectional structure of an end portion of a semiconductor module according to a twelfth embodiment of the present invention.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different forms, and should not be construed as being limited to the description of the embodiments exemplified below. To clarify the explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual form, but these are merely examples and do not limit the interpretation of the present invention. Furthermore, in this specification and each figure, elements similar to those previously described with reference to the previous figures will be given the same reference numerals (or reference numerals with a, b, etc. suffixed to the numeral), and detailed explanations may be omitted as appropriate. Furthermore, the letters "first" and "second" attached to each element are convenient labels used to distinguish between elements, and have no further meaning unless otherwise specified.

In one embodiment of the present invention, when a component or region is said to be "above (or below)" another component or region, unless otherwise specified, this includes not only the case where it is directly above (or below) the other component or region, but also the case where it is above (or below) the other component or region, i.e., the case where another component is included between the two components above (or below) the other component or region.

In one embodiment of the present invention, the first direction D1 intersects the second direction D2, and the third direction D3 intersects the first direction D1 and the second direction D2 (D1D2 plane).

In one embodiment of the present invention, when the terms "identical" and "matching" are used, the terms "identical" and "matching" may include a margin of error within the design range. Furthermore, in one embodiment of the present invention, when a margin of error within the design range is included, the terms "approximately identical" and "approximately matching" may be used.

First Embodiment
A semiconductor module 10 according to a first embodiment will be described with reference to FIGS.

<1-1. Overview of the semiconductor module 10>
First, an overview of the semiconductor module 10 will be described with reference to Figures 1 to 3. Figure 1 is a perspective view showing the configuration of the semiconductor module 10. Figure 2 is an end view showing the cross-sectional structure of the end of the semiconductor module 10 taken along line A1-A2 shown in Figure 1. Figure 3 is an end view showing the cross-sectional structure of the end of the semiconductor module 10 taken along line B1-B2 shown in Figure 1.

As shown in Figures 1 to 3, the semiconductor module 10 includes a cube chip 100, a frame 200, and a first substrate 300. The semiconductor module 10 may also include an insulating film 40 and an insulating film 210, and may also include a thermally conductive sheet 800 (see Figure 15) and a metal film 900 (see Figure 15).

Although details will be described later, the frame 200 is provided on the first surface 304 of the first substrate 300, and the cube chip 100 is provided on the first substrate 300 so as to be attachable to the frame 200 and detachable from the frame 200. Furthermore, for example, the semiconductor module 10 may be mounted on a motherboard (not shown) using a plurality of bumps (not shown). As a result, for example, if the cube chip 100 malfunctions, the cube chip 100 can be removed from the semiconductor module 10 and a cube chip 100 that is not malfunctioning can be attached. In other words, the semiconductor module 10 has a configuration that allows the cube chip 100 to be replaced.

Furthermore, as will be described in detail later, the cube chip 100 includes an IC chip 110 that includes a memory cell array 115 (see FIG. 7), and functions as a memory device. Furthermore, the cube chip 100 includes an inductor 172, and the first substrate 300 includes an inductor 372, with the inductor 172 being capable of non-contact inductive communication with the inductor 372. In other words, the cube chip 100 can transmit, receive, and store (memorize) signals (e.g., data) with the first substrate 300 using non-contact inductive communication, rather than transmitting and receiving signals via a signal path routed over a long distance using wiring, through electrodes, bumps, etc.

As a result, the semiconductor module 10 includes a configuration that allows the cube chip 100 to be attached and detached, enabling long-term use, and the manufacturing process for the semiconductor module 10 can eliminate the need for processes that involve routing wiring, through-electrodes, bumps, and the like over long distances. Therefore, the semiconductor module 10 can reduce manufacturing costs and maintain reliability without compromising long-term reliability.

<1-1-1. Configuration of cube chip 100>
1 to 3 , the cube chip 100 includes stacked memory chips 30, side power supply wiring 162 and side ground wiring 163 electrically connected to the stacked memory chips 30, and structures 50 and 50A in contact with the stacked memory chips 30. The cube chip 100 also includes a first outermost surface (first surface 146) and a second outermost surface (second surface 148) opposite the first outermost surface, which are two outermost surfaces in the third direction D3, a third outermost surface (third surface 145) and a fourth outermost surface (fourth surface 147) parallel to the third direction D3 and the first direction D1 and which are two outermost surfaces in the second direction D2, and a fifth outermost surface (fifth surface 142) and a sixth outermost surface (sixth surface 144) parallel to the third direction D3 and the second direction D2 and which are two outermost surfaces in the first direction D1.

The stacked memory chip 30 includes multiple IC chips 110, each including multiple power supply wiring 164, multiple ground wiring 165, multiple signal transmission wiring 166 (see Figure 7), and multiple inductors 172.

The stacked memory chip 30 also includes a first outermost surface (first surface 46) and a second outermost surface (second surface 48) opposite the first outermost surface, which are the two outermost surfaces in the third direction D3; a third outermost surface (third surface 45) and a fourth outermost surface (fourth surface 47) parallel to the third direction D3 and the first direction D1, which are the two outermost surfaces in the second direction D2; and a fifth outermost surface (fifth surface 42) and a sixth outermost surface (sixth surface 44) parallel to the third direction D3 and the second direction D2, which are the two outermost surfaces in the first direction D1.

2 or 3, the first surface 46, second surface 48, third surface 45, fourth surface 47, fifth surface 42, and sixth surface 44 of the stacked memory chip 30 are parallel to the first surface 146, second surface 148, third surface 145, fourth surface 147, fifth surface 142, and sixth surface 144 of the cube chip 100. For example, the first surface 46 is parallel to the first surface 146, and the second surface 48 is parallel to the second surface 148. The third surfaces 45 to 44 and the third surfaces 145 to 144 are also parallel to their corresponding surfaces, as are the first surface 46 and the first surface 146, and the second surface 48 and the second surface 148. A portion of the first surface 146 is the first surface 46. For example, the first surfaces 146 other than the first surfaces 146 that contact the structure 50A are the first surfaces 46.

Details will be provided later, but for example, the multiple IC chips 110 include IC chip 110n (see Figure 5) and IC chip 110n+1 (see Figure 5) arranged adjacent to IC chip 110n. When the multiple IC chips 110 are not distinguished from one another, the IC chips are expressed as IC chip 110. When the multiple IC chips 110 are distinguished from one another, the IC chips are expressed as IC chip 110n, IC chip 110n+1, etc.

As shown in FIG. 2, the multiple power supply wirings 164 are exposed on the third surface 45 and the fourth surface 47 and are electrically connected to the side surface power supply wirings 162. The multiple ground wirings 165 are exposed on the second surface 48 and are electrically connected to the side surface ground wirings 163. The multiple inductors 172 are arranged parallel to the first surface 46 for each IC chip and spaced apart from the first surface 46, and are arranged side by side in the second direction D2 for each IC chip. Note that the inductors 172 may be arranged across multiple IC chips.

2, the side power supply wiring 162 contacts the third surface 45 and the fourth surface 47 and is provided on the third surface 45 and the fourth surface 47. The side power supply wiring 162 also contacts the third surface 145 and the fourth surface 147. The side ground wiring 163 contacts the second surface 48 and is provided on the second surface 48. The side ground wiring 163 also contacts the second surface 148. The side power supply wiring 162 has the function of supplying a power supply voltage to multiple power supply wirings 164, and the side ground wiring 163 has the function of supplying a ground voltage to multiple ground wirings 165. For example, the power supply voltage is voltage VDD and the ground voltage is voltage VSS. For example, voltage VDD is a power supply voltage such as 1V or 3V, and voltage VSS is 0V, for example. For example, the side power supply wiring 162 and the side ground wiring 163 are not electrically connected to the first substrate 300 but are electrically connected to an external device (not shown). That is, the power supply voltage and ground voltage are supplied to the cube chip 100 via the side power supply wiring 162 and side ground wiring 163 that are independent of the first substrate 300, without passing through the first substrate 300.

The structure 50 is provided in contact with a portion of the third surface 45 other than the third surface 45 to which the side surface power supply wiring 162 contacts, is provided in contact with a portion of the fourth surface 47 other than the fourth surface 47 to which the side surface power supply wiring 162 contacts, and is provided in contact with portions of the fifth surface 42 and the sixth surface 44. The structure 50 is also provided in contact with a second surface 48 other than the second surface 48 to which the side surface ground wiring 163 contacts. For example, as shown in Figures 2 and 3, the structure 50 is provided to cover the corner where the second surface 48, the third surface 45, and the fifth surface 42 contact, a portion of the fifth surface 42, and the corner where the second surface 48, the fifth surface 42, and the fourth surface 47 contact. Although not shown, the structure 50 is arranged to cover the corner where the fourth surface 47 and the sixth surface 44 meet, a portion of the sixth surface 44, and the corner where the second surface 48, the sixth surface 44, and the third surface 45 meet.

For example, as shown in FIG. 2 or 3, the structure 50A includes a second inclined portion 51, and is provided in contact with the third surface 45 other than the third surface 45 with which the side power supply wiring 162 covered by the structure 50 is in contact, and is provided in contact with the fourth surface 47 other than the fourth surface 47 with which the side power supply wiring 162 covered by the structure 50 is in contact, and is provided in contact with the fifth surface 42 and the sixth surface 44 other than the portions of the fifth surface 42 and the sixth surface 44 covered by the structure 50.

For example, in the end view shown in Figure 2, structures 50 and 50A are spaced apart, but structures 50 and 50A are in contact on the third surface 145 side in the second direction D2 (not shown). Also, in the end view shown in Figure 3, structure 50 is in contact with third surface 145 and fourth surface 147, and is uniformly provided on third surface 145 and fourth surface 147.

The structures 50 and 50A cover and contact the surfaces of the stacked memory chip 30 that do not have side wiring (e.g., side ground wiring 163 and side power supply wiring 162). For example, the structures 50 and 50A include a sealing material. For example, the sealing material includes a resin material such as epoxy, a hardener, a filler, and additives. The structures 50 and 50A function to suppress moisture absorption and the intrusion of impurities into the stacked memory chip 30, as well as to protect against physical impact. Furthermore, the structure 50A is fitted into the frame body 200 and functions as a member for fixing the cube chip 100 to the frame body 200 and the first substrate 300. The structure 50A may also include metal.

The cube chip 100 is fitted into the frame 200 and is provided on the first surface 304 of the first substrate 300. The cube chip 100 is fitted into the frame 200 so that the second inclined portion 51 is parallel to the first inclined portion 41 of the frame 200. The angle between the first surface 304 and the second inclined portion 51 is angle α.

For example, the angle α is designed so that the length (width) of the first surface 146 along the first direction D1 is the length of the first surface 146 ±2 μm. Both ends of the length of the first surface 146 correspond to the ends of the second inclined portion 51, and the angle α at one end of the second inclined portion 51 is designed so that the length of the first surface 146 is ±1 μm. In other words, for example, the positional accuracy of the cube chip 100 may be expressed as ±2 μm with respect to the length (width) of the frame body 200 along the first direction D1, or as ±1 μm with respect to one end of the length (width) of the frame body 200.

<1-1-2. Configuration of frame body 200>
As shown in FIG. 1 , FIG. 2 or FIG. 3 , the frame 200 includes a first inclined portion 41 , and is in contact with and provided on the first surface 304 of the first substrate 300 .

For example, in the end view shown in Figures 2 and 3, the shape of the frame body 200 is trapezoidal, and the length of the side tangent to the first surface 304 is longer than the side opposite the first surface 304 in the third direction D3. The angle α between the first surface 304 and the first inclined portion 41 is the same as the angle α between the first surface 304 and the second inclined portion 51. The first inclined portion 41 and the second inclined portion 51 may be configured to interlock with each other. For example, the first inclined portion 41 may include a structure that is recessed more upward than downward along the third direction D3, and the second inclined portion 51 may include a structure that is recessed more downward than upward along the third direction D3, and the first inclined portion 41 may be configured to interlock with the second inclined portion 51.

The frame body 200 has the function of fitting the cube chip 100 and fixing the cube chip 100 onto the first substrate 300. For example, the frame body 200 may be configured to allow an IC chip to be attached and detached, similar to an IC socket. In other words, the frame body 200 is configured to allow the cube chip 100 to be attached and to allow the cube chip 100 to be detached.

<1-1-3. Configuration of first substrate 300>
As shown in FIG. 2 or 3 , the first substrate 300 includes at least a plurality of inductors 372, a control circuit (see, for example, FIG. 4 ) capable of controlling the plurality of inductors 372, and a multilayer wiring structure in which wiring and insulating layers are alternately stacked. For example, the first substrate 300 includes a first surface 304, a second surface 302, and a plurality of wiring layers 326, 328, 330, 332, and 334. The wiring layers 326, 328, 330, 332, and 334 are arranged parallel to the first direction D1 and the second direction D2, and are stacked in this order from the side closest to the first surface 304 along the third direction D3. The plurality of wiring layers 326 includes a wiring 327 and an inductor 372. The plurality of wiring layers 328, 330, 332, and 334 include a plurality of wirings 329, a plurality of wirings 331, a plurality of wirings 333, and a plurality of wirings 335. The wiring 327 and the inductor 372 are electrically connected to the wiring 329, the wiring 329 is electrically connected to the wiring 331, the wiring 331 is electrically connected to the wiring 333, and the wiring 333 is electrically connected to the wiring 335. In FIG. 1 , the insulating layers alternately stacked with the wiring are not shown.

Furthermore, the number of layers in the multilayer wiring structure of the first substrate 300 is not limited to the number of layers (five layers) shown in Figures 2 and 3. The number of layers in the multilayer wiring structure of the first substrate 300 can be changed as appropriate based on the application or specifications of the semiconductor module 10, etc.

Furthermore, for example, the wiring 335 may be exposed on the second surface 302 and function as an electrode. The wiring 335 of the semiconductor module 10 may be electrically connected to a motherboard (not shown) by a bump (not shown) or the like. For example, the motherboard may be a substrate on which the semiconductor module 10, a CPU (Central Processing Unit) including multiple arithmetic circuits and capable of arithmetic processing, and a GPU (Graphics Processing Unit) including multiple arithmetic circuits and capable of image processing or video processing are mounted. The semiconductor module 10 may include a CPU including multiple arithmetic circuits and capable of arithmetic processing, or a GPU including multiple arithmetic circuits and capable of image processing or video processing.

The first substrate 300 has the function of fixing and supporting the frame body 200 and the cube chip 100, and the function of communicating with the cube chip 100 via inductor. The first substrate 300 may also have the function of connecting the cube chip 100 to an external device, etc.

<1-1-4. Other configurations>
As explained in "1-1. Overview of the Semiconductor Module 10," the semiconductor module 10 may include an insulating film 40 and an insulating film 210 as shown in FIG. 2 or FIG.

For example, the insulating film 40 is provided so as to contact the first surface 146. For example, the first surface 146 is an important surface for the cube chip 100 to perform inductive communication with the first substrate 300, and the insulating film 40 has the function of coating the first surface 146 and protecting the first surface 146. The insulating film 40 also has the function of preventing the cube chip 100 from contacting the first substrate 300 and insulating the cube chip 100 from the first substrate 300. The insulating film 40 may be provided so as to contact the second inclined portion 51.

For example, the insulating film 210 contacts the first inclined portion 41, the first surface 304, the second inclined portion 51, and the insulating film 40, and is provided between the first inclined portion 41 and the first surface 304 and the second inclined portion 51 and the insulating film 40. The insulating film 210 prevents the cube chip 100 from contacting the first substrate 300, and functions to insulate the cube chip 100 from the first substrate 300.

For example, the insulating film 40 and the insulating film 210 may be made of resin, which may be a fluororesin such as Teflon (registered trademark).

The semiconductor module 10 shown in Figures 2 and 3 includes, as an example, both the insulating film 40 and the insulating film 210. The cube chip 100 and the first substrate 300 only need to be insulated from each other and have a configuration that allows them to be attached and detached from each other, and the semiconductor module 10 may include either the insulating film 40 or the insulating film 210.

Furthermore, as explained in "1-1. Overview of Semiconductor Module 10," the semiconductor module 10 may include a thermally conductive sheet 800 (see FIG. 15) and a metal film 900 (see FIG. 15). The thermally conductive sheet 800 or the metal film 900 may function as a heat spreader, or may be a heat spreader itself. For example, the thermally conductive sheet 800 and the metal film 900 have the function of releasing heat generated by the semiconductor module 10 to the outside of the semiconductor module 10.

<1-2. Functional Block Configuration of Semiconductor Module 10>
Next, the functional block configuration of the semiconductor module 10 will be described with reference to Figures 2 to 4. Figure 4 is a block diagram showing the functional block configuration of the semiconductor module 10. Configurations that are the same as or similar to those in Figures 1 to 3 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figures 1 to 3 may be omitted.

As shown in Figures 2, 3, and 4, the semiconductor module 10 includes a cube chip 100 and a first substrate 300.

The cube chip 100 includes multiple magnetically coupled chip-to-chip interfaces (Through Chip Interface-IO (TCI-IO)) 112 and multiple memory modules 111. The multiple TCI-IOs 112 are electrically connected to the memory modules 111. For example, the cube chip 100 (stacked memory chip 30) includes a function for storing received data and a function for transmitting stored data.

The TCI-IO 112 includes an inductor 172 (second inductor), a transmitting/receiving circuit 114, and a parallel-serial conversion circuit 113. The inductor 172 is electrically connected to the transmitting/receiving circuit 114 using terminals A and B. The transmitting/receiving circuit 114 is electrically connected to the parallel-serial conversion circuit 113. The parallel-serial conversion circuit 113 is electrically connected to the memory module 111.

Inductor 172 has the function of performing non-contact inductor communication with inductor 372 (first inductor) on the first substrate 300.

For example, the transmitter/receiver circuit 114 has the function of amplifying signals (e.g., control signals and data signals) received by the inductor 172, and the function of removing noise from the received signals (e.g., control signals and data signals). Furthermore, for example, the transmitter/receiver circuit 114 has the function of transmitting desired signals (e.g., control signals and data signals) converted using the parallel-to-serial conversion circuit 113 over radio waves. The signals received by the inductor 172 include a large number of parallel signals (parallel signals) from the first board 300. The desired signals include a large number of parallel signals (parallel signals) from the memory module 111.

For example, in step 1, the parallel-serial conversion circuit 113 converts a large number of parallel signals from the first board 300 into serial signals (serial signals) by parallel-serial conversion. The serial signals are transferred at high speed using a single signal path (wiring). In step 2, the parallel-serial conversion circuit 113 converts the serial signals into parallel signals just before the memory module 111, returning them to a large number of parallel signals, and then transmits the large number of parallel signals to the memory module 111. For example, when transmitting signals (e.g., control signals and data signals) from the memory module 111 to the first board 300, the parallel-serial conversion circuit 113 performs step 2 followed by step 1. The parallel-serial conversion circuit 113 is called, for example, a SerDes circuit (Serialize and Deserialize Circuit).

For example, memory module 111 includes the functionality of generating a large number of parallel signals to be transmitted, and the functionality of controlling a large number of parallel signals received and storing them in memory cell array 115 (see Figure 7).

The first board 300 includes multiple TCI-IOs 312 and multiple TCI-IO control modules 311. The multiple TCI-IOs 312 are electrically connected to the multiple TCI-IO control modules 311.

The TCI-IO 312 includes an inductor 372, a transmitting/receiving circuit 314, and a parallel-to-serial conversion circuit 313. The inductor 372 is electrically connected to the transmitting/receiving circuit 314 using terminals C and D. The transmitting/receiving circuit 314 is electrically connected to the parallel-to-serial conversion circuit 313. For example, the parallel-to-serial conversion circuit 313 is electrically connected to the TCI-IO control module 311.

The configurations and functions of the inductor 372, the transmitter/receiver circuit 314, and the parallel-serial conversion circuit 313 are similar to the configurations and functions of the inductor 172, the transmitter/receiver circuit 114, and the parallel-serial conversion circuit 113.

For example, the TCI-IO control module 311 may include a CPU or GPU. For example, the TCI-IO control module 311 may have the function of reading a control program stored in a DRAM (Dynamic Random Access Memory) (not shown) included in an external device, expanding the control program, executing processing based on the control program, and sending instructions (commands) to each IC chip 110 to execute processing based on the control program.

<1-3. Overview of inductor communication>
Next, an overview of inductor communication will be described with reference to Fig. 5. Fig. 5 is a perspective view showing a plurality of inductors 172 included in the cube chip 100 and a plurality of inductors 372 included in the first substrate 300, and is a perspective view showing the configurations of the inductors 172 and 272. Configurations that are the same as or similar to those in Figs. 1 to 4 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figs. 1 to 4 may be omitted.

As explained in "1-1-1. Configuration of the cube chip 100," the cube chip 100 includes a plurality of inductors 172 arranged parallel to the third surface 145, which is parallel to the second direction D2 and the third direction D3, and spaced apart from the first surface 146 and the third surface 145. The multiple inductors 172 are arranged along the second direction D2.

Each of the multiple inductors 172 includes terminal A, terminal B, a first portion 172a, a second portion 172b, a third portion 172c, a fourth portion 172e, and a fifth portion 172d.

The fifth portion 172d extends in the second direction D2, and one end of the fifth portion 172d is electrically connected to terminal A, and the other end of the fifth portion 172d is electrically connected to one end of the fourth portion 172e. The fourth portion 172e extends in the third direction D3, and the other end of the fourth portion 172e is electrically connected to one end of the first portion 172a. The first portion 172a extends in the second direction D2, and the other end of the first portion 172a is electrically connected to one end of the second portion 172b. The second portion 172b extends in the third direction D3, and the other end of the second portion 172b is electrically connected to one end of the third portion 172c. The third portion 172c extends in the second direction D2, and the other end of the third portion 172c is electrically connected to terminal B.

The first substrate 300 includes a plurality of inductors 372 that are parallel to the positions where the plurality of inductors 172 are arranged, parallel to the first surface 304 of the first substrate 300, and spaced apart from the first surface 304. The plurality of inductors 372 are arranged in a matrix along the first direction D1 and the second direction D2. Each of the plurality of inductors 372 includes a terminal C, a terminal D, a first portion 372a, a second portion 372b, a third portion 372c, a fourth portion 372e, and a fifth portion 372d.

The fifth portion 372d extends in the second direction D2, and one end of the fifth portion 372d is electrically connected to terminal C, and the other end of the fifth portion 372d is electrically connected to one end of the fourth portion 372e. The fourth portion 372e extends in the first direction D1, and the other end of the fourth portion 372e is electrically connected to one end of the first portion 372a. The first portion 372a extends in the second direction D2, and the other end of the first portion 372a is electrically connected to one end of the second portion 372b. The second portion 372b extends in the first direction D1, and the other end of the second portion 372b is electrically connected to one end of the third portion 372c. The third portion 372c extends in the second direction D2, and the other end of the third portion 372c is electrically connected to terminal D.

Because IC chips 110n and 110n+1 are standing perpendicular to the first substrate 300, inductor 172 is arranged opposite inductor 372 at a 90-degree angle. When viewed from the third direction D3 on a surface parallel to the first direction D1 and the second direction D2, first portion 172a of inductor 172 and first portion 372a of inductor 372 overlap and are arranged parallel and opposite to each other. Magnetic field coupling between one inductor 172 and one inductor 372 facing each other among the multiple inductors 172 and multiple inductors 372 enables one-to-one, non-contact communication between the inductors. For example, communication between inductors due to magnetic field coupling is called inductor communication, signal communication, data communication, etc. The shapes of inductors 172 and 372 are not limited to the rectangular shapes shown in FIG. 5 and may be any shape that allows inductor communication.

For example, inductor 172 and inductor 372 are arranged opposite each other at 90 degrees, and are capable of one-to-one communication through magnetic field coupling. In the example shown in FIG. 5, a magnetic field is generated by first portion 172a of inductor 172 and first portion 272a of inductor 372. More specifically, effective inductor communication is performed by first portion 172a of inductor 172 and first portion 372a of inductor 372. First portion 172a mainly functions to perform inductor communication with first portion 372a. Second portion 172b, third portion 172c, fourth portion 172e, and fifth portion 172d of inductor 172, excluding first portion 172a, mainly function to supply current to first portion 172a. Similar to inductor 172, the second portion 372b, third portion 372c, fourth portion 372e, and fifth portion 372d of inductor 372, excluding first portion 372a, mainly function to supply current to first portion 372a. Note that the magnetic field shown in FIG. 5 is an example, and the magnetic field that is actually generated is not limited to the magnetic field shown in FIG. 5.

Inductor 372 has the same configuration and function as inductor 172. Note that in semiconductor module 10, viewing a surface parallel to second direction D2 and third direction D3 from first direction D1 may be referred to as a front view, and viewing a surface parallel to first direction D1 and second direction D3 from third direction D3 may be referred to as a plan view.

Furthermore, when the inductor 172 is provided across multiple IC chips 110, the first portion 172a, second portion 172b, third portion 172c, fourth portion 172e, and fifth portion 172d of the inductor 172 are provided so as to face and be parallel to the first portion 372a, second portion 372b, third portion 372c, fourth portion 372e, and fifth portion 372d of the inductor 372.

As explained above, the cube chip 100 can transmit and receive signals to and from the first substrate 300 using non-contact inductor communication, rather than transmitting and receiving signals via signal paths routed long distances using wiring, through-electrodes, bumps, etc.

As a result, the manufacturing process for semiconductor module 10 can reduce the need for long-distance wiring by using wiring, through electrodes, bumps, etc., thereby reducing manufacturing costs and preventing a decrease in manufacturing yield. Furthermore, semiconductor module 10 can reduce the need for long-distance wiring by using wiring, through electrodes, bumps, etc., thereby reducing the resistance and parasitic capacitance caused by wiring. As a result, inductor communication using semiconductor module 10 can reduce the power consumption of semiconductor module 10.

<1-4. Overview of IC chip 110>
Next, an overview of the IC chip 110 will be described with reference to Fig. 6. Fig. 6 is an end view showing an enlarged portion of the end cross-sectional structure of the IC chip 110. Configurations that are the same as or similar to those in Figs. 1 to 5 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figs. 1 to 5 may be omitted.

As shown in FIG. 6, the IC chip 110 includes a first surface 102 parallel to the second direction D2 and the third direction D3, a second surface 104 opposite the first surface 102 in the first direction D1, a transistor layer 130, and a wiring layer 150. The first surface 102 is the surface opposite the surface on which the wiring layer 150 is arranged relative to the transistor layer 130, and the second surface 104 is the surface opposite the surface on which the wiring layer 150 is arranged relative to the transistor layer 130.

For example, the transistor layer 130 includes a semiconductor substrate 173, an isolation region 174, an activation region 175, a transistor 176, an insulating layer 177, and part of the wiring 178. For example, the semiconductor substrate 173 is a Si substrate or Si-wafer, and is called a semiconductor substrate. Note that a through electrode (not shown) that penetrates the semiconductor substrate 173 and the isolation region 174 may be provided.

For example, the wiring layer 150 includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked. For example, the wiring layer 150 includes a portion of the wiring 178, insulating layer 179, the wiring 180, insulating layer 181, insulating layer 182, and the wiring 183. The wiring 183 may be a through electrode.

For example, wiring 178 penetrates insulating layer 177 and is electrically connected to the source or drain of transistor 176. For example, wiring 180 penetrates insulating layer 179 and is electrically connected to wiring 178. For example, wiring 183 is electrically connected to wiring 180. Also, for example, inductor 172 is formed using wiring 183, and transceiver circuit 114, parallel-serial conversion circuit 113, and memory module 111 are formed using wiring 178, wiring 180, wiring 183, and transistor 176. The connections of each wiring shown in FIG. 6 are merely examples, and the connections of each wiring are not limited to the configuration shown in FIG. 6. The connections of each wiring can be changed as appropriate based on the application or specifications of semiconductor module 10.

Furthermore, for example, the first substrate 300 may have a configuration similar to that of the IC chip 110. For example, the first surface 304 and the second surface 302 may correspond to the first surface 102 and the second surface 104, the wiring 327 to the wiring 335 may correspond to the wiring layer 150, and the configuration between the wiring 335 and the second surface 302 may correspond to the transistor layer 130. Furthermore, the first substrate 300 may include a through electrode (not shown) that penetrates the transistor layer 130, and the through electrode may be electrically connected to the wiring 335, electrically connecting the semiconductor module 10 to an external device.

<1-5. Functional Block Configuration of Stacked Memory Chip 30>
Next, the functional block configuration of the stacked memory chip 30 will be described with reference to Fig. 7. Fig. 7 is a block diagram showing the functional block configuration of the stacked memory chip 30. Configurations that are the same as or similar to those in Figs. 1 to 6 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figs. 1 to 6 may be omitted.

The stacked memory chip 30 includes multiple memory modules 111. Each of the multiple memory modules 111 includes a memory cell array 115.

For example, each of the multiple memory modules 111 has the function of storing data contained in a received signal in the memory cell array 115, and the function of reading data from the memory cell array 115 and transmitting a signal containing that data. The multiple memory modules 111 are electrically connected to multiple power supply wiring 164, multiple ground wiring 165, and multiple signal transmission wiring 166.

The multiple power supply wiring 164 and the multiple ground wiring 165 include the configuration described in "1-1-1. Configuration of the cube chip 100," and detailed description here will be omitted.

For example, the multiple signal transmission wiring 166 is electrically connected to the TCI-IO 112. The multiple signal transmission wiring 166 is connected to the first substrate 300 and an external circuit (not shown) via inductor communication, and receives control signals such as address signals and enable signals for controlling the IC chip 110, as well as signals including data, from the first substrate 300 and the external circuit.

The memory cell array 115 includes a plurality of memory cells (not shown). Each of the plurality of memory cell arrays 115 is, for example, an SRAM (Static Random Access Memory), and each of the plurality of memory cells is an SRAM cell. The SRAM, SRAM cells, and SRAM memory module 111 can employ technology used in the SRAM technical field. Therefore, a detailed description will be omitted here. Note that the plurality of memory cell arrays 115 and the plurality of memory cells may be memory cell arrays and memory cells other than SRAM.

Second Embodiment
A method for manufacturing the frame body 200 according to the second embodiment will be described with reference to Figures 8 to 12. Figure 8 is a flowchart showing an example of a method for manufacturing the frame body 200. Figures 9 to 12 are perspective views for explaining an example of a method for manufacturing the frame body 200. Configurations that are the same as or similar to those in Figures 1 to 7 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figures 1 to 7 may be omitted.

As shown in Figure 8, the manufacturing method for the frame body 200 includes steps 11 (S11) to 19 (S19).

When the manufacturing method for the frame body 200 begins, a frame mold 400 is temporarily fixed to the first substrate 300 (S11 shown in Figure 8). Specifically, as shown in Figure 9, the first substrate 300 is prepared, and the frame mold 400 is temporarily fixed onto the first surface 304 of the first substrate 300. The frame mold 400 is a mold for forming the frame body 200. The frame mold 400 may be configured to be attachable to and detachable from the first substrate 300 after the frame body 200 has been formed. For example, the frame mold 400 may be formed from resin or metal.

Step 13 (S13) shown in FIG. 8 is a step of temporarily fixing the cube chip 100 to the frame mold 400. Specifically, as shown in FIG. 10, the cube chip 100 is aligned inside the frame mold 400 and removably fixed on the first surface 304. At this time, the first surface 146 of the cube chip 100 is removably fixed on the first surface 304 so as to face the first surface 304. The structure that allows for attachment and detachment on the first surface 304 may be an adhesive film, adhesive layer, or the like that can attach and detach the cube chip 100 and the first substrate 300. For example, the cube chip 100 is removably fixed on the first surface 304 so as to face the first surface 304 using a low-adhesion member.

Step 15 (S15) shown in Figure 8 is a step of applying resin to form the frame body 200. Specifically, as shown in Figure 11, resin to form the frame body 200 is applied between the cube chip 100 and the frame mold 400. For example, the resin is applied using a dispensing device. For example, the resin is a UV (Ultra Violet) curable resin. Note that the resin is not limited to UV curable resin, and any resin that can be provided on the first substrate 300 as the frame body 200 and can fix the cube chip 100 can be used.

Step 17 (S17) shown in Figure 8 is a step of hardening the resin applied in S15 to form the frame body 200. For example, if the resin used to form the frame body 200 is a UV-curable resin, the resin is hardened using UV.

Step 19 (S19) shown in FIG. 8 is a step of removing the cube chip 100 and frame mold 400 from the first substrate 300. Specifically, as shown in FIG. 12, the cube chip 100 and frame mold 400 are removed from the first substrate 300, and the frame body 200 is formed on the first substrate 300. The frame body 200 is configured by combining a first frame body 200L, a second frame body 200U, a third frame body 200R, and a fourth frame body 200D in a rectangular or square shape.

As described above, the frame body 200 is formed.

Third Embodiment
The configuration of the frame body according to the third embodiment will be described with reference to Figures 13 and 14. Figure 13 is a perspective view showing the configuration of frame body 202. Figure 14 is a perspective view showing the configuration of frame body 204. Configurations that are the same as or similar to those in Figures 1 to 12 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figures 1 to 12 may be omitted.

As shown in Figure 13, the frame body 202 includes a first L-shaped frame body 202LD, a second L-shaped frame body 202LU, a third L-shaped frame body 202RU, and a fourth L-shaped frame body 202RD. The first L-shaped frame body 202LD, the second L-shaped frame body 202LU, the third L-shaped frame body 202RU, and the fourth L-shaped frame body 202RD are spaced apart from each other and arranged on the first substrate 300 at the four corners of a rectangle. For example, the first L-shaped frame body 202LD and the third L-shaped frame body 202RU are provided at two diagonal corners on one side of a rectangle, and the second L-shaped frame body 202LU and the fourth L-shaped frame body 202RD are provided at two diagonal corners on the other side of the same rectangle where the first L-shaped frame body 202LD and the third L-shaped frame body 202RU are provided.

13 does not include part of each side of the rectangular frame body 200 shown in FIG. 12. Therefore, the amount of material forming the frame body 202 is less than the amount of material forming the frame body 200. For example, the frame body 202 is a frame body that can reduce manufacturing costs. Furthermore, the frame body 202, which is formed with a small amount of material, can fit around the four corners of the cube chip 100 and fix it to the first substrate 300 using the first L-shaped frame body 202LD, second L-shaped frame body 202LU, third L-shaped frame body 202RU, and fourth L-shaped frame body 202RD. Therefore, the frame body 202, like the frame body 200, can compensate for positional deviation of the cube chip 100 in the second direction D2 and the first direction D1.

As shown in FIG. 14, the frame 204 includes a first L-shaped frame 204LD and a second L-shaped frame 204RU. The first L-shaped frame 204LD and the second L-shaped frame 204RU are spaced apart from each other and are provided on the first substrate 300 at two corners of a rectangle.

14 does not include an L-shaped member located at one of the diagonal corners of the rectangular frame 202 shown in FIG. 13. Therefore, the amount of material forming the frame 204 is less than the amount of material forming the frame 202. For example, the frame 204 is a frame that can further reduce manufacturing costs. Furthermore, the frame 204 formed with a small amount of material can fit around the two diagonal corners of the cube chip 100 using the first L-shaped frame 204LD and the second L-shaped frame 204RU, and can be fixed to the first substrate 300. Therefore, like the frame 200 and the frame 202, the frame 204 can compensate for positional deviations of the cube chip 100 in the second direction D2 and the first direction D1.

Fourth Embodiment
The configuration of a semiconductor module 10A according to the fourth embodiment will be described with reference to FIGS. 15 and 16. FIG. 15 is an end view showing an enlarged portion of the cross-sectional structure of the end portion of the configuration of the semiconductor module 10A. FIG. 16 is an end view showing an enlarged portion of the cross-sectional structure of the end portion of the semiconductor module 10A after deformation. Configurations that are the same as or similar to those in FIGS. 1 to 14 will be described as necessary, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 14 may be omitted.

The semiconductor module 10A differs from the semiconductor module 10 in the following configuration (1).
(1) The semiconductor module 10A includes a plurality of cube chips (e.g., cube chips 100A and 100B), a plurality of frames (e.g., frames 200A and 200B) to which the plurality of cube chips can be attached and detached, a plurality of inductors 372 corresponding to each of the plurality of cube chips, a power supply unit 700, a heat conduction sheet 800, and a metal film 900.

The configuration of semiconductor module 10A other than that shown in (1) is the same as that of semiconductor module 10. Therefore, differences from semiconductor module 10 will be mainly described here.

For example, the configuration of each of the cube chips 100A and 100B is the same as the configuration of the cube chip 100, the configuration of each of the frame bodies 200A and 200B is the same as the configuration of the frame body 200, and the configuration of each of the multiple inductors 372 corresponding to each of the multiple cube chips is the same as the configuration of the inductors 372 in the semiconductor module 10. Furthermore, the configuration of the second substrate 300A is the same as that of the first substrate 300, except for the configuration indicated by (1) in the semiconductor module 10A. Reference numerals for identical components have been omitted, and configurations similar to those in the semiconductor module 10 will be explained as necessary. Furthermore, the insulating films 40 and 210 have been omitted.

Cube chip 100A is removably fitted to frame 200A and is provided on second substrate 300A (first surface 304A). Cube chip 100B is removably fitted to frame 200B and is provided on second substrate 300A (first surface 304A).

The power supply unit 700 includes a support unit 701 that includes a plurality of pogo pins 702. The support unit 701 has the function of supporting the plurality of pogo pins 702. For example, each of the plurality of pogo pins 702 is a connector composed of a terminal portion, a tubular member connected to the terminal portion, an elastic member inserted into the tubular member, and the like. The power supply unit 700 is sometimes called a pogo pin crimping mechanism.

For example, each of the multiple pogo pins 702 is pressed against a metal film or the like and comes into contact with the metal film. At this time, each of the multiple pogo pins 702 comes into contact with the metal film due to the expansion and contraction of the elastic member.

A power supply unit 700 is provided between the fourth surface 147 of cube chip 100A and the third surface 145 of cube chip 100B, and on the third surface 145 of cube chip 100A and the fourth surface 147 of cube chip 100B. The power supply unit 700 electrically connects the side power supply wiring 162 of cube chips 100A and 100B by crimping a plurality of pogo pins 702 to each of the side power supply wiring 162 of cube chips 100A and 100B. As a result, the power supply unit 700 can supply a power supply voltage VDD to the cube chips 100A and 100B from an external device (external circuit) outside the semiconductor module 10A via the plurality of pogo pins 702.

The metal film 900 is provided so as to contact the second surfaces 148 of the cube chips 100A and 100B. As a result, the metal film 900 is electrically connected to the side surface ground wiring 163 of each of the cube chips 100A and 100B. The thermally conductive sheet 800 is electrically connected to the metal film 900, which is electrically connected to the cube chips 100A and 100B. As a result, the thermally conductive sheet 800 can supply a ground voltage to the cube chips 100A and 100B from an external device outside the semiconductor module 10A via the metal film 900.

The thermally conductive sheet 800 and metal film 900 have the functions of supplying voltage to the cube chips 100A and 100B, and dissipating heat generated by the semiconductor module 10A to the outside of the semiconductor module 10. A heat sink may be disposed on the thermally conductive sheet 800 and metal film 900.

For example, if the second substrate 300A, cube chip 100A, or cube chip 100B generates heat due to operation of the second substrate 300A, cube chip 100A, or cube chip 100B, the substrate or chip may become warped, potentially causing the circuits to malfunction.

On the other hand, as shown in Figure 16, assume that the second substrate 300A of the semiconductor module 10A warps by a length BE along the third direction D3 due to heat from crimping or heat generated by each substrate or chip. The cube chip 100A or cube chip 100B is in contact with and fixed to the second substrate 300A, but is not bonded.

Even if the second substrate 300A warps, the cube chip 100A or cube chip 100B will only be slightly displaced from the position where it was originally attached to the second substrate 300A in accordance with the warping of the second substrate 300A, and the cube chip 100A or cube chip 100B will not be detached from the frame 200A or frame 200B.

Furthermore, each of the multiple pogo pins 702 maintains an electrical connection to the cube chip 100A or cube chip 100B due to the expansion and contraction of the elastic member. In other words, the power supply to the cube chip 100A or cube chip 100B is maintained.

Furthermore, there is only a slight misalignment between the multiple inductors 172 and the multiple inductors 372, and inductor communication between the multiple inductors 172 and the multiple inductors 372 is also possible.

As a result, the semiconductor module 10A can dissipate heat or generated heat to the outside of the semiconductor module 10A, preventing malfunctions caused by heat or generated heat, and reducing the effects of deformation of the semiconductor module 10A's structure. As a result, the semiconductor module 10A has excellent long-term reliability.

Fifth Embodiment
A method for forming electrodes included in a cube chip 100 according to the fifth embodiment will be described with reference to FIGS. 17 to 21. FIG. 17 is a flowchart showing an example of a method for forming electrodes included in a cube chip 100. FIGS. 18 to 21 are perspective views for explaining an example of a method for forming electrodes. Configurations that are the same as or similar to those in FIGS. 1 to 16 will be described as necessary, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 16 may be omitted.

As shown in Figure 17, the method for forming the electrodes included in the cube chip 100 includes steps 21 (S21) to 25 (S25).

When the method for forming the electrodes included in the cube chip 100 begins, multiple IC chips 110 are stacked (S21 shown in Figure 17). For example, as shown in Figure 18, eight IC chips 110 (eight layers, eight sheets) are stacked to form a stacked memory chip 30.

Although detailed explanation will be omitted here, as explained in "1-1-1. Structure of the cube chip 100," the stacked memory chip 30 includes a first surface 46, a second surface 48, a third surface 45, a fourth surface 47, a fifth surface 42, and a sixth surface 44, and as explained in "1-4. Overview of the IC chip 110," each of the multiple IC chips 110 includes a transistor layer 130 and a wiring layer 150. Although detailed explanation will be omitted here, as explained in "1-1-1. Structure of the cube chip 100," multiple ground wirings 165 are exposed on the second surfaces 48 of the multiple IC chips 110, as shown in FIG. 19.

For example, stacking (bonding) of IC chips 110 together can be achieved using techniques such as fusion bonding and silicon direct bonding (SDB). Fusion bonding and silicon direct bonding are techniques used in the relevant technical field, and detailed explanations will be omitted here. For example, bonding IC chips 110 together so that their wiring layers 150 face each other is called F2F bonding ( For example, joining two IC chips 110 together so that the semiconductor substrates 173 included in each transistor layer 130 face each other is called B2B joining (Back to Back Fusion). For example, joining two IC chips 110 together so that the wiring layer 150 faces the semiconductor substrate 173 included in the transistor layer 130 is called F2B joining (Face to Back Fusion).

The number of IC chips 110 stacked, their bonding, and their mounting structure can be changed as appropriate depending on the specifications and applications of the cube chip 100.

Step 23 (S23) shown in FIG. 17 is a step of applying resin to the side surfaces of the stacked memory chips 30. For example, as shown in FIG. 20, the resin is an insulating film 56. For example, the insulating film 56 is a sealing material similar to that of the structure 50. The side surfaces of the stacked memory chips 30 are the second surface 48, the third surface 45, the fourth surface 47, the fifth surface 42, and the sixth surface 44, excluding a portion of the second surface 48. The insulating film 56 is not applied to the first surface 46 and a portion of the second surface 48 of the stacked memory chips 30.

For example, the insulating film 56 is formed using a coating device such as a dispenser.

The surfaces formed by S23 are the surfaces of the cube chip 100. Referring to FIG. 18 or 20, the first surface 446, second surface 448, third surface 445, fourth surface 447, fifth surface 442, and 444 of the cube chip 100 are parallel to the first surface 46, second surface 48, third surface 45, fourth surface 47, fifth surface 42, and sixth surface 44 of the stacked memory chip 30. For example, the first surface 446 is parallel to the first surface 46, and the second surface 448 is parallel to the second surface 48. The third surfaces 445 to 444 and the third surfaces 45 to 44 are also parallel to their corresponding surfaces, as are the first surface 446 and the first surface 46, and the second surface 448 and the second surface 48. Note that the first surface 446 is the first surface 46 because the insulating film 56 is not applied to the first surface 46.

Step 25 (S25) shown in FIG. 17 is a step of forming an electrode on the upper surface. As shown in FIG. 21, the upper surface is the second surface 448 of the cube chip 100, and the electrode is a plurality of side surface ground wirings 465. The plurality of side surface ground wirings 465 are formed on the second surface 448 of the cube chip 100. The plurality of side surface ground wirings 465 are electrically connected to the plurality of ground wirings 165 exposed on the second surface 48 of the stacked memory chip 30. Some of the plurality of side surface ground wirings 465 may contact and overlap part of the insulating film 56 formed on the second surface 448.

For example, the multiple side ground wirings 465 are formed using electrolytic plating (plating method). The multiple side ground wirings 465 include conductors made of metal. For example, the conductors made of metal may include conductors containing copper, silver, nickel, etc., or conductors containing gold, tin, nickel, etc. The multiple side ground wirings 465 include a thick metal film formed by electrolytic plating (plating method).

As described above, the electrodes (side surface ground wiring 465) included in the cube chip 100 are formed.

The corners of the stacked memory chips 30 are easily chipped due to physical impacts caused by transporting the stacked memory chips 30. For example, the corners of the stacked memory chips 30 are the intersections of the second surface 48, the fifth surface 42, and the third surface 45, and the intersections of the second surface 48, the third surface 45, and the sixth surface 44.

Like structures 50 and 50A, insulating film 56 functions to protect stacked memory chips 30 and cube chips 100 including stacked memory chips 30 from physical impact, and also functions to prevent moisture absorption and intrusion of impurities into stacked memory chips 30 and cube chips 100 including stacked memory chips 30.

Furthermore, the electrode (side surface ground wiring 465) is a thick metal film that functions to protect the stacked memory chips 30 and the stacked memory chips 30 from physical impact. Furthermore, the side surface ground wiring 465 is a thick metal film that can sufficiently reduce the resistance value of the side surface ground wiring 465 and can sufficiently suppress voltage drops in the ground voltage. As a result, the cube chip 100 is a chip with excellent long-term reliability, and the semiconductor module 10 is a module with excellent long-term reliability.

Sixth Embodiment
A method for forming electrodes included in a cube chip 100 according to the sixth embodiment will be described with reference to Fig. 18 and Figs. 22 to 25. Fig. 22 is a flowchart showing an example of a method for forming electrodes included in a cube chip 100. Figs. 23 to 25 are perspective views for explaining an example of a method for forming electrodes. Configurations that are the same as or similar to those in Figs. 1 to 21 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figs. 1 to 21 may be omitted.

As shown in Figure 22, the method for forming the electrodes included in the cube chip 100 includes steps 31 (S31) to 35 (S35).

When the method for forming the electrodes included in the cube chip 100 begins, multiple IC chips 110 are stacked (S31 shown in Figure 22). For example, as shown in Figure 18, eight IC chips 110 (eight layers, eight sheets) are stacked to form a stacked memory chip 30.

The stacked memory chip 30 includes the same configuration as that described in the "Fifth Embodiment." Therefore, configurations similar to those described in the "Fifth Embodiment" will be described as necessary. The stacked memory chip 30 according to the sixth embodiment includes the same configuration as that described in the "Fifth Embodiment" as well as the configuration shown in FIG. 23. Although detailed description will be omitted here, as explained in "1-1-1. Configuration of the cube chip 100," multiple power supply wiring 164 is exposed on the third surface 45 of the multiple IC chips 110, as shown in FIG. 23. Furthermore, although not shown, the multiple power supply wiring 164 is also exposed on the fourth surface 47.

Step 33 (S33) shown in FIG. 22 is a step of forming electrodes on the top and side surfaces. As shown in FIG. 24, the top surface is the second surface 48 of the stacked memory chip 30, and the electrodes are side surface ground wiring 565. Also, as shown in FIG. 24, the side surface is the third surface 45, and the electrodes are multiple side surface power supply wiring 564.

For example, the side ground wiring 565 is formed in a solid state on the second surface 48 of the stacked memory chip 30. The side ground wiring 565 is electrically connected to a plurality of ground wirings 165 exposed on the second surface 48 of the stacked memory chip 30. A plurality of side power supply wirings 564 are formed on the third surface 45 of the stacked memory chip 30. The side power supply wiring 564 is electrically connected to a plurality of power supply wirings 164 exposed on the third surface 45 of the stacked memory chip 30. Although not shown in the figure, the plurality of side power supply wirings 564 are also electrically connected to a plurality of power supply wirings 164 exposed on the fourth surface 47.

For example, the side surface ground wiring 565 and the multiple side surface power supply wirings 564 are formed using electrolytic plating (plating method), as in the "fifth embodiment." The side surface ground wiring 565 and the multiple side surface power supply wirings 564 include a conductor containing the same material as the multiple side surface ground wirings 465, and include a thick metal film.

Step 35 (S35) shown in FIG. 22 is a step of applying resin to the bottom surface and surfaces other than the surface on which electrodes are formed. For example, as shown in FIG. 25, the resin is an insulating film 58. For example, the insulating film 58 is formed using the same sealing material and apparatus as the insulating film 56. The bottom surface of the stacked memory chip 30 is the first surface 46. The surfaces of the stacked memory chip 30 other than the surface on which electrodes are formed are the second surfaces 48 other than the second surface 48 on which electrodes are formed, the third surfaces 45 other than the third surface 45 on which electrodes are formed, the fourth surfaces 47 other than the fourth surface 47 on which electrodes are formed, the fifth surface 42, and the sixth surface 44.

The insulating film 58 formed on the second surface 48 may contact and overlap a portion of the side surface ground wiring 565, and the insulating film 58 formed on the third surface 45 and fourth surface 47 may contact and overlap a portion of the side surface power supply wiring 564.

As described above, the electrodes (side surface ground wiring 565 and side surface power supply wiring 564) and resin (insulating film 58) included in the cube chip 100 are formed.

By using the method for forming the electrodes included in the cube chip 100 according to the sixth embodiment, it is possible to achieve the same effects as the method for forming the electrodes included in the cube chip 100 according to the fifth embodiment.

・BR>E-V implementation form＞
A method for manufacturing a semiconductor module 10 according to a seventh embodiment of the present invention will be described with reference to Figures 26 and 27. Figures 26 and 27 are flowcharts showing an example of a method for manufacturing a semiconductor module 10. Configurations that are the same as or similar to those in Figures 1 to 25 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figures 1 to 25 may be omitted.

For example, as shown in FIG. 26, the method for manufacturing the semiconductor module 10 includes steps 41 (S41) to 45 (S45).

When the manufacturing method for the semiconductor module 10 begins, the second inclined portion 51 included in the cube chip 100 is formed (S41 shown in FIG. 26). After forming the second inclined portion 51, the insulating film 40 may be formed on the first surface 146. In addition, the insulating film 210 may be formed on the first inclined portion 41 of the frame body 200 and the first surface 304 of the first substrate 300.

Step 43 (S43) shown in Figure 26 is a step of temporarily aligning the cube chip 100 and the frame body 200. For example, the second inclined portion 51 of the cube chip 100 is aligned with the first inclined portion 41 of the frame body 200. At this time, the cube chip 100 is not pressed against the frame body 200 and is not fitted together. For example, if the cube chip 100 moves within the frame body 200, you can return to S41 and adjust the angle α of the second inclined portion 51.

26 shows step 45 (S45), which rotates the cube chip 100 and attaches it to the frame 200. For example, after the temporary alignment in S43, the cube chip 100 is removed from the frame 200 and the first substrate 300. Then, for example, the cube chip 100 shown in FIG. 21 is rotated clockwise along the third direction D3 from the second direction D2 to the first direction D1, and the cube chip 100 shown in FIG. 21 is attached to the frame 200 shown in FIG. 12 so that the second inclined portion 51 is parallel to the first inclined portion 41. That is, the first surface 146 (see, for example, FIGS. 1 and 2) of the cube chip 100 and the first surface 46 (see, for example, FIG. 2) of the stacked memory chip 30 are positioned at predetermined positions inside the frame 200 (the first surface 304 of the first substrate 300) via the frame 200. Furthermore, after the cube chip 100 is attached to the frame 200, the cube chip 100 is pressure-bonded to the frame 200, and the cube chip 100 is fitted into the frame 200.

At this time, the cube chip 100 is not electrically or mechanically connected to the first substrate 300. For example, the cube chip 100 is pressed onto the first surface 304 of the first substrate 300. For example, the first surface 146 of the cube chip 100 and the first surface 46 of the stacked memory chip 30 may correspond to the surface pressed onto the first surface 304 of the first substrate 300, or a portion of the insulating film 40 provided on the first surface 146 of the cube chip 100 and the first surface 46 of the stacked memory chip 30 may correspond to the surface pressed onto the first surface 304 of the first substrate 300. Note that, for example, as described in the "Fourth Embodiment," the cube chip 100 is electrically connected to an external device (external circuit) outside the semiconductor module 10 via the side power supply wiring 162 (see FIG. 2) provided on the third surface 145. The third surface 145 is a surface different from the surface pressed onto the first surface 304 of the first substrate 300.

For example, if particles of several microns are superimposed on inductor 172 or inductor 372, the particles of several microns will interfere with inductor communication, reducing the quality of inductor communication. Therefore, for example, the cube chip 100 is attached to and removed from the frame body 200 and first substrate 300 in a clean room of class 100 or higher. Furthermore, the attachment of the cube chip 100 to and removal of the cube chip 100 from the frame body 200 and first substrate 300 are performed with a reduced number of particles, using an air blower or the like. As a result, particles of several microns can be reduced, preventing a reduction in the quality of inductor communication between inductor 172 and inductor 372.

As explained above, the cube chip 100 is fitted into the frame body 200 and connected (contacted) to the top of the first substrate 300. The method for manufacturing the semiconductor module 10 shown in FIG. 26 makes it possible to removably connect the cube chip 100 to the frame body 200 and the first substrate 300.

Furthermore, for example, as shown in FIG. 27, the method for manufacturing the semiconductor module 10 may include steps 51 (S51) to 55 (S55). Steps S51 and 53 (S53) are similar to steps S41 and S43, and therefore will not be described here.

27 shows step 55 (S55) in which the first substrate 300 and frame body 200 are vibrated to attach the cube chip 100 to the frame body 200. For example, after temporary alignment in S43, the cube chip 100 is removed from the frame body 200 and first substrate 300. Thereafter, for example, the cube chip 100 shown in FIG. 21 is placed on the frame body 200 and first substrate 300 shown in FIG. 12 so that the second inclined portion 51 is parallel to the first inclined portion 41. After the cube chip 100 is placed on the frame body 200 and first substrate 300, the frame body 200 and first substrate 300 are vibrated to fit the cube chip 100 into the frame body 200. The frame body 200 and the first substrate 300 may be vibrated to fit the cube chip 100 into the frame body 200, and then the cube chip 100 may be pressure-bonded to the frame body 200 to fit the cube chip 100 into the frame body 200.

As explained above, the cube chip 100 is fitted into the frame body 200 and connected (contacted) to the top of the first substrate 300. The method for manufacturing the semiconductor module 10 shown in Figure 27 makes it possible to removably connect the cube chip 100 to the frame body 200 and the first substrate 300.

In S41, the cube chip 100 may be rotated clockwise from the second direction D2 to the first direction D1 along the third direction D3, and the cube chip 100 may be attached to the frame body 200 so that the second inclined portion 51 is parallel to the first inclined portion 41. Then, in S51, the frame body 200 and the first substrate 300 may be vibrated to fit the cube chip 100 into the frame body 200. Alternatively, the frame body 200 and the first substrate 300 may be vibrated to fit the cube chip 100 into the frame body 200, and then the cube chip 100 may be pressure-bonded to the frame body 200 to fit the cube chip 100 into the frame body 200. By combining the manufacturing methods for the semiconductor module 10 shown in FIGS. 26 and 27, the cube chip 100 can be removably connected to the frame body 200 and the first substrate 300.

Eighth Embodiment
A semiconductor module 10B according to the eighth embodiment will be described with reference to Fig. 28. Fig. 28 is a plan view showing an example of the configuration of the semiconductor module 10B. Configurations that are the same as or similar to those in Figs. 1 to 27 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figs. 1 to 27 may be omitted.

The semiconductor module 10B differs from the semiconductor module 10 in the following configurations (1) and (2).
(1) Three or more cube chips 100 (for example, cube chips 100C and 100D) and three or more frames 200 (for example, frames 200C and 200F) are included.
(2) The third substrate 300B includes three or more cube chips 100 (for example, cube chips 100C and 100D) and three or more frame bodies 200 (for example, frame bodies 200C and 200F).

The configuration of semiconductor module 10B other than the configurations shown in (1) and (2) is the same as that of semiconductor module 10. For example, cube chips 100C and 100D include the same configuration as cube chip 100, and frame bodies 200C and 200F include the same configuration as frame body 200.

Furthermore, each of the multiple cube chips 100, including cube chips 100C and 100D, is fitted into a corresponding frame body 200. For example, cube chip 100C is fitted into frame body 200C, and cube chip 100D is fitted into frame body 200F. The third substrate 300B includes multiple inductors 372 corresponding to the multiple inductors 172 of each of the multiple cube chips, including cube chips 100C and 100D.

As explained above, the semiconductor module 10B can include multiple cube chips 100 on a single substrate (third substrate 300B). As a result, the semiconductor module 10B can have a large memory capacity. Furthermore, like the semiconductor module 10A, the semiconductor module 10B may be supplied with a power supply voltage using the power supply unit 700, and may be supplied with a ground voltage and dissipate heat to the outside using the thermal conduction sheet 800 and metal film 900. Therefore, the semiconductor module 10B has the same effects as the semiconductor module 10 and the semiconductor module 10A.

Ninth Embodiment
A semiconductor module 10C according to the ninth embodiment will be described with reference to FIGS. 29 and 30. FIG. 29 is a plan view showing an example of the configuration of the semiconductor module 10C. FIG. 30 is an end view showing the cross-sectional structure of the end portion of the semiconductor module 10C taken along line C1-C2 shown in FIG. 29. Configurations that are the same as or similar to those in FIGS. 1 to 28 will be described as necessary, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 28 may be omitted.

The semiconductor module 10C differs from the semiconductor module 10B in the following configurations (1) to (3).
(1) Includes a connecting member 750.
(2) A plurality of cube chips 100 (for example, four cube chips including cube chips 100E and 100F) are bundled with a connecting member 750 and fitted into one frame 200E.
(3) The fourth substrate 300C includes a plurality of (for example, six) cube chips 100 bundled by the connection members 750 fitted into one frame 200E.

The configuration of semiconductor module 10C other than those shown in (1) to (3) is the same as that of semiconductor module 10B.

Furthermore, the fourth substrate 300C includes a plurality of inductors 372 corresponding to the respective inductors 172 of the plurality of cube chips including the cube chips 100E and 100F.

For example, cube chips 100E and 100F have a configuration similar to that of the cube chip 100 shown in FIG. 24. Furthermore, frame body 200E has a configuration in which the first frame body 200L and the third frame body 200R of the frame body 200 shown in FIG. 12 extend in the second direction D2.

Referring to Figures 24, 29, and 30, each of the cube chips 100E and 100F includes a side power supply wiring 162 in contact with the third surface 145 and a side power supply wiring 162 in contact with the fourth surface 147.

Furthermore, the fifth surface 142 of the cube chip 100E contacts the sixth surface 144 of the cube chip 100F. The connecting member 750 contacts at least the sixth surface 144, third surface 145, and fourth surface 147 of the cube chip 100E, as well as the third surface 145 and fourth surface 147 of the cube chip 100F.

Furthermore, the connection member 750 contacts the side power supply wiring 162 that contacts the third surface 145 of each of the cube chips 100E and 100F and the side power supply wiring 162 that contacts the fourth surface 147 of each of the cube chips 100E and 100F, and supplies power supply voltage to the side power supply wiring 162 that contacts the third surface 145 of each of the cube chips 100E and 100F and the side power supply wiring 162 that contacts the fourth surface 147 of each of the cube chips 100E and 100F.

As explained above, the semiconductor module 10C can include multiple frame bodies 200E, which can bundle multiple cube chips 100, on a single substrate (fourth substrate 300C). As a result, the semiconductor module 10C can shorten the installation time compared to when multiple cube chips 100 are installed one by one on the frame body 200.

Furthermore, the connection member 750 has the function of bundling multiple cube chips 100 together and the function of supplying power supply voltage to the multiple cube chips 100. Therefore, the semiconductor module 10C can reduce manufacturing costs and suppress a decrease in yield compared to when multiple cube chips 100 are attached one by one to the frame 200 and power supply voltage is supplied to each cube chip 100 individually.

Furthermore, the semiconductor module 10C has a configuration that can reduce misalignment between the cube chips 100 and the frame body 200 compared to when multiple cube chips 100 are attached to the frame body 200 one by one. Therefore, the semiconductor module 10C can reduce damage to the cube chips 100 due to misalignment, and has a configuration that is excellent in long-term reliability.

Furthermore, the semiconductor module 10C can include multiple frame bodies 200E, which can bundle multiple cube chips 100, on a single substrate (fourth substrate 300C). As a result, like the semiconductor module 10B, the semiconductor module 10C can have a large memory capacity and has the same effects as the semiconductor module 10B.

Tenth Embodiment
A semiconductor module 10D according to a tenth embodiment will be described with reference to FIGS. 31 to 38. FIG. 31 is a plan view showing an example of the configuration of the semiconductor module 10D. FIG. 32 is an end view showing the end cross-sectional structure of the semiconductor module 10D taken along line E1-E2 shown in FIG. 31. FIG. 33 is a flowchart showing an example of a manufacturing method for the semiconductor module 10D. FIGS. 34 to 38 are end views for explaining an example of a manufacturing method for the semiconductor module 10D. Configurations that are the same as or similar to those in FIGS. 1 to 30 will be described as necessary, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 30 may be omitted. Note that the configuration of the semiconductor module 10D described with reference to FIGS. 31 to 38 is merely an example and does not limit the configuration of the semiconductor module 10D.

<10-1. Configuration of Semiconductor Module 10D>

First, an example of the configuration of a semiconductor module 10D will be described with reference to FIGS.

Semiconductor module 10D includes cube chips 100G-100J, first substrates 300G and 300H, bump layer 80, underfill (UF) materials 84A-84C, a semiconductor chip 600, a fifth substrate 60, and a molding material 90. As an example, semiconductor module 10D includes four cube chips 100G-100J and one semiconductor chip 600, but the number of cube chips 100G-100J and semiconductor chips 600 is not limited to the configuration described in the tenth embodiment. The number of cube chips 100G-100J and semiconductor chips 600 can be selected appropriately depending on the specifications and application of semiconductor module 10D.

Each of the cube chips 100G to 100J has a configuration similar to that of the cube chip 100. Therefore, the configuration of the multiple cube chips 100G to 100J will be described as necessary. The multiple cube chips 100G to 100J are attached to their corresponding frame bodies 200 and provided on a first substrate 300. For example, as shown in FIG. 33 , the cube chip 100G is attached to the frame body 200G and provided on a first substrate 300G, and the cube chip 100H is attached to the frame body 200H and provided on a first substrate 300H. Although not shown, each of the multiple cube chips 100G to 100J may include an insulating film 40 and an insulating film 210, similar to the cube chip 100.

Each of the first substrates 300G and 300H has a configuration similar to that of the first substrate 300. Therefore, the configurations of the first substrates 300G and 300H will be described as necessary. The first substrate 300G is electrically connected to the fifth substrate 60 via the bump layer 80 (plurality of bumps 82).

For example, the semiconductor chip 600 may be a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or may include both a CPU and a GPU.

If the semiconductor chip 600 includes a CPU, the semiconductor chip 600 includes multiple arithmetic circuits and is capable of arithmetic processing. Furthermore, if the semiconductor chip 600 includes a GPU, the semiconductor chip 600 includes multiple arithmetic circuits and is capable of image processing and video processing. For example, the semiconductor chip 600 has the function of reading a control program stored in a dynamic random access memory (DRAM) (not shown) included in an external device via the bump layer 80 and the fifth substrate 60, unpacking the control program, and executing processing based on the control program, as well as transmitting commands to each IC chip 110 to execute processing based on the control program.

The bump layer 80 includes a plurality of bumps 82. For example, the plurality of bumps 82 correspond to output terminals of the cube chips 100G to 100J and the semiconductor chip 600. Each of the cube chips 100G to 100J and the semiconductor chip 600 is electrically connected to the plurality of bumps 82, and is electrically connected to the fifth substrate 60.

For example, the UF material 84 (84A-84C) is an insulating adhesive. For example, the UF material 84A can secure the electrically connected cube chip 100G, first substrate 300G, bump layer 80 (bumps 82), and fifth substrate 60 to one another. Like the UF material 84A, the UF material 84B can secure the electrically connected cube chip 100H, first substrate 300H, bump layer 80 (bumps 82), and fifth substrate 60 to one another, and the UF material 84C can secure the electrically connected semiconductor chip 600, bump layer 80 (bumps 82), and fifth substrate 60 to one another.

Like the first substrate 300, the fifth substrate 60 includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked. For example, the fifth substrate 60 is a printed circuit board capable of high-density interconnect (HDI). Specifically, the fifth substrate 60 may be an organic laminate substrate, a silicon interposer in which wiring is formed on a silicon substrate (e.g., Si-wafer), an active interposer in which active elements are added to a silicon interposer, a silicon bridge-embedded substrate in which a silicon chip with wiring is embedded in an organic substrate, a glass core substrate in which wiring is formed using glass as a core material, or an RDL (Redistribution Layer) interposer in which wiring is formed in an insulating film. Furthermore, like the semiconductor module 10 shown in FIGS. 2 and 3 , the number of layers in the multilayer wiring structure of the fifth substrate 60 is not limited to the number of layers (five) shown in FIG. 32 . As with the semiconductor module 10, the number of layers in the multilayer wiring structure of the fifth substrate 60 can be changed as appropriate based on the application or specifications of the semiconductor module 10D.

As an example, the fifth substrate 60 includes a first surface 62, a second surface 64, and multiple wiring layers 66, 68, 70, 72, and 74. The wiring layers 66, 68, 70, 72, and 74 are arranged parallel to the first direction D1 and the second direction D2, and are stacked in this order in the third direction D3. The multiple wiring layers 66 and 74 include multiple electrodes 67 and multiple electrodes 75. The multiple wiring layers 68, 70, and 72 include multiple wires 69, multiple wires 71, and multiple wires 73. The multiple electrodes 67 are exposed on the first surface 62, and the multiple electrodes 75 are exposed on the second surface 64. The electrode 67 is electrically connected to the wire 69, the wire 69 is electrically connected to the wire 71, the wire 71 is electrically connected to the wire 73, and the wire 73 is electrically connected to the electrode 75. The insulating layers stacked alternately with the wires are not shown in Figure 32.

For example, the fifth substrate 60 has a function of connecting each of the cube chips 100G to 100J to the semiconductor chip 600. As an example, as shown in FIG. 32 , the cube chip 100G is connected to the semiconductor chip 600 via electrodes 67, wirings 69, wirings 71, and bumps 82. Note that the example shown in FIG. 32 is just an example, and the connection between each of the cube chips 100G to 100J and the semiconductor chip 600 is not limited to the example shown in FIG. 32 . Each of the cube chips 100G to 100J and the semiconductor chip 600 may be connected via a plurality of electrodes 67, a plurality of wirings 69, a plurality of wirings 71, or a plurality of wirings 73, and each of the cube chips 100G to 100J may be connected via a plurality of electrodes 67, a plurality of wirings 69, a plurality of wirings 71, or a plurality of wirings 73.

The fifth substrate 60 also functions to connect the cube chips 100G-100J and the semiconductor chip 600 to external devices, etc. The fifth substrate 60 also functions to electrically connect the plurality of bumps 82 to the electrodes 75 corresponding to each bump 82. The length (pitch) between two adjacent bumps 82 is shorter than the length (pitch) between two adjacent electrodes 75. The fifth substrate 60 also functions to widen the pitch of the bumps 82 to the pitch of the electrodes 75. In other words, the fifth substrate 60 also functions to rewire the bumps 82 so that the pitch of the bumps 82 matches the pitch of the electrodes 75. As a result, the semiconductor module 10 can be easily electrically connected to a motherboard (not shown).

For example, the molding material 90 is an insulating resin material. For example, the insulating resin material includes a resin material such as epoxy, a curing agent, a filler, an additive, etc. For example, the molding material 90 is provided on the fifth substrate 60 so as to contact and surround the cube chip 100G fixed by the UF material 84A, the first substrate 300G and the bumps 82, the cube chip 100H fixed by the UF material 84B, the first substrate 300H and the bumps 82, and the semiconductor chip 600 and the bumps 82 fixed by the UF material 84C. The molding material 90 can fix the cube chip 100G fixed by the UF material 84A, the first substrate 300G and the bumps 82, the cube chip 100H fixed by the UF material 84B, the first substrate 300H and the bumps 82, and the semiconductor chip 600 fixed by the UF material 84C to one another on the fifth substrate 60. As a result, the molding material 90 can suppress vibrations and shocks that the semiconductor module 10D receives from the outside, as well as the intrusion of moisture into the semiconductor module 10D from the outside. Furthermore, the molding material 90 allows the semiconductor module 10D to efficiently discharge heat generated inside the semiconductor module 10D to the outside.

For example, as shown in FIG. 31, when the scale of the semiconductor module 10D is small, the fifth substrate 60 may be an interposer.

Semiconductor module 10D is small in scale and has a configuration that allows multiple cube chips (e.g., cube chips 100G-100J) to be attached and detached. Therefore, even if a cube chip in semiconductor module 10D fails, the user can simply remove the failed cube chip and replace it with a non-failed cube chip.

Furthermore, because the semiconductor module 10D has a configuration that allows multiple cube chips (e.g., cube chips 100G-100J) to be attached and detached, and is small in scale, even if the fifth substrate 60 warps, the effect of the warping of the fifth substrate 60 on the multiple cube chips is minor. For example, by removing and reattaching the multiple cube chips, it is possible to adjust the positions of the multiple cube chips relative to the frame 200G, and the effects of substrate warping can be suppressed.

<10-2. Manufacturing Method of Semiconductor Module 10D>

Next, an example of a method for manufacturing the semiconductor module 10D will be described with reference to FIGS.

As shown in Figure 33, the method for manufacturing the semiconductor module 10D includes steps 60 (S60) to 66 (S66).

When the manufacturing method for the semiconductor module 10D begins, chips are mounted on the substrates (S60 shown in FIG. 33). Specifically, as shown in FIG. 34, the first surface 302G of the first substrate 300G is mounted on (electrically connected to) the fifth substrate 60 via the bump layer 80 (multiple bumps 82), the first surface 302H of the first substrate 300H is mounted on (electrically connected to) the fifth substrate 60 via the bump layer 80 (multiple bumps 82), and the first surface 602 of the semiconductor chip 600 is mounted on (electrically connected to) the fifth substrate 60 via the bump layer 80 (multiple bumps 82). Although not shown, the third substrate on which the cube chips 100I and 100J are provided is also mounted on (electrically connected to) the fifth substrate 60 via the bump layer 80 (multiple bumps 82), similar to the first substrates 300G and 300H. For example, first surface 302G, first surface 302H, and first surface 602 are parallel to first surface 32, which is an imaginary surface. In the following explanation, explanations related to cube chips 100I and 100J and the third substrate on which cube chips 100I and 100J are provided are similar to those related to cube chips 100G and 100H and first substrates 300G and 300H on which cube chips 100G and 100H are provided, and will be explained as necessary.

Step 61 (S61) is a step in which the first substrates 300G and 300H and the semiconductor chip 600 are fixed together using UF materials 84 (84A-84C). Specifically, as shown in FIG. 34, UF material 84A fixes the first substrate 300G, bump layer 80 (bumps 82), and fifth substrate 60 to one another. Like UF material 84A, UF material 84B fixes the first substrate 300H, bump layer 80 (bumps 82), and fifth substrate 60 to one another, and UF material 84C fixes the semiconductor chip 600, bump layer 80 (bumps 82), and fifth substrate 60 to one another.

In step 62 (S62), the cube molds 92 are mounted and temporarily bonded using adhesive 94. Specifically, as shown in FIG. 35, two cube molds 92 are temporarily bonded to first substrates 300G and 300H using adhesive 94. The cube molds 92 have the same shape as cube chips 100G to 100J.

Step 63 (S63) is a step in which each chip (first substrate 300G, first substrate 300H, and semiconductor chip 600), UF materials 84A-84C, and multiple cube molds 92 are sealed using molding material 90. Specifically, as shown in FIG. 36, first substrate 300G, first substrate 300H, semiconductor chip 600, UF materials 84A-84C, and multiple cube molds 92 are covered and sealed with molding material 90. At this time, molding material 90 contacts first substrate 300G, first substrate 300H, semiconductor chip 600, UF materials 84A-84C, and multiple cube molds 92, as well as the surface of fifth substrate 60 on which first substrate 300G, first substrate 300H, semiconductor chip 600, UF materials 84A-84C, and multiple cube molds 92 are not provided.

Step 64 (S64) is a step of grinding the molding material 90. Specifically, as shown in FIG. 37 , the surface 96 of the molding material 90 provided in S63 is ground by back-grinding in the direction of the black arrow, which is a virtual line parallel to the third direction D3. As a result, a ground surface 98 of the molding material 90 is exposed. Furthermore, the multiple cube dies 92 are ground in the same manner as the molding material 90, exposing the surfaces of the multiple cube dies 92. For example, after chips are mounted on a substrate or after a pattern is formed on a substrate, the entire substrate can be ground by back-grinding to reduce the thickness of the substrate on which the chips are mounted or the substrate on which the pattern is formed.

Step 65 (S65) is a step of removing the cube mold 92 with its surface exposed. Specifically, as shown in FIG. 38 , the cube mold 92 with its surface exposed is removed from the molding material 90. At this time, the adhesive 94 may also be removed in the same manner as the molding material 90, and the adhesive 94 may remain on the first substrates 300G and 300H. By S65, frame bodies 200G and 200H are formed, to which the cube chips 100G and 100H can be attached.

Step 66 (S66) is a step of attaching the plurality of cube chips 100G and 100H. Specifically, as shown in Fig. 32, the cube chip 100G is attached to a frame 200G and a first substrate 300G, and the cube chip 100H is attached to a frame 200H and a first substrate 300H.

As described above, the semiconductor module 10D is manufactured by the manufacturing method of the semiconductor module 10D.

For example, chips are typically mounted on a substrate using a molding material. In the semiconductor module 10D according to the tenth embodiment of the present invention, the molding material 90 is used to secure the first substrate 300G, the second substrate 300H, and the semiconductor chip 600 on the fifth substrate 60, and to form the frame bodies 200G and 200H. In other words, without adding any special processes, the chips can be secured and the frame bodies 200G and 200H can be formed using a general process. Therefore, the manufacturing method of the semiconductor module 10D can reduce manufacturing costs.

Eleventh Embodiment
A semiconductor module 10E according to an eleventh embodiment will be described with reference to FIGS. 39 to 42. FIG. 39 is an end view showing an example of the cross-sectional structure of an end portion of the semiconductor module 10E. FIG. 40 is a flowchart showing an example of a manufacturing method for the semiconductor module 10E. FIGS. 41 and 42 are end views for explaining an example of a manufacturing method for the semiconductor module 10E. Configurations that are the same as or similar to those in FIGS. 1 to 38 will be described as necessary, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 38 may be omitted. Note that the configuration of the semiconductor module 10E described with reference to FIGS. 39 to 42 is an example and does not limit the configuration of the semiconductor module 10E.

<11-1. Configuration of Semiconductor Module 10E>

First, an example of the configuration of a semiconductor module 10E will be described with reference to FIG.

The semiconductor module 10E includes a cube chip 100K, a first substrate 300D, a plurality of bumps 82, a UF material 84D, a fifth substrate 60A, and a resin 99.

The cube chip 100K, the first substrate 300D, the UF material 84D, the plurality of bumps 82, and the fifth substrate 60A each have the same configuration as the cube chip 100, the first substrate 300, the UF materials 84A to 84C, the plurality of bumps 82, and the fifth substrate 60. Therefore, the configurations of the cube chip 100K, the first substrate 300D, the UF material 84D, the plurality of bumps 82, and the fifth substrate 60A will be described as necessary.

The resin 99 is an adhesive such as a thermoplastic resin or wax. As an example, the resin 99 is a thermoplastic resin, which is an adhesive containing an epoxy resin or an acrylic polymer. The resin 99 is provided between the cube chip 100K and the second surface 304D of the first substrate 300D so as to contact the cube chip 100K and the first substrate 300D.

Like the cube chip 100 and the first substrate 300, the cube chip 100K includes an inductor 172, and the first substrate 300D includes an inductor 372, and the inductor 172 is capable of non-contact inductive communication with the inductor 372. Also, for example, the side surface power supply wiring 162 in the cube chip 100K is divided into three in the third direction D3. Of the three divided side surface power supply wirings 162, structures 50 are provided between adjacent side surface power supply wirings 162, and the three divided side surface power supply wirings 162 are spaced apart from each other.

The first substrate 300D is connected to a plurality of bumps 82, each of which is connected to a corresponding one of the electrodes 67, and the first substrate 300D is connected to the fifth substrate 60A.

The UF material 84D surrounds the first substrate 300D, the plurality of bumps 82, and the plurality of electrodes 67, and is provided between the first surface 302D of the first substrate 300D and the first surface 62A of the fifth substrate 60A so as to be in contact with the first surface 302D and the first surface 62A. The cube chip 100K bonded to the first substrate 300D and the first substrate 300D are fixed to the fifth substrate 60A by the UF material 84D.

<11-2. Manufacturing Method of Semiconductor Module 10E>

Next, an example of a method for manufacturing the semiconductor module 10E will be described with reference to FIGS.

As shown in Figure 40, the method for manufacturing the semiconductor module 10D includes steps 70 (S70) to 75 (S75).

When the manufacturing method for the semiconductor module 10E begins, the temperature is raised to above the softening temperature of the resin 99, and the cube chip 100K is mounted on the first substrate 300D (S70 shown in Figure 40). Specifically, the temperature of the entire semiconductor module 10E is raised to above the softening temperature of the resin 99, and the cube chip 100K is mounted on the first substrate 300D on which the resin 99 is provided. For example, the softening temperature of the resin 99 is 150 degrees.

Step 71 (S71) is a step of supplying power to the cube chip 100K and the first substrate 300D. Specifically, as shown in FIG. 41 , a plurality of pogo pins 702 in a power supply unit 700 are pressure-bonded to the side power wiring 162 of the cube chip 100K. The power supply unit 700 supplies voltages (e.g., power supply voltages VDD and VSS) from an external device (external circuit) outside the semiconductor module 10E to the cube chip 100K and the first substrate 300D via the plurality of pogo pins 702. The power supply unit 700 may supply a plurality of power supply voltages (e.g., power supply voltages VDD1 and VDD2), and some electrodes may be changed to signal lines, and signals (e.g., control signals and data signals) rather than DC (Direct Current) power may be input/output to the signal lines via the pogo pins 702.

Step 72 (S72) is a step in which wireless communication (inductor communication) is performed between the cube chip 100K and the first substrate 300D. Specifically, as shown in Fig. 41 , power is supplied to each of the cube chip 100K and the first substrate 300D, causing the cube chip 100K and the first substrate 300D to operate, and inductor communication (wireless communication) between the inductor 172 and the inductor 372 to be performed in a contactless manner.

Step 73 (S73) is a step of fixing the cube chip 100K while moving it, while maintaining good quality of wireless communication (inductor communication) between the cube chip 100K and the first substrate 300D. For example, when the resin 99 is softened, the cube chip 100K can move on the second surface 90B of the resin 99 in parallel with the second direction D2. Furthermore, when power is supplied to the cube chip 100K and the first substrate 300D, wireless communication between the cube chip 100K and the first substrate 300D is possible, and the quality of the wireless communication can be monitored. Therefore, step S73 includes causing the cube chip 100K to perform inductor communication between the inductor 172 and the inductor 372 facing each other, moving the cube chip 100K along the second surface 90B of the resin 99 in parallel to the second direction D2, moving the cube chip 100K to cause inductor communication between the inductor 172 and the inductor 372 facing each other in a plurality of states where the positional relationship between the cube chip 100K and the first substrate 300D is different, monitoring and acquiring data related to the strength of communication in a plurality of states where the positional relationship between the cube chip 100K and the first substrate 300D is different, and determining a state where the quality of wireless communication (inductor communication) is good, moving the cube chip 100K to be positioned at a position corresponding to that state, and fixing the cube chip 100K. For example, the first substrate 300D analyzes all the acquired data and determines a state where the strength of communication between the inductor 172 and the inductor 372 facing each other is greatest (highest) as a state where the quality of wireless communication (inductor communication) is good. The first substrate 300D determines whether the quality of wireless communication (inductor communication) is good, and instructs the external circuit to move the cube chip 100K so that it is positioned at a position corresponding to the determined quality and fix the cube chip 100K. That is, S73 includes fixing the cube chip 100K at a position where the optimal communication state is achieved by so-called active alignment.

Step 74 (S74) is a step in which the temperature is lowered to below the softening temperature of the resin 99, and the cube chip 100K is placed on the first substrate 300D. Since the quality of wireless communication between the cube chip 100K and the first substrate 300D is good and the power supply is stopped in S73, the resin 99 is hardened by lowering the temperature of the entire semiconductor module 10E to below 150°C. As the resin 99 hardens, the cube chip 100K is fixed onto the first substrate 300D.

Step 75 (S75) is a step of stopping the supply of power to the cube chip 100K and the first substrate 300D. Furthermore, stopping the supply of power to the cube chip 100K and the first substrate 300D stops wireless communication between the cube chip 100K and the first substrate 300D. Note that the manufacturing method for the semiconductor module 10E does not need to include S75, and S75 may be executed after the manufacturing method for the semiconductor module 10E is completed, or S75 may be executed as needed.

As described above, the semiconductor module 10E is manufactured by the manufacturing method of the semiconductor module 10E.

Furthermore, for example, if the cube chip 100K breaks down, the user can replace the cube chip 100K with a non-faulty cube chip. Replacing the cube chip 100K with a non-faulty cube chip includes executing S70 to soften the resin 99 by the manufacturing method of the semiconductor module 10E, and removing the cube chip 100K by moving it over the second surface 90B of the resin 99 along the imaginary line indicated by the black arrow parallel to the second direction D2, as shown in FIG.

As described above, the manufacturing method of the semiconductor module 10E can fix the cube chip 100K in a position that provides optimal communication through active alignment, thereby enabling optimal wireless communication between the cube chip 100K and the first substrate 300D.

Furthermore, the semiconductor module 10E does not include a frame body 200, and has a configuration in which the cube chip 100K can be attached and detached using a resin 99. The resin 99 is provided between the cube chip 100K and the first substrate 300D by a process commonly used in semiconductor processes, and therefore the manufacturing method of the semiconductor module 10E does not require a special process for providing the resin 99. Therefore, the manufacturing method of the semiconductor module 10E can reduce manufacturing costs.

Twelfth Embodiment
A semiconductor module 10F according to a twelfth embodiment will be described with reference to FIG. 43. FIG. 43 is an end view showing an example of the cross-sectional structure of the end portion of the semiconductor module 10F. Configurations that are the same as or similar to those in FIGS. 1 to 42 will be described as necessary, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 42 may be omitted. Note that the configuration of the semiconductor module 10F described with reference to FIG. 43 is one example and does not limit the configuration of the semiconductor module 10F.

The semiconductor module 10F differs from the semiconductor module 10E in the following configurations (1) and (2).
(1) The resin 95 has the same configuration as the resin 99, but as shown in FIG. 43, the resin 95 has a smaller contact area with the cube chip 100K and the first substrate 300D than the resin 99.
(2) As shown in FIG. 43, between the cube chip 100K and the first substrate 300D, the portion excluding the portion where the cube chip 100K and the first substrate 300D contact the resin 99 includes a non-contact region 97 where the cube chip 100K is separated from the first substrate 300D.

The configuration of semiconductor module 10F other than the configuration shown in (1) and (2) is the same as that of semiconductor module 10E. Therefore, a description of the configuration of semiconductor module 10F other than the configuration shown in (1) and (2) will be omitted.

The non-contact area 97 may be referred to as an unbonded area.

The semiconductor module 10F can be manufactured using the same manufacturing method as the semiconductor module 10E.

As shown in FIG. 43, in a cross-sectional view, the resin 95 is provided approximately in the center of the cube chip 100K (first surface 102K) and the first substrate 300D (second surface 304D) in the second direction D2. Also, in a cross-sectional view, the non-contact region 97 is provided to surround the resin 95 in the second direction D2. As a result, for example, in S70 of the manufacturing method of the semiconductor module 10F, when the resin 95 reaches or exceeds its softening temperature, the cube chip 100K can move independently in the non-contact region 97 without being affected by the resin 95.

For example, by including a non-contact region 97 between the cube chip 100K and the first substrate 300D, the semiconductor module 10F can suppress the concentration of stress during thermal cycles including S70 and S74 more than when resin is provided between the cube chip 100K and the first substrate 300D. As a result, the long-term reliability of the semiconductor module 10F is higher than that of a semiconductor module in which resin is provided between the cube chip 100K and the first substrate 300D.

(Additional Note)
The present invention is not limited to the above-described embodiment, and can be modified as appropriate without departing from the spirit of the present invention. For example, one embodiment of the present invention may have the following configuration.

(Appendix 1)

a first substrate including a first surface parallel to a first direction and a second direction intersecting the first direction;
a frame disposed on the first surface along a third direction intersecting the first direction and the second direction;
a cube chip attached to the frame and arranged on the first surface along the third direction and including a plurality of stacked IC chips;
a semiconductor chip including a plurality of logic circuits; a second substrate including a multilayer wiring structure;

a bump layer including a plurality of bumps that electrically connect the first substrate and the semiconductor chip to the second substrate;
an underfill material that fixes the first substrate and the bump layer, and the semiconductor chip and the bump layer, to the second substrate;
a molding material including the frame, the molding material being provided between the first substrate and the semiconductor chip, and being provided on the second substrate so as to surround a portion of the first substrate and a portion of the semiconductor chip;
12. A semiconductor module comprising:

(Appendix 2)

the frame body includes a first inclined portion,
the cube chip includes a second sloped portion;
an angle formed between the first surface and the first inclined portion is the same as an angle formed between the first surface and the second inclined portion;
2. The semiconductor module of claim 1.

(Appendix 3)

the second inclined portion is covered with an insulating film;
3. The semiconductor module of claim 2.

(Appendix 4)

A method for manufacturing the semiconductor module according to claim 1,
The manufacturing method includes:
Mounting the first substrate and the semiconductor chip on the second substrate using the bump layer;
using the underfill material to fix the first substrate, the semiconductor chip, and the bump layer onto the second substrate;
temporarily adhering a cube mold having the same shape as the cube chip onto the first substrate;
using the molding material to cover the cube, the first substrate, the semiconductor chip, the bump layer, and the underfill material, and fix the cube, the first substrate, the semiconductor chip, the bump layer, and the underfill material onto the second substrate;
grinding the molding material to thin the molding material and expose the surface of the cube;
removing the cube;
attaching the cube chip to the frame formed by removing the cube mold;
A method for manufacturing a semiconductor module, comprising:

(Appendix 5)

a first substrate including a first inductor and including a first surface parallel to a first direction and a second direction intersecting the first direction;
a cube chip disposed on the first surface along the third direction and including a second inductor and a plurality of stacked IC chips;
a resin in contact with the first substrate and the cube chip and provided between the first substrate and the cube chip; a second substrate including a multilayer wiring structure;

a bump layer including a plurality of bumps electrically connecting the first substrate onto the second substrate;
an underfill material that fixes the first substrate and the bump layer to the second substrate;
Including,
the first inductor communicates with the second inductor in a non-contact manner;
Semiconductor module.

(Appendix 6)

the first substrate further includes an unbonded region provided between the first substrate and the cube chip, the first substrate being spaced apart from the cube chip;
The unbonded region surrounds the resin.
6. The semiconductor module of claim 5.

(Appendix 7)

A method for manufacturing a semiconductor module according to claim 6, comprising:
The manufacturing method includes:
raising the temperature of the semiconductor module to a temperature equal to or higher than the softening temperature of the resin, and mounting the cube chip on the first substrate;
supplying power to the cube chip and the first substrate;
moving the cube chip over the resin;
causing the first inductor and the second inductor to communicate with each other in a non-contact manner;
acquiring a communication strength in a state where the communication strength is strong in non-contact communication between the first inductor and the second inductor;
lowering the temperature of the semiconductor module below the softening temperature to fix the cube chip onto the first substrate;
A method for manufacturing a semiconductor module, comprising:

(Appendix 8)

raising the temperature of the semiconductor module to a temperature equal to or higher than the softening temperature of the resin, and moving the cube chip on the resin to remove it;
8. The semiconductor module of claim 7, comprising:

The semiconductor modules or various configurations of semiconductor modules exemplified as embodiments of the present invention may be combined as appropriate, provided they are not mutually inconsistent. Furthermore, the semiconductor modules or various configurations of semiconductor modules exemplified as embodiments of the present invention may be interchanged as appropriate, provided they are not mutually inconsistent. Furthermore, technical matters common to each embodiment are included in each embodiment even if not explicitly stated. Furthermore, semiconductor modules disclosed in this specification and drawings, to which a person skilled in the art has appropriately added, deleted, or modified components, or to which processes have been added, omitted, or conditions have been changed, are also included within the scope of the present invention, as long as they comprise the essence of the present invention.

Even if there are other effects and advantages different from those brought about by the embodiments disclosed in this specification, if they are clear from the description in this specification or can be easily predicted by a person skilled in the art, they are naturally understood to be brought about by the present invention.

10: Semiconductor module, 10A: Semiconductor module, 10B: Semiconductor module, 10C: Semiconductor module, 10D: Semiconductor module, 10E: Semiconductor module, 10F: Semiconductor module, 30: Stacked memory chip, 32: First surface, 40: Insulating film, 41: First inclined portion, 42: Fifth surface, 44: Sixth surface, 45: Third surface, 46: First surface, 47: Fourth surface, 48: Second surface, 50: Structure, 50A: Structure, 51: Second inclined portion, 56: Insulating film, 58: Insulating film, 60: Fifth Substrate, 60A: fifth substrate, 62: first surface, 62A: first surface, 64: second surface, 66: wiring layer, 67: electrode, 68: wiring layer, 69: wiring, 70: wiring layer, 71: wiring, 72: wiring layer, 73: wiring, 74: wiring layer, 75: electrode, 80: bump layer, 82: bump, 84: UF material, 84A: UF material, 84B: UF material, 84C: UF material, 84D: UF material, 90: molding material, 90B: second surface, 92: cube shape, 94: adhesive, 95: resin, 96: surface, 97: non-contact area, 98: Grinding surface, 99: resin, 100: cube chip, 100A: cube chip, 100B: cube chip, 100C: cube chip, 100D: cube chip, 100E: cube chip, 100F: cube chip, 100G: cube chip, 100H: cube chip, 100I: cube chip, 100J: cube chip, 100K: cube chip, 102: first surface, 102K: first surface, 104: second surface, 110: IC chip, 110n: IC chip , 111: memory module, 112: TCI-IO, 113: parallel-serial conversion circuit, 114: transceiver circuit, 115: memory cell array, 130: transistor layer, 142: fifth surface, 144: sixth surface, 145: third surface, 146: first surface, 147: fourth surface, 148: second surface, 150: wiring layer, 162: side power supply wiring, 163: side ground wiring, 164: power supply wiring, 165: ground wiring, 166: signal transmission wiring, 172: inductor, 172a: first part, 172b: second part, 1 72c: third portion, 172d: fifth portion, 172e: fourth portion, 173: semiconductor substrate, 174: element isolation region, 175: activation region, 176: transistor, 177: insulating layer, 178: wiring, 179: insulating layer, 180: wiring, 181: insulating layer, 182: insulating layer, 183: wiring, 200: frame, 200A: frame, 200B: frame, 200C: frame, 200D: fourth frame, 200E: frame, 200F: frame, 200G: frame, 200H: frame, 200L: first frame, 200 R: third frame, 200U: second frame, 202: frame, 202LD: first L-shaped frame, 202LU: second L-shaped frame, 202RD: fourth L-shaped frame, 202RU: third L-shaped frame, 204: frame, 204LD: first L-shaped frame, 204RU: second L-shaped frame, 210: insulating film, 272: inductor, 272a: first part, 300: first substrate, 300A: second substrate, 300B: third substrate, 300C: fourth substrate, 300D: first substrate, 300G: first substrate, 300H: first substrate Plate, 302: second surface, 304: first surface, 302A: second surface, 304A: first surface, 302D: first surface, 302G: first surface, 302H: first surface, 304D: second surface, 311: TCI-IO control module, 312: TCI-IO, 313: parallel-serial conversion circuit, 314: transmitter/receiver circuit, 326: wiring layer, 327: wiring, 328: wiring layer, 329: wiring, 330: wiring layer, 331: wiring, 332: wiring layer, 333: wiring, 334: wiring layer, 335: wiring, 372: inductor, 3 72a: First part, 372b: Second part, 372c: Third part, 372d: Fifth part, 372e: Fourth part, 400: Frame, 442: Fifth surface, 444: Sixth surface, 445: Third surface, 446: First surface, 447: Fourth surface, 448: Second surface, 465: Side ground wiring, 564: Side power wiring, 565: Side ground wiring, 600: Semiconductor chip, 602: First surface, 700: Power supply unit, 701: Support, 702: Pogo pin, 750: Connection member, 800: Thermal conduction sheet, 900: Metal film

Claims (17)

a first substrate including a first surface parallel to a first direction and a second direction intersecting the first direction;
a frame disposed on the first surface along a third direction intersecting the first direction and the second direction;
a first cube chip attached to the frame and arranged on the first surface along the third direction, the first cube chip including a plurality of stacked IC chips;
Semiconductor module. the first substrate includes a first inductor provided parallel to the first surface and spaced apart from the first surface;
the IC chip includes a second inductor provided parallel to the first surface and spaced apart from the first surface;
the first inductor is in contactless communication with the second inductor;
The semiconductor module according to claim 1 . the IC chip includes a plurality of memory cell arrays electrically connected to the first inductor;
The semiconductor module according to claim 2 . the frame body includes a first inclined portion,
the first cube chip includes a second sloped portion;
an angle formed between the first surface and the first inclined portion is the same as an angle formed between the first surface and the second inclined portion;
The semiconductor module according to claim 1 . the first cube chip includes a stacked memory chip including the plurality of IC chips, a first electrode electrically connected to the stacked memory chip, and a structure;
the stacked memory chips include at least a first outermost surface and a second outermost surface opposite to the first outermost surface, which are two outermost surfaces in the third direction, and a third outermost surface and a fourth outermost surface opposite to the third outermost surface, which are parallel to the third direction and the first direction and are two outermost surfaces in the second direction,
the first electrode is electrically connected to the third outermost surface;
the structure includes the second inclined portion and is provided so as to be in contact with the third outermost surface other than the surface to which the first electrode is connected;
The semiconductor module according to claim 4 . the first electrode is electrically connected to a power supply unit including a plurality of terminals to which a power supply voltage is supplied;
The semiconductor module according to claim 5 . the first cube chip includes a second electrode electrically connected to the second outermost surface;
A ground voltage is supplied to the second electrode.
The semiconductor module according to claim 5 . further comprising a heat spreader;
the heat spreader is electrically connected to a second electrode and supplies the ground voltage to the second electrode;
The semiconductor module according to claim 7 . The structure includes a resin or a metal.
The semiconductor module according to claim 5 . The frame body is configured by combining a first frame body, a second frame body, a third frame body, and a fourth frame body in a quadrangular shape.
The semiconductor module according to claim 1 . The frame body includes a first L-shaped frame body, a second L-shaped frame body, a third L-shaped frame body, and a fourth L-shaped frame body that are spaced apart from each other and provided at four corners of a rectangle.
The semiconductor module according to claim 1 . The frame body includes a first L-shaped frame body and a second L-shaped frame body spaced apart from each other and provided at two diagonal corners of a rectangle.
The semiconductor module according to claim 1 . a second cube chip attached to the frame, disposed on the first surface, adjacent to the first cube chip, and having a plurality of IC chips stacked thereon that are different from the plurality of IC chips;
a connecting member connecting the first cube chip and the second cube chip,
each of the first cube chip and the second cube chip includes a first outermost surface which is the two outermost surfaces in the third direction and a second outermost surface opposite to the first outermost surface; a third outermost surface which is parallel to the third direction and the first direction and which is the two outermost surfaces in the second direction and a fourth outermost surface opposite to the third outermost surface; a fifth outermost surface which is parallel to the third direction and the second direction and which is the two outermost surfaces in the first direction and a sixth outermost surface opposite to the fifth outermost surface;
the fifth outermost surface of the first cube chip is in contact with the sixth outermost surface of the second cube chip;
the connecting member contacts at least the sixth outermost surface, the third outermost surface, and the fourth outermost surface of the first cube chip, and the third outermost surface and the fourth outermost surface of the second cube chip;
The semiconductor module according to claim 1 . each of the first cube chip and the second cube chip includes a first electrode in contact with the third outermost surface and a second electrode in contact with the fourth outermost surface;
the connection member is in contact with the first electrode and the second electrode and supplies a power supply voltage to the first electrode and the second electrode.
The semiconductor module according to claim 13 . the first cube chip includes an electrode provided on a surface that is pressed against the first surface and a surface that is different from the surface that is pressed against the first surface,
a surface to be pressure-bonded to the first surface is disposed at a predetermined position on the first substrate via the frame;
the first cube chip is not electrically or mechanically connected to the first substrate, and is electrically connected to an external circuit via the electrodes;
The semiconductor module according to claim 1 . a first substrate including a first surface parallel to a first direction and a second direction intersecting the first direction;
a frame disposed on the first surface along a third direction intersecting the first direction and the second direction;
a cube chip attached to the frame, arranged on the first surface along the third direction, and including a plurality of stacked IC chips,
The manufacturing method includes:
forming the frame on the first surface; and
rotating the cube chip and placing it on the frame and the first surface so that a first inclined portion included in the frame and a second inclined portion included in the cube chip are fitted together;
A method for manufacturing a semiconductor module, comprising: The method for manufacturing a semiconductor module described in claim 16 further includes vibrating the first substrate to position the cube chip on the frame and the first surface.